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2 changed files with 21 additions and 72 deletions
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43
src/cpu.zig
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@ -137,49 +137,6 @@ pub const Arm7tdmi = struct {
self.changeMode(mode); self.changeMode(mode);
} }
pub fn setUserModeRegister(self: *Self, idx: usize, value: u32) void {
const current = getMode(self.cpsr.mode.read()) orelse unreachable;
if (idx < 8) {
self.r[idx] = value;
} else if (idx < 13) {
if (current == .Fiq) {
const user_offset: usize = 0;
self.banked_fiq[(idx - 8) * 2 + user_offset] = value;
} else self.r[idx] = value;
} else if (idx < 15) {
switch (current) {
.User, .System => self.r[idx] = value,
else => {
self.banked_r[bankedIdx(.User) * 2 + (idx - 13)] = value;
},
}
} else self.r[idx] = value;
}
pub fn getUserModeRegister(self: *Self, idx: usize) u32 {
const current = getMode(self.cpsr.mode.read()) orelse unreachable;
var result: u32 = undefined;
if (idx < 8) {
result = self.r[idx];
} else if (idx < 13) {
if (current == .Fiq) {
const user_offset: usize = 0;
result = self.banked_fiq[(idx - 8) * 2 + user_offset];
} else result = self.r[idx];
} else if (idx < 15) {
switch (current) {
.User, .System => result = self.r[idx],
else => {
result = self.banked_r[bankedIdx(.User) * 2 + (idx - 13)];
},
}
} else result = self.r[idx];
return result;
}
pub fn changeMode(self: *Self, next: Mode) void { pub fn changeMode(self: *Self, next: Mode) void {
const now = getMode(self.cpsr.mode.read()) orelse unreachable; const now = getMode(self.cpsr.mode.read()) orelse unreachable;

50
src/cpu/arm/block_data_transfer.zig
View File

@ -7,63 +7,55 @@ const InstrFn = @import("../../cpu.zig").ArmInstrFn;
pub fn blockDataTransfer(comptime P: bool, comptime U: bool, comptime S: bool, comptime W: bool, comptime L: bool) InstrFn { pub fn blockDataTransfer(comptime P: bool, comptime U: bool, comptime S: bool, comptime W: bool, comptime L: bool) InstrFn {
return struct { return struct {
fn inner(cpu: *Arm7tdmi, bus: *Bus, opcode: u32) void { fn inner(cpu: *Arm7tdmi, bus: *Bus, opcode: u32) void {
const r15_present = opcode >> 15 & 1 == 1;
const rn = opcode >> 16 & 0xF; const rn = opcode >> 16 & 0xF;
const base = cpu.r[rn]; const base = cpu.r[rn];
const in_list = opcode >> @truncate(u4, rn) & 1 == 1; if (S and opcode >> 15 & 1 == 0) cpu.panic("[CPU] TODO: STM/LDM with S set but R15 not in transfer list", .{});
var address: u32 = base; var address: u32 = undefined;
if (U) { if (U) {
// Increment // Increment
address = if (P) base + 4 else base;
var i: u5 = 0; var i: u5 = 0;
while (i < 0x10) : (i += 1) { while (i < 0x10) : (i += 1) {
if (opcode >> i & 1 == 1) { if (opcode >> i & 1 == 1) {
if (P) address += 4; transfer(cpu, bus, i, address);
transfer(cpu, bus, r15_present, i, address); address += 4;
if (!P) address += 4;
} }
} }
} else { } else {
// Decrement // Decrement
address = if (P) base - 4 else base;
var i: u5 = 0x10; var i: u5 = 0x10;
while (i > 0) : (i -= 1) { while (i > 0) : (i -= 1) {
const j = i - 1; const j = i - 1;
if (opcode >> j & 1 == 1) { if (opcode >> j & 1 == 1) {
if (P) address -= 4; transfer(cpu, bus, j, address);
transfer(cpu, bus, r15_present, j, address); address -= 4;
if (!P) address -= 4;
} }
} }
} }
if (W) { if (W and P or !P) cpu.r[rn] = if (U) address else address + 4;
if (!L or (L and !in_list)) {
cpu.r[rn] = address;
}
}
} }
fn transfer(cpu: *Arm7tdmi, bus: *Bus, r15_present: bool, i: u5, address: u32) void { fn transfer(cpu: *Arm7tdmi, bus: *Bus, i: u5, address: u32) void {
if (L) { if (L) {
if (S and !r15_present) { cpu.r[i] = bus.read32(address);
// Always Transfer User mode Registers if (S and i == 0xF) cpu.panic("[CPU] TODO: SPSR_<mode> is transferred to CPSR", .{});
cpu.setUserModeRegister(i, bus.read32(address));
} else {
const value = bus.read32(address);
cpu.r[i] = if (i == 0xF) value & 0xFFFF_FFFC else value;
if (S and i == 0xF) cpu.setCpsr(cpu.spsr.raw);
}
} else { } else {
if (S) { if (i == 0xF) {
// Always Transfer User mode Registers if (!S) {
// This happens regardless if r15 is in the list // TODO: Assure that this is Address of STM instruction + 12
const value = cpu.getUserModeRegister(i); bus.write32(address, cpu.r[i] + (12 - 4));
bus.write32(address, value + if (i == 0xF) 8 else @as(u32, 0)); // PC is already 4 ahead to make 12 } else {
cpu.panic("[CPU] TODO: STM with S set and R15 in transfer list", .{});
}
} else { } else {
bus.write32(address, cpu.r[i] + if (i == 0xF) 8 else @as(u32, 0)); bus.write32(address, cpu.r[i]);
} }
} }
} }