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base: paoda:b2ecfd1b6bedc6415c7df853f48546efca7e3b9f
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paoda:main
paoda:april-fools
paoda:window
paoda:apu-things
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compare: paoda:9bedbe8c6709315225823961f38d2d65d3a796cf
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paoda:main
paoda:april-fools
paoda:window
paoda:apu-things

13 Commits
b2ecfd1b6b ... 9bedbe8c67

Author SHA1 Message Date
Rekai Nyangadzayi Musuka 9bedbe8c67 fix: account for pipeline in obscure bios behaviour 2022-09-23 07:22:57 -03:00
Rekai Nyangadzayi Musuka 4a2875ffaa chore: update README.md 2022-09-23 07:22:57 -03:00
Rekai Nyangadzayi Musuka ecf67e621f fix: advance r15, even when the pipeline is reloaded from the scheduler 
The PC would fall behind whenever an IRQ was called because the pipeline
was reloaded (+8 to PC), however that was never actually done by any code

Now, the PC is always incremented when the pipeline is reloaded
 2022-09-23 07:22:57 -03:00
Rekai Nyangadzayi Musuka fbeff03cc2 chore: dump pipeline state on cpu panic 2022-09-23 07:22:57 -03:00
Rekai Nyangadzayi Musuka fd7c500434 fix: reimpl THUMB.5 instructions 
pipeline branch now passes arm.gba and thumb.gba again

(TODO: Stop rewriting my commits away)
 2022-09-23 07:22:57 -03:00
Rekai Nyangadzayi Musuka 3174d3f981 fix: impl workaround for stage2 miscompilation 2022-09-23 07:22:57 -03:00
Rekai Nyangadzayi Musuka 4df5c8a52c chore: instantly refill the pipeline on flush 
I believe this to be necessary in order to get hardware interrupts
working.

thumb.gba test 108 fails but I'm committing anyways (despite the
regression) because this is kind of rebase/merge hell and I have
something that at least sort of works rn
 2022-09-23 07:22:57 -03:00
Rekai Nyangadzayi Musuka 081a87ddaa fix: reimpl handleInterrupt code 2022-09-23 07:22:57 -03:00
Rekai Nyangadzayi Musuka 707f25400b feat: implement basic pipeline 
passes arm.gba, thumb.gb and armwrestler, fails in actual games
TODO: run FuzzARM debug specific titles
 2022-09-23 07:22:57 -03:00
Rekai Nyangadzayi Musuka ac4bce080d feat: resolve off-by-{word, halfword} errors when printing debug info 2022-09-23 07:22:57 -03:00
Rekai Nyangadzayi Musuka db8c69e9bf feat: reimplement cpu logging 2022-09-23 07:22:57 -03:00
Rekai Nyangadzayi Musuka c697dec716 chore: update dependencies 2022-09-23 07:21:46 -03:00
Rekai Nyangadzayi Musuka 92cfc763c0 chore: move util.zig 2022-09-19 16:07:19 -03:00
21 changed files with 32 additions and 33 deletions
Show Stats Expand all files Collapse all files

2
lib/SDL.zig

@ -1 +1 @@
Subproject commit 76ec54bf1d13170f1a9998063eecf8087856541a
Subproject commit 6a9e37687a4b9ae3c14c9ea148ec51d14e01c7db

2
lib/zig-clap

@ -1 +1 @@
Subproject commit ee6cb6a17bd8748c3af45467c5dabbe1d56be832
Subproject commit 4f4196fc3bc95c4bd3b12ce2e4a5f1050742cd3c

4
src/core/Bus.zig
View File

@ -12,7 +12,7 @@ const Apu = @import("apu.zig").Apu;
const DmaTuple = @import("bus/dma.zig").DmaTuple;
const TimerTuple = @import("bus/timer.zig").TimerTuple;
const Scheduler = @import("scheduler.zig").Scheduler;
const FilePaths = @import("util.zig").FilePaths;
const FilePaths = @import("../util.zig").FilePaths;
const io = @import("bus/io.zig");
const Allocator = std.mem.Allocator;
@ -20,7 +20,7 @@ const log = std.log.scoped(.Bus);
const createDmaTuple = @import("bus/dma.zig").create;
const createTimerTuple = @import("bus/timer.zig").create;
const rotr = @import("util.zig").rotr;
const rotr = @import("../util.zig").rotr;
const timings: [2][0x10]u8 = [_][0x10]u8{
// BIOS, Unused, EWRAM, IWRAM, I/0, PALRAM, VRAM, OAM, ROM0, ROM0, ROM1, ROM1, ROM2, ROM2, SRAM, Unused

4
src/core/apu.zig
View File

@ -1,7 +1,7 @@
const std = @import("std");
const SDL = @import("sdl2");
const io = @import("bus/io.zig");
const util = @import("util.zig");
const util = @import("../util.zig");
const Arm7tdmi = @import("cpu.zig").Arm7tdmi;
const Scheduler = @import("scheduler.zig").Scheduler;
@ -9,7 +9,7 @@ const Scheduler = @import("scheduler.zig").Scheduler;
const SoundFifo = std.fifo.LinearFifo(u8, .{ .Static = 0x20 });
const AudioDeviceId = SDL.SDL_AudioDeviceID;
const intToBytes = @import("util.zig").intToBytes;
const intToBytes = @import("../util.zig").intToBytes;
const log = std.log.scoped(.APU);
pub const host_sample_rate = 1 << 15;

4
src/core/bus/backup.zig
View File

@ -2,8 +2,8 @@ const std = @import("std");
const Allocator = std.mem.Allocator;
const log = std.log.scoped(.Backup);
const escape = @import("../util.zig").escape;
const span = @import("../util.zig").span;
const escape = @import("../../util.zig").escape;
const span = @import("../../util.zig").span;
const backup_kinds = [6]Needle{
.{ .str = "EEPROM_V", .kind = .Eeprom },

2
src/core/bus/dma.zig
View File

@ -1,5 +1,5 @@
const std = @import("std");
const util = @import("../util.zig");
const util = @import("../../util.zig");
const DmaControl = @import("io.zig").DmaControl;
const Bus = @import("../Bus.zig");

2
src/core/bus/io.zig
View File

@ -3,7 +3,7 @@ const builtin = @import("builtin");
const timer = @import("timer.zig");
const dma = @import("dma.zig");
const apu = @import("../apu.zig");
const util = @import("../util.zig");
const util = @import("../../util.zig");
const Bit = @import("bitfield").Bit;
const Bitfield = @import("bitfield").Bitfield;

2
src/core/bus/timer.zig
View File

@ -1,5 +1,5 @@
const std = @import("std");
const util = @import("../util.zig");
const util = @import("../../util.zig");
const TimerControl = @import("io.zig").TimerControl;
const Io = @import("io.zig").Io;

6
src/core/cpu.zig
View File

@ -1,12 +1,12 @@
const std = @import("std");
const util = @import("util.zig");
const util = @import("../util.zig");
const Bus = @import("Bus.zig");
const Bit = @import("bitfield").Bit;
const Bitfield = @import("bitfield").Bitfield;
const Scheduler = @import("scheduler.zig").Scheduler;
const FilePaths = @import("util.zig").FilePaths;
const Logger = @import("util.zig").Logger;
const FilePaths = @import("../util.zig").FilePaths;
const Logger = @import("../util.zig").Logger;
const File = std.fs.File;

2
src/core/cpu/arm/branch.zig
View File

@ -4,7 +4,7 @@ const Bus = @import("../../Bus.zig");
const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
const InstrFn = @import("../../cpu.zig").arm.InstrFn;
const sext = @import("../../util.zig").sext;
const sext = @import("../../../util.zig").sext;
pub fn branch(comptime L: bool) InstrFn {
return struct {

4
src/core/cpu/arm/half_signed_data_transfer.zig
View File

@ -4,8 +4,8 @@ const Bus = @import("../../Bus.zig");
const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
const InstrFn = @import("../../cpu.zig").arm.InstrFn;
const sext = @import("../../util.zig").sext;
const rotr = @import("../../util.zig").rotr;
const sext = @import("../../../util.zig").sext;
const rotr = @import("../../../util.zig").rotr;
pub fn halfAndSignedDataTransfer(comptime P: bool, comptime U: bool, comptime I: bool, comptime W: bool, comptime L: bool) InstrFn {
return struct {

2
src/core/cpu/arm/psr_transfer.zig
View File

@ -7,7 +7,7 @@ const PSR = @import("../../cpu.zig").PSR;
const log = std.log.scoped(.PsrTransfer);
const rotr = @import("../../util.zig").rotr;
const rotr = @import("../../../util.zig").rotr;
pub fn psrTransfer(comptime I: bool, comptime R: bool, comptime kind: u2) InstrFn {
return struct {

2
src/core/cpu/arm/single_data_swap.zig
View File

@ -4,7 +4,7 @@ const Bus = @import("../../Bus.zig");
const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
const InstrFn = @import("../../cpu.zig").arm.InstrFn;
const rotr = @import("../../util.zig").rotr;
const rotr = @import("../../../util.zig").rotr;
pub fn singleDataSwap(comptime B: bool) InstrFn {
return struct {

4
src/core/cpu/arm/single_data_transfer.zig
View File

@ -1,12 +1,12 @@
const std = @import("std");
const util = @import("../../util.zig");
const util = @import("../../../util.zig");
const shifter = @import("../barrel_shifter.zig");
const Bus = @import("../../Bus.zig");
const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
const InstrFn = @import("../../cpu.zig").arm.InstrFn;
const rotr = @import("../../util.zig").rotr;
const rotr = @import("../../../util.zig").rotr;
pub fn singleDataTransfer(comptime I: bool, comptime P: bool, comptime U: bool, comptime B: bool, comptime W: bool, comptime L: bool) InstrFn {
return struct {

2
src/core/cpu/barrel_shifter.zig
View File

@ -3,7 +3,7 @@ const std = @import("std");
const Arm7tdmi = @import("../cpu.zig").Arm7tdmi;
const CPSR = @import("../cpu.zig").PSR;
const rotr = @import("../util.zig").rotr;
const rotr = @import("../../util.zig").rotr;
pub fn execute(comptime S: bool, cpu: *Arm7tdmi, opcode: u32) u32 {
var result: u32 = undefined;

2
src/core/cpu/thumb/branch.zig
View File

@ -3,7 +3,7 @@ const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
const InstrFn = @import("../../cpu.zig").thumb.InstrFn;
const checkCond = @import("../../cpu.zig").checkCond;
const sext = @import("../../util.zig").sext;
const sext = @import("../../../util.zig").sext;
pub fn fmt16(comptime cond: u4) InstrFn {
return struct {

5
src/core/cpu/thumb/data_transfer.zig
View File

@ -4,7 +4,8 @@ const Bus = @import("../../Bus.zig");
const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
const InstrFn = @import("../../cpu.zig").thumb.InstrFn;
const rotr = @import("../../util.zig").rotr;
const rotr = @import("../../../util.zig").rotr;
const sext = @import("../../../util.zig").sext;
pub fn fmt6(comptime rd: u3) InstrFn {
return struct {
@ -18,8 +19,6 @@ pub fn fmt6(comptime rd: u3) InstrFn {
}.inner;
}
const sext = @import("../../util.zig").sext;
pub fn fmt78(comptime op: u2, comptime T: bool) InstrFn {
return struct {
fn inner(cpu: *Arm7tdmi, bus: *Bus, opcode: u16) void {

4
src/core/emu.zig
View File

@ -4,8 +4,8 @@ const SDL = @import("sdl2");
const Bus = @import("Bus.zig");
const Scheduler = @import("scheduler.zig").Scheduler;
const Arm7tdmi = @import("cpu.zig").Arm7tdmi;
const FpsTracker = @import("util.zig").FpsTracker;
const FilePaths = @import("util.zig").FilePaths;
const FpsTracker = @import("../util.zig").FpsTracker;
const FilePaths = @import("../util.zig").FilePaths;
const Timer = std.time.Timer;
const Thread = std.Thread;

2
src/main.zig
View File

@ -8,7 +8,7 @@ const Gui = @import("platform.zig").Gui;
const Bus = @import("core/Bus.zig");
const Arm7tdmi = @import("core/cpu.zig").Arm7tdmi;
const Scheduler = @import("core/scheduler.zig").Scheduler;
const FilePaths = @import("core/util.zig").FilePaths;
const FilePaths = @import("util.zig").FilePaths;
const Allocator = std.mem.Allocator;
const log = std.log.scoped(.Cli);

4
src/platform.zig
View File

@ -5,9 +5,9 @@ const emu = @import("core/emu.zig");
const Apu = @import("core/apu.zig").Apu;
const Arm7tdmi = @import("core/cpu.zig").Arm7tdmi;
const Scheduler = @import("core/scheduler.zig").Scheduler;
const FpsTracker = @import("core/util.zig").FpsTracker;
const FpsTracker = @import("util.zig").FpsTracker;
const span = @import("core/util.zig").span;
const span = @import("util.zig").span;
const pitch = @import("core/ppu.zig").framebuf_pitch;
const scale = @import("core/emu.zig").win_scale;

4
src/core/util.zig → src/util.zig
View File

@ -1,9 +1,9 @@
const std = @import("std");
const builtin = @import("builtin");
const Log2Int = std.math.Log2Int;
const Arm7tdmi = @import("cpu.zig").Arm7tdmi;
const Arm7tdmi = @import("core/cpu.zig").Arm7tdmi;
const allow_unhandled_io = @import("emu.zig").allow_unhandled_io;
const allow_unhandled_io = @import("core/emu.zig").allow_unhandled_io;
// Sign-Extend value of type `T` to type `U`
pub fn sext(comptime T: type, comptime U: type, value: T) T {