fix: account for pipeline in obscure bios behaviour

The PC would fall behind whenever an IRQ was called because the pipeline
was reloaded (+8 to PC), however that was never actually done by any code

Now, the PC is always incremented when the pipeline is reloaded

lib/SDL.zig

@@ -1 +1 @@
-Subproject commit 76ec54bf1d13170f1a9998063eecf8087856541a
+Subproject commit 6a9e37687a4b9ae3c14c9ea148ec51d14e01c7db

lib/zig-clap

@@ -1 +1 @@
-Subproject commit ee6cb6a17bd8748c3af45467c5dabbe1d56be832
+Subproject commit 4f4196fc3bc95c4bd3b12ce2e4a5f1050742cd3c

src/core/Bus.zig

@@ -12,7 +12,7 @@ const Apu = @import("apu.zig").Apu;
 const DmaTuple = @import("bus/dma.zig").DmaTuple;
 const TimerTuple = @import("bus/timer.zig").TimerTuple;
 const Scheduler = @import("scheduler.zig").Scheduler;
-const FilePaths = @import("util.zig").FilePaths;
+const FilePaths = @import("../util.zig").FilePaths;
 
 const io = @import("bus/io.zig");
 const Allocator = std.mem.Allocator;
@@ -20,7 +20,7 @@ const log = std.log.scoped(.Bus);
 
 const createDmaTuple = @import("bus/dma.zig").create;
 const createTimerTuple = @import("bus/timer.zig").create;
-const rotr = @import("util.zig").rotr;
+const rotr = @import("../util.zig").rotr;
 
 const timings: [2][0x10]u8 = [_][0x10]u8{
     // BIOS, Unused, EWRAM, IWRAM, I/0, PALRAM, VRAM, OAM, ROM0, ROM0, ROM1, ROM1, ROM2, ROM2, SRAM, Unused

src/core/apu.zig

@@ -1,7 +1,7 @@
 const std = @import("std");
 const SDL = @import("sdl2");
 const io = @import("bus/io.zig");
-const util = @import("util.zig");
+const util = @import("../util.zig");
 
 const Arm7tdmi = @import("cpu.zig").Arm7tdmi;
 const Scheduler = @import("scheduler.zig").Scheduler;
@@ -9,7 +9,7 @@ const Scheduler = @import("scheduler.zig").Scheduler;
 const SoundFifo = std.fifo.LinearFifo(u8, .{ .Static = 0x20 });
 const AudioDeviceId = SDL.SDL_AudioDeviceID;
 
-const intToBytes = @import("util.zig").intToBytes;
+const intToBytes = @import("../util.zig").intToBytes;
 const log = std.log.scoped(.APU);
 
 pub const host_sample_rate = 1 << 15;

src/core/bus/backup.zig

@@ -2,8 +2,8 @@ const std = @import("std");
 const Allocator = std.mem.Allocator;
 const log = std.log.scoped(.Backup);
 
-const escape = @import("../util.zig").escape;
+const escape = @import("../../util.zig").escape;
-const span = @import("../util.zig").span;
+const span = @import("../../util.zig").span;
 
 const backup_kinds = [6]Needle{
     .{ .str = "EEPROM_V", .kind = .Eeprom },

src/core/bus/dma.zig

@@ -1,5 +1,5 @@
 const std = @import("std");
-const util = @import("../util.zig");
+const util = @import("../../util.zig");
 
 const DmaControl = @import("io.zig").DmaControl;
 const Bus = @import("../Bus.zig");

src/core/bus/io.zig

@@ -3,7 +3,7 @@ const builtin = @import("builtin");
 const timer = @import("timer.zig");
 const dma = @import("dma.zig");
 const apu = @import("../apu.zig");
-const util = @import("../util.zig");
+const util = @import("../../util.zig");
 
 const Bit = @import("bitfield").Bit;
 const Bitfield = @import("bitfield").Bitfield;

src/core/bus/timer.zig

@@ -1,5 +1,5 @@
 const std = @import("std");
-const util = @import("../util.zig");
+const util = @import("../../util.zig");
 
 const TimerControl = @import("io.zig").TimerControl;
 const Io = @import("io.zig").Io;

src/core/cpu.zig

@@ -1,12 +1,12 @@
 const std = @import("std");
-const util = @import("util.zig");
+const util = @import("../util.zig");
 
 const Bus = @import("Bus.zig");
 const Bit = @import("bitfield").Bit;
 const Bitfield = @import("bitfield").Bitfield;
 const Scheduler = @import("scheduler.zig").Scheduler;
-const FilePaths = @import("util.zig").FilePaths;
+const FilePaths = @import("../util.zig").FilePaths;
-const Logger = @import("util.zig").Logger;
+const Logger = @import("../util.zig").Logger;
 
 const File = std.fs.File;
 

src/core/cpu/arm/branch.zig

@@ -4,7 +4,7 @@ const Bus = @import("../../Bus.zig");
 const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
 const InstrFn = @import("../../cpu.zig").arm.InstrFn;
 
-const sext = @import("../../util.zig").sext;
+const sext = @import("../../../util.zig").sext;
 
 pub fn branch(comptime L: bool) InstrFn {
     return struct {

src/core/cpu/arm/half_signed_data_transfer.zig

@@ -4,8 +4,8 @@ const Bus = @import("../../Bus.zig");
 const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
 const InstrFn = @import("../../cpu.zig").arm.InstrFn;
 
-const sext = @import("../../util.zig").sext;
+const sext = @import("../../../util.zig").sext;
-const rotr = @import("../../util.zig").rotr;
+const rotr = @import("../../../util.zig").rotr;
 
 pub fn halfAndSignedDataTransfer(comptime P: bool, comptime U: bool, comptime I: bool, comptime W: bool, comptime L: bool) InstrFn {
     return struct {

src/core/cpu/arm/psr_transfer.zig

@@ -7,7 +7,7 @@ const PSR = @import("../../cpu.zig").PSR;
 
 const log = std.log.scoped(.PsrTransfer);
 
-const rotr = @import("../../util.zig").rotr;
+const rotr = @import("../../../util.zig").rotr;
 
 pub fn psrTransfer(comptime I: bool, comptime R: bool, comptime kind: u2) InstrFn {
     return struct {

src/core/cpu/arm/single_data_swap.zig

@@ -4,7 +4,7 @@ const Bus = @import("../../Bus.zig");
 const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
 const InstrFn = @import("../../cpu.zig").arm.InstrFn;
 
-const rotr = @import("../../util.zig").rotr;
+const rotr = @import("../../../util.zig").rotr;
 
 pub fn singleDataSwap(comptime B: bool) InstrFn {
     return struct {

src/core/cpu/arm/single_data_transfer.zig

@@ -1,12 +1,12 @@
 const std = @import("std");
-const util = @import("../../util.zig");
+const util = @import("../../../util.zig");
 
 const shifter = @import("../barrel_shifter.zig");
 const Bus = @import("../../Bus.zig");
 const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
 const InstrFn = @import("../../cpu.zig").arm.InstrFn;
 
-const rotr = @import("../../util.zig").rotr;
+const rotr = @import("../../../util.zig").rotr;
 
 pub fn singleDataTransfer(comptime I: bool, comptime P: bool, comptime U: bool, comptime B: bool, comptime W: bool, comptime L: bool) InstrFn {
     return struct {

src/core/cpu/barrel_shifter.zig

@@ -3,7 +3,7 @@ const std = @import("std");
 const Arm7tdmi = @import("../cpu.zig").Arm7tdmi;
 const CPSR = @import("../cpu.zig").PSR;
 
-const rotr = @import("../util.zig").rotr;
+const rotr = @import("../../util.zig").rotr;
 
 pub fn execute(comptime S: bool, cpu: *Arm7tdmi, opcode: u32) u32 {
     var result: u32 = undefined;

src/core/cpu/thumb/branch.zig

@@ -3,7 +3,7 @@ const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
 const InstrFn = @import("../../cpu.zig").thumb.InstrFn;
 
 const checkCond = @import("../../cpu.zig").checkCond;
-const sext = @import("../../util.zig").sext;
+const sext = @import("../../../util.zig").sext;
 
 pub fn fmt16(comptime cond: u4) InstrFn {
     return struct {

src/core/cpu/thumb/data_transfer.zig

@@ -4,7 +4,8 @@ const Bus = @import("../../Bus.zig");
 const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
 const InstrFn = @import("../../cpu.zig").thumb.InstrFn;
 
-const rotr = @import("../../util.zig").rotr;
+const rotr = @import("../../../util.zig").rotr;
+const sext = @import("../../../util.zig").sext;
 
 pub fn fmt6(comptime rd: u3) InstrFn {
     return struct {
@@ -18,8 +19,6 @@ pub fn fmt6(comptime rd: u3) InstrFn {
     }.inner;
 }
 
-const sext = @import("../../util.zig").sext;
-
 pub fn fmt78(comptime op: u2, comptime T: bool) InstrFn {
     return struct {
         fn inner(cpu: *Arm7tdmi, bus: *Bus, opcode: u16) void {

src/core/emu.zig

@@ -4,8 +4,8 @@ const SDL = @import("sdl2");
 const Bus = @import("Bus.zig");
 const Scheduler = @import("scheduler.zig").Scheduler;
 const Arm7tdmi = @import("cpu.zig").Arm7tdmi;
-const FpsTracker = @import("util.zig").FpsTracker;
+const FpsTracker = @import("../util.zig").FpsTracker;
-const FilePaths = @import("util.zig").FilePaths;
+const FilePaths = @import("../util.zig").FilePaths;
 
 const Timer = std.time.Timer;
 const Thread = std.Thread;

src/main.zig

@@ -8,7 +8,7 @@ const Gui = @import("platform.zig").Gui;
 const Bus = @import("core/Bus.zig");
 const Arm7tdmi = @import("core/cpu.zig").Arm7tdmi;
 const Scheduler = @import("core/scheduler.zig").Scheduler;
-const FilePaths = @import("core/util.zig").FilePaths;
+const FilePaths = @import("util.zig").FilePaths;
 
 const Allocator = std.mem.Allocator;
 const log = std.log.scoped(.Cli);

src/platform.zig

@@ -5,9 +5,9 @@ const emu = @import("core/emu.zig");
 const Apu = @import("core/apu.zig").Apu;
 const Arm7tdmi = @import("core/cpu.zig").Arm7tdmi;
 const Scheduler = @import("core/scheduler.zig").Scheduler;
-const FpsTracker = @import("core/util.zig").FpsTracker;
+const FpsTracker = @import("util.zig").FpsTracker;
 
-const span = @import("core/util.zig").span;
+const span = @import("util.zig").span;
 
 const pitch = @import("core/ppu.zig").framebuf_pitch;
 const scale = @import("core/emu.zig").win_scale;

src/util.zig

@@ -1,9 +1,9 @@
 const std = @import("std");
 const builtin = @import("builtin");
 const Log2Int = std.math.Log2Int;
-const Arm7tdmi = @import("cpu.zig").Arm7tdmi;
+const Arm7tdmi = @import("core/cpu.zig").Arm7tdmi;
 
-const allow_unhandled_io = @import("emu.zig").allow_unhandled_io;
+const allow_unhandled_io = @import("core/emu.zig").allow_unhandled_io;
 
 // Sign-Extend value of type `T` to type `U`
 pub fn sext(comptime T: type, comptime U: type, value: T) T {