src/core/Bus.zig

@@ -73,31 +73,31 @@ pub fn deinit(self: *Self) void {
     self.* = undefined;
 }
 
-pub fn dbgRead(self: *const Self, comptime T: type, unaligned_address: u32) T {
+pub fn dbgRead(self: *const Self, comptime T: type, address: u32) T {
-    const page = @truncate(u8, unaligned_address >> 24);
+    const page = @truncate(u8, address >> 24);
-    const address = forceAlign(T, unaligned_address);
+    const aligned_addr = forceAlign(T, address);
 
     return switch (page) {
         // General Internal Memory
         0x00 => blk: {
             if (address < Bios.size)
-                break :blk self.bios.dbgRead(T, self.cpu.r[15], address);
+                break :blk self.bios.dbgRead(T, self.cpu.r[15], aligned_addr);
 
             break :blk self.openBus(T, address);
         },
-        0x02 => self.ewram.read(T, address),
+        0x02 => self.ewram.read(T, aligned_addr),
-        0x03 => self.iwram.read(T, address),
+        0x03 => self.iwram.read(T, aligned_addr),
         0x04 => self.readIo(T, address),
 
         // Internal Display Memory
-        0x05 => self.ppu.palette.read(T, address),
+        0x05 => self.ppu.palette.read(T, aligned_addr),
-        0x06 => self.ppu.vram.read(T, address),
+        0x06 => self.ppu.vram.read(T, aligned_addr),
-        0x07 => self.ppu.oam.read(T, address),
+        0x07 => self.ppu.oam.read(T, aligned_addr),
 
         // External Memory (Game Pak)
-        0x08...0x0D => self.pak.dbgRead(T, address),
+        0x08...0x0D => self.pak.dbgRead(T, aligned_addr),
         0x0E...0x0F => blk: {
-            const value = self.pak.backup.read(unaligned_address);
+            const value = self.pak.backup.read(address);
 
             const multiplier = switch (T) {
                 u32 => 0x01010101,
@@ -112,8 +112,10 @@ pub fn dbgRead(self: *const Self, comptime T: type, unaligned_address: u32) T {
     };
 }
 
-fn readIo(self: *const Self, comptime T: type, address: u32) T {
+/// TODO: Should open bus read addresses be force-aligned?
-    return io.read(self, T, address) orelse self.openBus(T, address);
+fn readIo(self: *const Self, comptime T: type, unaligned_address: u32) T {
+    const maybe_value = io.read(self, T, forceAlign(T, unaligned_address));
+    return if (maybe_value) |value| value else self.openBus(T, unaligned_address);
 }
 
 fn openBus(self: *const Self, comptime T: type, address: u32) T {
@@ -121,12 +123,6 @@ fn openBus(self: *const Self, comptime T: type, address: u32) T {
 
     const word = blk: {
         // If Arm, get the most recently fetched instruction (PC + 8)
-        //
-        // FIXME: This is most likely a faulty assumption.
-        // I think what *actually* happens is that the Bus has a latch for the most
-        // recently fetched piece of data, which is then returned during Open Bus (also DMA open bus?)
-        // I can "get away" with this because it's very statistically likely that the most recently latched value is
-        // the most recently fetched instruction by the pipeline
         if (!self.cpu.cpsr.t.read()) break :blk self.cpu.pipe.stage[1].?;
 
         const page = @truncate(u8, r15 >> 24);
@@ -176,9 +172,9 @@ fn openBus(self: *const Self, comptime T: type, address: u32) T {
     return @truncate(T, word);
 }
 
-pub fn read(self: *Self, comptime T: type, unaligned_address: u32) T {
+pub fn read(self: *Self, comptime T: type, address: u32) T {
-    const page = @truncate(u8, unaligned_address >> 24);
+    const page = @truncate(u8, address >> 24);
-    const address = forceAlign(T, unaligned_address);
+    const aligned_addr = forceAlign(T, address);
 
     self.sched.tick += timings[@boolToInt(T == u32)][@truncate(u4, page)];
 
@@ -186,23 +182,23 @@ pub fn read(self: *Self, comptime T: type, unaligned_address: u32) T {
         // General Internal Memory
         0x00 => blk: {
             if (address < Bios.size)
-                break :blk self.bios.read(T, self.cpu.r[15], address);
+                break :blk self.bios.read(T, self.cpu.r[15], aligned_addr);
 
             break :blk self.openBus(T, address);
         },
-        0x02 => self.ewram.read(T, address),
+        0x02 => self.ewram.read(T, aligned_addr),
-        0x03 => self.iwram.read(T, address),
+        0x03 => self.iwram.read(T, aligned_addr),
         0x04 => self.readIo(T, address),
 
         // Internal Display Memory
-        0x05 => self.ppu.palette.read(T, address),
+        0x05 => self.ppu.palette.read(T, aligned_addr),
-        0x06 => self.ppu.vram.read(T, address),
+        0x06 => self.ppu.vram.read(T, aligned_addr),
-        0x07 => self.ppu.oam.read(T, address),
+        0x07 => self.ppu.oam.read(T, aligned_addr),
 
         // External Memory (Game Pak)
-        0x08...0x0D => self.pak.read(T, address),
+        0x08...0x0D => self.pak.read(T, aligned_addr),
         0x0E...0x0F => blk: {
-            const value = self.pak.backup.read(unaligned_address);
+            const value = self.pak.backup.read(address);
 
             const multiplier = switch (T) {
                 u32 => 0x01010101,
@@ -217,44 +213,44 @@ pub fn read(self: *Self, comptime T: type, unaligned_address: u32) T {
     };
 }
 
-pub fn write(self: *Self, comptime T: type, unaligned_address: u32, value: T) void {
+pub fn write(self: *Self, comptime T: type, address: u32, value: T) void {
-    const page = @truncate(u8, unaligned_address >> 24);
+    const page = @truncate(u8, address >> 24);
-    const address = forceAlign(T, unaligned_address);
+    const aligned_addr = forceAlign(T, address);
 
     self.sched.tick += timings[@boolToInt(T == u32)][@truncate(u4, page)];
 
     switch (page) {
         // General Internal Memory
-        0x00 => self.bios.write(T, address, value),
+        0x00 => self.bios.write(T, aligned_addr, value),
-        0x02 => self.ewram.write(T, address, value),
+        0x02 => self.ewram.write(T, aligned_addr, value),
-        0x03 => self.iwram.write(T, address, value),
+        0x03 => self.iwram.write(T, aligned_addr, value),
-        0x04 => io.write(self, T, address, value),
+        0x04 => io.write(self, T, aligned_addr, value),
 
         // Internal Display Memory
-        0x05 => self.ppu.palette.write(T, address, value),
+        0x05 => self.ppu.palette.write(T, aligned_addr, value),
-        0x06 => self.ppu.vram.write(T, self.ppu.dispcnt, address, value),
+        0x06 => self.ppu.vram.write(T, self.ppu.dispcnt, aligned_addr, value),
-        0x07 => self.ppu.oam.write(T, address, value),
+        0x07 => self.ppu.oam.write(T, aligned_addr, value),
 
         // External Memory (Game Pak)
-        0x08...0x0D => self.pak.write(T, self.dma[3].word_count, address, value),
+        0x08...0x0D => self.pak.write(T, self.dma[3].word_count, aligned_addr, value),
-        0x0E...0x0F => self.pak.backup.write(unaligned_address, @truncate(u8, rotr(T, value, 8 * rotateBy(T, unaligned_address)))),
+        0x0E...0x0F => {
-        else => {},
+            const rotate_by = switch (T) {
-    }
-}
-
-inline fn rotateBy(comptime T: type, address: u32) u32 {
-    return switch (T) {
                 u32 => address & 3,
                 u16 => address & 1,
                 u8 => 0,
                 else => @compileError("Backup: Unsupported write width"),
             };
+
+            self.pak.backup.write(address, @truncate(u8, rotr(T, value, 8 * rotate_by)));
+        },
+        else => {},
+    }
 }
 
-inline fn forceAlign(comptime T: type, address: u32) u32 {
+fn forceAlign(comptime T: type, address: u32) u32 {
     return switch (T) {
-        u32 => address & ~@as(u32, 3),
+        u32 => address & 0xFFFF_FFFC,
-        u16 => address & ~@as(u32, 1),
+        u16 => address & 0xFFFF_FFFE,
         u8 => address,
         else => @compileError("Bus: Invalid read/write type"),
     };

src/core/apu.zig

@@ -407,6 +407,7 @@ pub const Apu = struct {
         const ext_left = (clamped_left << 5) | (clamped_left >> 6);
         const ext_right = (clamped_right << 5) | (clamped_right >> 6);
 
+        // FIXME: This rarely happens
         if (self.sampling_cycle != self.bias.sampling_cycle.read()) self.replaceSDLResampler();
 
         _ = SDL.SDL_AudioStreamPut(self.stream, &[2]u16{ ext_left, ext_right }, 2 * @sizeOf(u16));
@@ -506,6 +507,7 @@ pub fn DmaSound(comptime kind: DmaSoundKind) type {
         }
 
         pub fn push(self: *Self, value: u32) void {
+            // FIXME: I tried to communicate that this is unlikely to the compiler
             if (!self.enabled) self.enable();
 
             self.fifo.write(&intToBytes(u32, value)) catch |e| log.err("{} Error: {}", .{ kind, e });

src/core/apu/signal/Lfsr.zig

@@ -33,7 +33,7 @@ pub fn reload(self: *Self, poly: io.PolyCounter) void {
 }
 
 /// Scheduler Event Handler for LFSR Timer Expire
-/// FIXME: This gets called a lot, slowing down the scheduler
+/// FIXME: This gets called a lot, clogging up the Scheduler
 pub fn onLfsrTimerExpire(self: *Self, poly: io.PolyCounter, late: u64) void {
     // Obscure: "Using a noise channel clock shift of 14 or 15
     // results in the LFSR receiving no clocks."

src/core/bus/GamePak.zig

@@ -105,13 +105,14 @@ pub fn dbgRead(self: *const Self, comptime T: type, address: u32) T {
 
         switch (T) {
             u32 => switch (address) {
-                // FIXME: Do I even need to implement these?
+                // TODO: Do I even need to implement these?
                 0x0800_00C4 => std.debug.panic("Handle 32-bit GPIO Data/Direction Reads", .{}),
                 0x0800_00C6 => std.debug.panic("Handle 32-bit GPIO Direction/Control Reads", .{}),
                 0x0800_00C8 => std.debug.panic("Handle 32-bit GPIO Control Reads", .{}),
                 else => {},
             },
             u16 => switch (address) {
+                // FIXME: What do 16-bit GPIO Reads look like?
                 0x0800_00C4 => return self.gpio.read(.Data),
                 0x0800_00C6 => return self.gpio.read(.Direction),
                 0x0800_00C8 => return self.gpio.read(.Control),

src/core/bus/backup.zig

@@ -151,8 +151,8 @@ pub const Backup = struct {
         const file_path = try self.savePath(allocator, path);
         defer allocator.free(file_path);
 
-        const expected = "untitled.sav";
+        // FIXME: Don't rely on this lol
-        if (std.mem.eql(u8, file_path[file_path.len - expected.len .. file_path.len], expected)) {
+        if (std.mem.eql(u8, file_path[file_path.len - 12 .. file_path.len], "untitled.sav")) {
             return log.err("ROM header lacks title, no save loaded", .{});
         }
 

src/core/bus/backup/eeprom.zig

@@ -63,7 +63,7 @@ pub const Eeprom = struct {
         }
 
         if (self.state == .RequestEnd) {
-            // if (bit != 0) log.debug("EEPROM Request did not end in 0u1. TODO: is this ok?", .{});
+            if (bit != 0) log.debug("EEPROM Request did not end in 0u1. TODO: is this ok?", .{});
             self.state = .Ready;
             return;
         }

src/core/bus/dma.zig

@@ -259,6 +259,7 @@ fn DmaController(comptime id: u2) type {
             switch (sad_adj) {
                 .Increment => self.sad_latch +%= offset,
                 .Decrement => self.sad_latch -%= offset,
+                // FIXME: Is just ignoring this ok?
                 .IncrementReload => log.err("{} is a prohibited adjustment on SAD", .{sad_adj}),
                 .Fixed => {},
             }

src/core/bus/gpio.zig

@@ -71,7 +71,7 @@ pub const Gpio = struct {
 
         self.* = .{
             .data = 0b0000,
-            .direction = 0b1111, // TODO: What is GPIO Direction set to by default?
+            .direction = 0b1111, // TODO: What is GPIO DIrection set to by default?
             .cnt = 0b0,
 
             .device = switch (kind) {

src/core/bus/io.zig

@@ -213,7 +213,7 @@ pub fn write(bus: *Bus, comptime T: type, address: u32, value: T) void {
 
             // Timers
             0x0400_0100...0x0400_010E => timer.write(T, &bus.tim, address, value),
-            0x0400_0114 => {},
+            0x0400_0114 => {}, // TODO: Gyakuten Saiban writes 0x8000 to 0x0400_0114
             0x0400_0110 => {}, // Not Used,
 
             // Serial Communication 1

src/core/cpu/arm/block_data_transfer.zig

@@ -57,6 +57,7 @@ pub fn blockDataTransfer(comptime P: bool, comptime U: bool, comptime S: bool, c
                     cpu.r[15] = bus.read(u32, und_addr);
                     cpu.pipe.reload(cpu);
                 } else {
+                    // FIXME: Should r15 on write be +12 ahead?
                     bus.write(u32, und_addr, cpu.r[15] + 4);
                 }
 

src/util.zig

@@ -302,6 +302,8 @@ pub inline fn getHalf(byte: u8) u4 {
     return @truncate(u4, byte & 1) << 3;
 }
 
+// TODO: Maybe combine SetLo and SetHi, use addr alignment to deduplicate code
+
 pub inline fn setHalf(comptime T: type, left: T, addr: u8, right: HalfInt(T)) T {
     const offset = @truncate(u1, addr >> if (T == u32) 1 else 0);
 
@@ -318,6 +320,26 @@ pub inline fn setHalf(comptime T: type, left: T, addr: u8, right: HalfInt(T)) T
     };
 }
 
+/// Sets the high bits of an integer to a value
+pub inline fn setLo(comptime T: type, left: T, right: HalfInt(T)) T {
+    return switch (T) {
+        u32 => (left & 0xFFFF_0000) | right,
+        u16 => (left & 0xFF00) | right,
+        u8 => (left & 0xF0) | right,
+        else => @compileError("unsupported type"),
+    };
+}
+
+/// sets the low bits of an integer to a value
+pub inline fn setHi(comptime T: type, left: T, right: HalfInt(T)) T {
+    return switch (T) {
+        u32 => (left & 0x0000_FFFF) | @as(u32, right) << 16,
+        u16 => (left & 0x00FF) | @as(u16, right) << 8,
+        u8 => (left & 0x0F) | @as(u8, right) << 4,
+        else => @compileError("unsupported type"),
+    };
+}
+
 /// The Integer type which corresponds to T with exactly half the amount of bits
 fn HalfInt(comptime T: type) type {
     const type_info = @typeInfo(T);