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13 changed files with 155 additions and 356 deletions
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49
src/cpu.zig
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@ -1,6 +1,7 @@
const std = @import("std"); const std = @import("std");
const util = @import("util.zig"); const util = @import("util.zig");
const BarrelShifter = @import("cpu/arm/barrel_shifter.zig");
const Bus = @import("Bus.zig"); const Bus = @import("Bus.zig");
const Bit = @import("bitfield").Bit; const Bit = @import("bitfield").Bit;
const Bitfield = @import("bitfield").Bitfield; const Bitfield = @import("bitfield").Bitfield;
@ -19,14 +20,9 @@ const branchAndExchange = @import("cpu/arm/branch.zig").branchAndExchange;
const softwareInterrupt = @import("cpu/arm/software_interrupt.zig").softwareInterrupt; const softwareInterrupt = @import("cpu/arm/software_interrupt.zig").softwareInterrupt;
// THUMB Instruction Groups // THUMB Instruction Groups
const format1 = @import("cpu/thumb/format1.zig").format1;
const format3 = @import("cpu/thumb/format3.zig").format3; const format3 = @import("cpu/thumb/format3.zig").format3;
const format2 = @import("cpu/thumb/format2.zig").format2;
const format5 = @import("cpu/thumb/format5.zig").format5; const format5 = @import("cpu/thumb/format5.zig").format5;
const format6 = @import("cpu/thumb/format6.zig").format6;
const format12 = @import("cpu/thumb/format12.zig").format12; const format12 = @import("cpu/thumb/format12.zig").format12;
const format16 = @import("cpu/thumb/format16.zig").format16;
const format19 = @import("cpu/thumb/format19.zig").format19;
pub const ArmInstrFn = fn (*Arm7tdmi, *Bus, u32) void; pub const ArmInstrFn = fn (*Arm7tdmi, *Bus, u32) void;
pub const ThumbInstrFn = fn (*Arm7tdmi, *Bus, u16) void; pub const ThumbInstrFn = fn (*Arm7tdmi, *Bus, u16) void;
@ -273,14 +269,7 @@ pub const Arm7tdmi = struct {
var log_str: []u8 = undefined; var log_str: []u8 = undefined;
if (self.cpsr.t.read()) { if (self.cpsr.t.read()) {
if (opcode >> 11 == 0x1E) { log_str = try std.fmt.bufPrint(&buf, thumb_fmt, .{ r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r13, r14, r15, c_psr, opcode });
// Instruction 1 of a BL Opcode, print in ARM mode
const tmp_opcode = self.bus.read32(self.r[15] - 2);
const be_opcode = tmp_opcode << 16 | tmp_opcode >> 16;
log_str = try std.fmt.bufPrint(&buf, arm_fmt, .{ r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r13, r14, r15, c_psr, be_opcode });
} else {
log_str = try std.fmt.bufPrint(&buf, thumb_fmt, .{ r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r13, r14, r15, c_psr, opcode });
}
} else { } else {
log_str = try std.fmt.bufPrint(&buf, arm_fmt, .{ r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r13, r14, r15, c_psr, opcode }); log_str = try std.fmt.bufPrint(&buf, arm_fmt, .{ r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r13, r14, r15, c_psr, opcode });
} }
@ -297,7 +286,7 @@ inline fn thumbIdx(opcode: u16) u10 {
return @truncate(u10, opcode >> 6); return @truncate(u10, opcode >> 6);
} }
pub fn checkCond(cpsr: PSR, cond: u4) bool { fn checkCond(cpsr: PSR, cond: u4) bool {
// TODO: Should I implement an enum? // TODO: Should I implement an enum?
return switch (cond) { return switch (cond) {
0x0 => cpsr.z.read(), // EQ - Equal 0x0 => cpsr.z.read(), // EQ - Equal
@ -326,20 +315,6 @@ fn thumbPopulate() [0x400]ThumbInstrFn {
var i: usize = 0; var i: usize = 0;
while (i < lut.len) : (i += 1) { while (i < lut.len) : (i += 1) {
if (i >> 7 & 0x7 == 0b000) {
const op = i >> 5 & 0x3;
const offset = i & 0x1F;
lut[i] = format1(op, offset);
}
if (i >> 5 & 0x1F == 0b00011) {
const I = i >> 4 & 1 == 1;
const is_sub = i >> 3 & 1 == 1;
const rn = i & 0x7;
lut[i] = format2(I, is_sub, rn);
}
if (i >> 7 & 0x7 == 0b001) { if (i >> 7 & 0x7 == 0b001) {
const op = i >> 5 & 0x3; const op = i >> 5 & 0x3;
const rd = i >> 2 & 0x7; const rd = i >> 2 & 0x7;
@ -355,30 +330,12 @@ fn thumbPopulate() [0x400]ThumbInstrFn {
lut[i] = format5(op, h1, h2); lut[i] = format5(op, h1, h2);
} }
if (i >> 5 & 0x1F == 0b01001) {
const rd = i >> 2 & 0x7;
lut[i] = format6(rd);
}
if (i >> 6 & 0xF == 0b1010) { if (i >> 6 & 0xF == 0b1010) {
const isSP = i >> 5 & 1 == 1; const isSP = i >> 5 & 1 == 1;
const rd = i >> 2 & 0x7; const rd = i >> 2 & 0x7;
lut[i] = format12(isSP, rd); lut[i] = format12(isSP, rd);
} }
if (i >> 6 & 0xF == 0b1101) {
const cond = i >> 2 & 0xF;
lut[i] = format16(cond);
}
if (i >> 6 & 0xF == 0b1111) {
const is_low = i >> 5 & 1 == 1;
lut[i] = format19(is_low);
}
} }
return lut; return lut;

4
src/cpu/barrel_shifter.zig → src/cpu/arm/barrel_shifter.zig
View File

@ -1,7 +1,7 @@
const std = @import("std"); const std = @import("std");
const Arm7tdmi = @import("../cpu.zig").Arm7tdmi; const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
const CPSR = @import("../cpu.zig").PSR; const CPSR = @import("../../cpu.zig").PSR;
pub fn execute(comptime S: bool, cpu: *Arm7tdmi, opcode: u32) u32 { pub fn execute(comptime S: bool, cpu: *Arm7tdmi, opcode: u32) u32 {
var result: u32 = undefined; var result: u32 = undefined;

235
src/cpu/arm/data_processing.zig
View File

@ -1,6 +1,6 @@
const std = @import("std"); const std = @import("std");
const shifter = @import("../barrel_shifter.zig"); const shifter = @import("barrel_shifter.zig");
const Bus = @import("../../Bus.zig"); const Bus = @import("../../Bus.zig");
const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi; const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
const InstrFn = @import("../../cpu.zig").ArmInstrFn; const InstrFn = @import("../../cpu.zig").ArmInstrFn;
@ -33,245 +33,184 @@ pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime instrKind: u4
// AND // AND
const result = op1 & op2; const result = op1 & op2;
cpu.r[rd] = result; cpu.r[rd] = result;
setArmLogicOpFlags(S, cpu, rd, result); logicFlags(S, cpu, rd, result);
}, },
0x1 => { 0x1 => {
// EOR // EOR
const result = op1 ^ op2; const result = op1 ^ op2;
cpu.r[rd] = result; cpu.r[rd] = result;
setArmLogicOpFlags(S, cpu, rd, result); logicFlags(S, cpu, rd, result);
},
0x2 => {
// SUB
cpu.r[rd] = armSub(S, cpu, rd, op1, op2);
},
0x3 => {
// RSB
cpu.r[rd] = armSub(S, cpu, rd, op2, op1);
}, },
0x2 => cpu.r[rd] = sub(S, cpu, rd, op1, op2), // SUB
0x3 => cpu.r[rd] = sub(S, cpu, rd, op2, op1), // RSB
0x4 => { 0x4 => {
// ADD // ADD
cpu.r[rd] = armAdd(S, cpu, rd, op1, op2); var result: u32 = undefined;
const didOverflow = @addWithOverflow(u32, op1, op2, &result);
cpu.r[rd] = result;
if (S) {
if (rd == 0xF) {
cpu.setCpsr(cpu.spsr.raw);
} else {
cpu.cpsr.n.write(result >> 31 & 1 == 1);
cpu.cpsr.z.write(result == 0);
cpu.cpsr.c.write(didOverflow);
cpu.cpsr.v.write(((op1 ^ result) & (op2 ^ result)) >> 31 & 1 == 1);
}
}
}, },
0x5 => { 0x5 => {
// ADC // ADC
cpu.r[rd] = armAdc(S, cpu, rd, op1, op2, old_carry); var result: u32 = undefined;
},
0x6 => { const did = @addWithOverflow(u32, op1, op2, &result);
// SBC const overflow = @addWithOverflow(u32, result, old_carry, &result);
cpu.r[rd] = armSbc(S, cpu, rd, op1, op2, old_carry); cpu.r[rd] = result;
},
0x7 => { if (S) {
// RSC if (rd == 0xF) {
cpu.r[rd] = armSbc(S, cpu, rd, op2, op1, old_carry); cpu.setCpsr(cpu.spsr.raw);
} else {
cpu.cpsr.n.write(result >> 31 & 1 == 1);
cpu.cpsr.z.write(result == 0);
cpu.cpsr.c.write(did or overflow);
cpu.cpsr.v.write(((op1 ^ result) & (op2 ^ result)) >> 31 & 1 == 1);
}
}
}, },
0x6 => cpu.r[rd] = sbc(S, cpu, rd, op1, op2, old_carry), // SBC
0x7 => cpu.r[rd] = sbc(S, cpu, rd, op2, op1, old_carry), // RSC
0x8 => { 0x8 => {
// TST // TST
if (rd == 0xF) { if (rd == 0xF) {
undefinedTestBehaviour(cpu); undefinedTestBehaviour(cpu);
return; return;
} }
const result = op1 & op2; const result = op1 & op2;
setTestOpFlags(S, cpu, opcode, result); testFlags(S, cpu, opcode, result);
}, },
0x9 => { 0x9 => {
// TEQ // TEQ
if (rd == 0xF) { if (rd == 0xF) {
undefinedTestBehaviour(cpu); undefinedTestBehaviour(cpu);
return; return;
} }
const result = op1 ^ op2; const result = op1 ^ op2;
setTestOpFlags(S, cpu, opcode, result); testFlags(S, cpu, opcode, result);
}, },
0xA => { 0xA => {
// CMP // CMP
if (rd == 0xF) { if (rd == 0xF) {
undefinedTestBehaviour(cpu); undefinedTestBehaviour(cpu);
return; return;
} }
cmp(cpu, op1, op2); const result = op1 -% op2;
cpu.cpsr.n.write(result >> 31 & 1 == 1);
cpu.cpsr.z.write(result == 0);
cpu.cpsr.c.write(op2 <= op1);
cpu.cpsr.v.write(((op1 ^ result) & (~op2 ^ result)) >> 31 & 1 == 1);
}, },
0xB => { 0xB => {
// CMN // CMN
if (rd == 0xF) { if (rd == 0xF) {
undefinedTestBehaviour(cpu); undefinedTestBehaviour(cpu);
return; return;
} }
cmn(cpu, op1, op2); var result: u32 = undefined;
const didOverflow = @addWithOverflow(u32, op1, op2, &result);
cpu.cpsr.n.write(result >> 31 & 1 == 1);
cpu.cpsr.z.write(result == 0);
cpu.cpsr.c.write(didOverflow);
cpu.cpsr.v.write(((op1 ^ result) & (op2 ^ result)) >> 31 & 1 == 1);
}, },
0xC => { 0xC => {
// ORR // ORR
const result = op1 | op2; const result = op1 | op2;
cpu.r[rd] = result; cpu.r[rd] = result;
setArmLogicOpFlags(S, cpu, rd, result); logicFlags(S, cpu, rd, result);
}, },
0xD => { 0xD => {
// MOV // MOV
cpu.r[rd] = op2; cpu.r[rd] = op2;
setArmLogicOpFlags(S, cpu, rd, op2); logicFlags(S, cpu, rd, op2);
}, },
0xE => { 0xE => {
// BIC // BIC
const result = op1 & ~op2; const result = op1 & ~op2;
cpu.r[rd] = result; cpu.r[rd] = result;
setArmLogicOpFlags(S, cpu, rd, result); logicFlags(S, cpu, rd, result);
}, },
0xF => { 0xF => {
// MVN // MVN
const result = ~op2; const result = ~op2;
cpu.r[rd] = result; cpu.r[rd] = result;
setArmLogicOpFlags(S, cpu, rd, result); logicFlags(S, cpu, rd, result);
}, },
} }
} }
}.inner; }.inner;
} }
fn armSbc(comptime S: bool, cpu: *Arm7tdmi, rd: u4, left: u32, right: u32, old_carry: u1) u32 { fn sbc(comptime S: bool, cpu: *Arm7tdmi, rd: u4, left: u32, right: u32, old_carry: u1) u32 {
var result: u32 = undefined;
if (S and rd == 0xF) {
result = sbc(false, cpu, left, right, old_carry);
cpu.setCpsr(cpu.spsr.raw);
} else {
result = sbc(S, cpu, left, right, old_carry);
}
return result;
}
pub fn sbc(comptime S: bool, cpu: *Arm7tdmi, left: u32, right: u32, old_carry: u1) u32 {
// TODO: Make your own version (thanks peach.bot) // TODO: Make your own version (thanks peach.bot)
const subtrahend = @as(u64, right) - old_carry + 1; const subtrahend = @as(u64, right) - old_carry + 1;
const result = @truncate(u32, left -% subtrahend); const result = @truncate(u32, left -% subtrahend);
if (S) { if (S) {
cpu.cpsr.n.write(result >> 31 & 1 == 1); if (rd == 0xF) {
cpu.cpsr.z.write(result == 0); cpu.setCpsr(cpu.spsr.raw);
cpu.cpsr.c.write(subtrahend <= left); } else {
cpu.cpsr.v.write(((left ^ result) & (~right ^ result)) >> 31 & 1 == 1); cpu.cpsr.n.write(result >> 31 & 1 == 1);
cpu.cpsr.z.write(result == 0);
cpu.cpsr.c.write(subtrahend <= left);
cpu.cpsr.v.write(((left ^ result) & (~right ^ result)) >> 31 & 1 == 1);
}
} }
return result; return result;
} }
fn armSub(comptime S: bool, cpu: *Arm7tdmi, rd: u4, left: u32, right: u32) u32 { fn sub(comptime S: bool, cpu: *Arm7tdmi, rd: u4, left: u32, right: u32) u32 {
var result: u32 = undefined;
if (S and rd == 0xF) {
result = sub(false, cpu, left, right);
cpu.setCpsr(cpu.spsr.raw);
} else {
result = sub(S, cpu, left, right);
}
return result;
}
pub fn sub(comptime S: bool, cpu: *Arm7tdmi, left: u32, right: u32) u32 {
const result = left -% right; const result = left -% right;
if (S) { if (S) {
cpu.cpsr.n.write(result >> 31 & 1 == 1); if (rd == 0xF) {
cpu.cpsr.z.write(result == 0); cpu.setCpsr(cpu.spsr.raw);
cpu.cpsr.c.write(right <= left); } else {
cpu.cpsr.v.write(((left ^ result) & (~right ^ result)) >> 31 & 1 == 1); cpu.cpsr.n.write(result >> 31 & 1 == 1);
cpu.cpsr.z.write(result == 0);
cpu.cpsr.c.write(right <= left);
cpu.cpsr.v.write(((left ^ result) & (~right ^ result)) >> 31 & 1 == 1);
}
} }
return result; return result;
} }
fn armAdd(comptime S: bool, cpu: *Arm7tdmi, rd: u4, left: u32, right: u32) u32 { fn logicFlags(comptime S: bool, cpu: *Arm7tdmi, rd: u4, result: u32) void {
var result: u32 = undefined;
if (S and rd == 0xF) {
result = add(false, cpu, left, right);
cpu.setCpsr(cpu.spsr.raw);
} else {
result = add(S, cpu, left, right);
}
return result;
}
pub fn add(comptime S: bool, cpu: *Arm7tdmi, left: u32, right: u32) u32 {
var result: u32 = undefined;
const didOverflow = @addWithOverflow(u32, left, right, &result);
if (S) { if (S) {
cpu.cpsr.n.write(result >> 31 & 1 == 1); if (rd == 0xF) {
cpu.cpsr.z.write(result == 0); cpu.setCpsr(cpu.spsr.raw);
cpu.cpsr.c.write(didOverflow); } else {
cpu.cpsr.v.write(((left ^ result) & (right ^ result)) >> 31 & 1 == 1); cpu.cpsr.n.write(result >> 31 & 1 == 1);
} cpu.cpsr.z.write(result == 0);
// C set by Barrel Shifter, V is unaffected
return result; }
}
fn armAdc(comptime S: bool, cpu: *Arm7tdmi, rd: u4, left: u32, right: u32, old_carry: u1) u32 {
var result: u32 = undefined;
if (S and rd == 0xF) {
result = adc(false, cpu, left, right, old_carry);
cpu.setCpsr(cpu.spsr.raw);
} else {
result = adc(S, cpu, left, right, old_carry);
}
return result;
}
pub fn adc(comptime S: bool, cpu: *Arm7tdmi, left: u32, right: u32, old_carry: u1) u32 {
var result: u32 = undefined;
const did = @addWithOverflow(u32, left, right, &result);
const overflow = @addWithOverflow(u32, result, old_carry, &result);
if (S) {
cpu.cpsr.n.write(result >> 31 & 1 == 1);
cpu.cpsr.z.write(result == 0);
cpu.cpsr.c.write(did or overflow);
cpu.cpsr.v.write(((left ^ result) & (right ^ result)) >> 31 & 1 == 1);
}
return result;
}
pub fn cmp(cpu: *Arm7tdmi, left: u32, right: u32) void {
const result = left -% right;
cpu.cpsr.n.write(result >> 31 & 1 == 1);
cpu.cpsr.z.write(result == 0);
cpu.cpsr.c.write(right <= left);
cpu.cpsr.v.write(((left ^ result) & (~right ^ result)) >> 31 & 1 == 1);
}
pub fn cmn(cpu: *Arm7tdmi, left: u32, right: u32) void {
var result: u32 = undefined;
const didOverflow = @addWithOverflow(u32, left, right, &result);
cpu.cpsr.n.write(result >> 31 & 1 == 1);
cpu.cpsr.z.write(result == 0);
cpu.cpsr.c.write(didOverflow);
cpu.cpsr.v.write(((left ^ result) & (right ^ result)) >> 31 & 1 == 1);
}
fn setArmLogicOpFlags(comptime S: bool, cpu: *Arm7tdmi, rd: u4, result: u32) void {
if (S and rd == 0xF) {
cpu.setCpsr(cpu.spsr.raw);
} else {
setLogicOpFlags(S, cpu, result);
} }
} }
pub fn setLogicOpFlags(comptime S: bool, cpu: *Arm7tdmi, result: u32) void { fn testFlags(comptime S: bool, cpu: *Arm7tdmi, opcode: u32, result: u32) void {
if (S) {
cpu.cpsr.n.write(result >> 31 & 1 == 1);
cpu.cpsr.z.write(result == 0);
// C set by Barrel Shifter, V is unaffected
}
}
fn setTestOpFlags(comptime S: bool, cpu: *Arm7tdmi, opcode: u32, result: u32) void {
cpu.cpsr.n.write(result >> 31 & 1 == 1); cpu.cpsr.n.write(result >> 31 & 1 == 1);
cpu.cpsr.z.write(result == 0); cpu.cpsr.z.write(result == 0);
// Barrel Shifter should always calc CPSR C in TST // Barrel Shifter should always calc CPSR C in TST

10
src/cpu/arm/single_data_transfer.zig
View File

@ -1,7 +1,7 @@
const std = @import("std"); const std = @import("std");
const util = @import("../../util.zig"); const util = @import("../../util.zig");
const shifter = @import("../barrel_shifter.zig"); const BarrelShifter = @import("barrel_shifter.zig");
const Bus = @import("../../Bus.zig"); const Bus = @import("../../Bus.zig");
const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi; const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
const InstrFn = @import("../../cpu.zig").ArmInstrFn; const InstrFn = @import("../../cpu.zig").ArmInstrFn;
@ -58,9 +58,9 @@ fn registerOffset(cpu: *Arm7tdmi, opcode: u32) u32 {
const rm = cpu.r[opcode & 0xF]; const rm = cpu.r[opcode & 0xF];
return switch (@truncate(u2, opcode >> 5)) { return switch (@truncate(u2, opcode >> 5)) {
0b00 => shifter.logicalLeft(false, &cpu.cpsr, rm, amount), 0b00 => BarrelShifter.logicalLeft(false, &cpu.cpsr, rm, amount),
0b01 => shifter.logicalRight(false, &cpu.cpsr, rm, amount), 0b01 => BarrelShifter.logicalRight(false, &cpu.cpsr, rm, amount),
0b10 => shifter.arithmeticRight(false, &cpu.cpsr, rm, amount), 0b10 => BarrelShifter.arithmeticRight(false, &cpu.cpsr, rm, amount),
0b11 => shifter.rotateRight(false, &cpu.cpsr, rm, amount), 0b11 => BarrelShifter.rotateRight(false, &cpu.cpsr, rm, amount),
}; };
} }

28
src/cpu/thumb/format1.zig
View File

@ -1,28 +0,0 @@
const std = @import("std");
const Bus = @import("../../Bus.zig");
const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
const InstrFn = @import("../../cpu.zig").ThumbInstrFn;
const shifter = @import("../barrel_shifter.zig");
const setLogicOpFlags = @import("../arm/data_processing.zig").setLogicOpFlags;
pub fn format1(comptime op: u2, comptime offset: u5) InstrFn {
return struct {
fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void {
const rs = opcode >> 3 & 0x7;
const rd = opcode & 0x7;
const result = switch (op) {
0b00 => shifter.logicalLeft(true, &cpu.cpsr, cpu.r[rs], offset), // LSL
0b01 => shifter.logicalRight(true, &cpu.cpsr, cpu.r[rs], offset), // LSR
0b10 => shifter.arithmeticRight(true, &cpu.cpsr, cpu.r[rs], offset), // ASR
else => std.debug.panic("[CPU|THUMB|Fmt1] {} is an invalid op", .{op}),
};
// Equivalent to an ARM MOVS
cpu.r[rd] = result;
setLogicOpFlags(true, cpu, result);
}
}.inner;
}

5
src/cpu/thumb/format12.zig
View File

@ -7,9 +7,8 @@ const InstrFn = @import("../../cpu.zig").ThumbInstrFn;
pub fn format12(comptime isSP: bool, comptime rd: u3) InstrFn { pub fn format12(comptime isSP: bool, comptime rd: u3) InstrFn {
return struct { return struct {
fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void { fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void {
// ADD const left = if (isSP) cpu.r[13] else cpu.r[15] + 2 & 0xFFFF_FFFD; // fetch (+2)
const left = if (isSP) cpu.r[13] else cpu.fakePC() & 0xFFFF_FFFC; const right = @truncate(u10, opcode & 0xFF) << 2;
const right = (opcode & 0xFF) << 2;
const result = left + right; // TODO: What about overflows? const result = left + right; // TODO: What about overflows?
cpu.r[rd] = result; cpu.r[rd] = result;
} }

26
src/cpu/thumb/format16.zig
View File

@ -1,26 +0,0 @@
const std = @import("std");
const Bus = @import("../../Bus.zig");
const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
const InstrFn = @import("../../cpu.zig").ThumbInstrFn;
const checkCond = @import("../../cpu.zig").checkCond;
const u32SignExtend = @import("../../util.zig").u32SignExtend;
pub fn format16(comptime cond: u4) InstrFn {
return struct {
fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void {
// B
const offset = u32SignExtend(8, opcode & 0xFF) << 1;
const should_execute = switch (cond) {
0xE, 0xF => std.debug.panic("[CPU/THUMB] Undefined conditional branch with condition {}", .{cond}),
else => checkCond(cpu.cpsr, cond),
};
if (should_execute) {
cpu.r[15] = (cpu.fakePC() & 0xFFFF_FFFC) +% offset;
}
}
}.inner;
}

26
src/cpu/thumb/format19.zig
View File

@ -1,26 +0,0 @@
const std = @import("std");
const Bus = @import("../../Bus.zig");
const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
const InstrFn = @import("../../cpu.zig").ThumbInstrFn;
const u32SignExtend = @import("../../util.zig").u32SignExtend;
pub fn format19(comptime is_low: bool) InstrFn {
return struct {
fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void {
// BL
const offset = opcode & 0x3FF;
if (is_low) {
// Instruction 2
const old_pc = cpu.r[15];
cpu.r[15] = cpu.r[14] + (offset << 1);
cpu.r[14] = old_pc | 1;
} else {
// Instruction 1
cpu.r[14] = (cpu.fakePC() & 0xFFFF_FFFC) + (u32SignExtend(11, @as(u32, offset)) << 12);
}
}
}.inner;
}

33
src/cpu/thumb/format2.zig
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@ -1,33 +0,0 @@
const std = @import("std");
const Bus = @import("../../Bus.zig");
const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
const InstrFn = @import("../../cpu.zig").ThumbInstrFn;
const add = @import("../arm/data_processing.zig").add;
const sub = @import("../arm/data_processing.zig").sub;
pub fn format2(comptime I: bool, is_sub: bool, rn: u3) InstrFn {
return struct {
fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void {
const rs = opcode >> 3 & 0x7;
const rd = @truncate(u3, opcode);
if (is_sub) {
// SUB
cpu.r[rd] = if (I) blk: {
break :blk sub(true, cpu, cpu.r[rs], @as(u32, rn));
} else blk: {
break :blk sub(true, cpu, cpu.r[rs], cpu.r[rn]);
};
} else {
// ADD
cpu.r[rd] = if (I) blk: {
break :blk add(true, cpu, cpu.r[rs], @as(u32, rn));
} else blk: {
break :blk add(true, cpu, cpu.r[rs], cpu.r[rn]);
};
}
}
}.inner;
}

46
src/cpu/thumb/format3.zig
View File

@ -4,11 +4,6 @@ const Bus = @import("../../Bus.zig");
const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi; const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
const InstrFn = @import("../../cpu.zig").ThumbInstrFn; const InstrFn = @import("../../cpu.zig").ThumbInstrFn;
const add = @import("../arm/data_processing.zig").add;
const sub = @import("../arm/data_processing.zig").sub;
const cmp = @import("../arm/data_processing.zig").cmp;
const setLogicOpFlags = @import("../arm/data_processing.zig").setLogicOpFlags;
pub fn format3(comptime op: u2, comptime rd: u3) InstrFn { pub fn format3(comptime op: u2, comptime rd: u3) InstrFn {
return struct { return struct {
fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void { fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void {
@ -18,11 +13,44 @@ pub fn format3(comptime op: u2, comptime rd: u3) InstrFn {
0b00 => { 0b00 => {
// MOV // MOV
cpu.r[rd] = offset; cpu.r[rd] = offset;
setLogicOpFlags(true, cpu, offset);
cpu.cpsr.n.unset();
cpu.cpsr.z.write(offset == 0);
},
0b01 => {
// CMP
const left = cpu.r[rd];
const result = left -% offset;
cpu.cpsr.n.write(result >> 31 & 1 == 1);
cpu.cpsr.z.write(result == 0);
cpu.cpsr.c.write(offset <= left);
cpu.cpsr.v.write(((left ^ result) & (~offset ^ result)) >> 31 & 1 == 1);
},
0b10 => {
// ADD
const left = cpu.r[rd];
var result: u32 = undefined;
const didOverflow = @addWithOverflow(u32, left, offset, &result);
cpu.r[rd] = result;
cpu.cpsr.n.write(result >> 31 & 1 == 1);
cpu.cpsr.z.write(result == 0);
cpu.cpsr.c.write(didOverflow);
cpu.cpsr.v.write(((left ^ result) & (offset ^ result)) >> 31 & 1 == 1);
},
0b11 => {
// SUB
const left = cpu.r[rd];
const result = left -% offset;
cpu.r[rd] = result;
cpu.cpsr.n.write(result >> 31 & 1 == 1);
cpu.cpsr.z.write(result == 0);
cpu.cpsr.c.write(offset <= left);
cpu.cpsr.v.write(((left ^ result) & (~offset ^ result)) >> 31 & 1 == 1);
}, },
0b01 => cmp(cpu, cpu.r[rd], offset), // CMP
0b10 => cpu.r[rd] = add(true, cpu, cpu.r[rd], offset), // ADD
0b11 => cpu.r[rd] = sub(true, cpu, cpu.r[rd], offset), // SUB
} }
} }
}.inner; }.inner;

16
src/cpu/thumb/format5.zig
View File

@ -4,8 +4,6 @@ const Bus = @import("../../Bus.zig");
const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi; const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
const InstrFn = @import("../../cpu.zig").ThumbInstrFn; const InstrFn = @import("../../cpu.zig").ThumbInstrFn;
const cmp = @import("../arm/data_processing.zig").cmp;
pub fn format5(comptime op: u2, comptime h1: u1, comptime h2: u1) InstrFn { pub fn format5(comptime op: u2, comptime h1: u1, comptime h2: u1) InstrFn {
return struct { return struct {
fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void { fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void {
@ -13,14 +11,24 @@ pub fn format5(comptime op: u2, comptime h1: u1, comptime h2: u1) InstrFn {
const dst = @as(u4, h1) << 3 | (opcode & 0x7); const dst = @as(u4, h1) << 3 | (opcode & 0x7);
switch (op) { switch (op) {
0b01 => cmp(cpu, cpu.r[dst], cpu.r[src]), // CMP 0b01 => {
// CMP
const left = cpu.r[dst];
const right = cpu.r[src];
const result = left -% right;
cpu.cpsr.n.write(result >> 31 & 1 == 1);
cpu.cpsr.z.write(result == 0);
cpu.cpsr.c.write(right <= left);
cpu.cpsr.v.write(((left ^ result) & (~right ^ result)) >> 31 & 1 == 1);
},
0b10 => cpu.r[dst] = cpu.r[src], // MOV 0b10 => cpu.r[dst] = cpu.r[src], // MOV
0b11 => { 0b11 => {
// BX // BX
cpu.cpsr.t.write(cpu.r[src] & 1 == 1); cpu.cpsr.t.write(cpu.r[src] & 1 == 1);
cpu.r[15] = cpu.r[src] & 0xFFFF_FFFE; cpu.r[15] = cpu.r[src] & 0xFFFF_FFFE;
}, },
else => std.debug.panic("[CPU|THUMB|Fmt5] {} is an invalid op", .{op}), else => std.debug.panic("[CPU] Op #{} is invalid for THUMB Format 5", .{op}),
} }
} }
}.inner; }.inner;

17
src/cpu/thumb/format6.zig
View File

@ -1,17 +0,0 @@
const std = @import("std");
const Bus = @import("../../Bus.zig");
const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
const InstrFn = @import("../../cpu.zig").ThumbInstrFn;
pub fn format6(comptime rd: u3) InstrFn {
return struct {
fn inner(cpu: *Arm7tdmi, bus: *Bus, opcode: u16) void {
// LDR
const offset = (opcode & 0xFF) << 2;
// FIXME: Should this overflow?
cpu.r[rd] = bus.read32((cpu.fakePC() & 0xFFFF_FFFC) + offset);
}
}.inner;
}

16
src/main.zig
View File

@ -9,7 +9,6 @@ const Scheduler = @import("scheduler.zig").Scheduler;
const Timer = std.time.Timer; const Timer = std.time.Timer;
const Thread = std.Thread; const Thread = std.Thread;
const Atomic = std.atomic.Atomic; const Atomic = std.atomic.Atomic;
const File = std.fs.File;
const window_scale = 3; const window_scale = 3;
const gba_width = @import("ppu.zig").width; const gba_width = @import("ppu.zig").width;
@ -49,15 +48,14 @@ pub fn main() anyerror!void {
var cpu = Arm7tdmi.init(&scheduler, &bus); var cpu = Arm7tdmi.init(&scheduler, &bus);
cpu.fastBoot(); cpu.fastBoot();
var log_file: ?File = undefined;
if (enable_logging) { if (enable_logging) {
const file_name: []const u8 = if (is_binary) "zba.bin" else "zba.log"; const file_name = if (is_binary) "zba.bin" else "zba.log";
const file = try std.fs.cwd().createFile(file_name, .{ .read = true });
cpu.useLogger(&file, is_binary);
log_file = file; const file = try std.fs.cwd().createFile(file_name, .{ .read = true });
defer file.close();
cpu.useLogger(&file, is_binary);
} }
defer if (log_file) |file| file.close();
// Init Atomics // Init Atomics
var quit = Atomic(bool).init(false); var quit = Atomic(bool).init(false);
@ -72,7 +70,7 @@ pub fn main() anyerror!void {
defer SDL.SDL_Quit(); defer SDL.SDL_Quit();
var window = SDL.SDL_CreateWindow( var window = SDL.SDL_CreateWindow(
"ZBA", "Gameboy Advance Emulator",
SDL.SDL_WINDOWPOS_CENTERED, SDL.SDL_WINDOWPOS_CENTERED,
SDL.SDL_WINDOWPOS_CENTERED, SDL.SDL_WINDOWPOS_CENTERED,
gba_width * window_scale, gba_width * window_scale,
@ -108,7 +106,7 @@ pub fn main() anyerror!void {
SDL.SDL_RenderPresent(renderer); SDL.SDL_RenderPresent(renderer);
const fps = std.time.ns_per_s / timer.lap(); const fps = std.time.ns_per_s / timer.lap();
const title = std.fmt.bufPrint(&title_buf, "ZBA FPS: {d}", .{fps}) catch unreachable; const title = std.fmt.bufPrint(&title_buf, "Gameboy Advance Emulator FPS: {d}", .{fps}) catch unreachable;
SDL.SDL_SetWindowTitle(window, title.ptr); SDL.SDL_SetWindowTitle(window, title.ptr);
} }