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a7a44c4463
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85ffdf44f5
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@ -3,142 +3,82 @@ const std = @import("std");
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const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
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const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
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const CPSR = @import("../../cpu.zig").PSR;
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const CPSR = @import("../../cpu.zig").PSR;
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pub fn execute(comptime S: bool, cpu: *Arm7tdmi, opcode: u32) u32 {
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pub fn exec(comptime S: bool, cpu: *Arm7tdmi, opcode: u32) u32 {
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var result: u32 = undefined;
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var shift_amt: u8 = undefined;
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if (opcode >> 4 & 1 == 1) {
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if (opcode >> 4 & 1 == 1) {
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result = registerShift(S, cpu, opcode);
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shift_amt = @truncate(u8, cpu.r[opcode >> 8 & 0xF]);
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} else {
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} else {
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result = immShift(S, cpu, opcode);
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shift_amt = @truncate(u8, opcode >> 7 & 0x1F);
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}
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}
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return result;
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const rm = cpu.r[opcode & 0xF];
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}
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var value: u32 = undefined;
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if (rm == 0xF) {
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fn registerShift(comptime S: bool, cpu: *Arm7tdmi, opcode: u32) u32 {
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value = cpu.fakePC() + 4; // 12 ahead
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const rs_idx = opcode >> 8 & 0xF;
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} else {
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const rs = @truncate(u8, cpu.r[rs_idx]);
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value = cpu.r[opcode & 0xF];
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}
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const rm_idx = opcode & 0xF;
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const rm = if (rm_idx == 0xF) cpu.fakePC() + 4 else cpu.r[rm_idx];
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return switch (@truncate(u2, opcode >> 5)) {
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return switch (@truncate(u2, opcode >> 5)) {
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0b00 => logicalLeft(S, &cpu.cpsr, rm, rs),
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0b00 => logicalLeft(S, &cpu.cpsr, value, shift_amt),
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0b01 => logicalRight(S, &cpu.cpsr, rm, rs),
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0b01 => logicalRight(S, &cpu.cpsr, value, shift_amt),
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0b10 => arithmeticRight(S, &cpu.cpsr, rm, rs),
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0b10 => arithmeticRight(S, &cpu.cpsr, value, shift_amt),
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0b11 => rotateRight(S, &cpu.cpsr, rm, rs),
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0b11 => rotateRight(S, &cpu.cpsr, value, shift_amt),
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};
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};
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}
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}
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fn immShift(comptime S: bool, cpu: *Arm7tdmi, opcode: u32) u32 {
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pub fn logicalLeft(comptime S: bool, cpsr: *CPSR, rm: u32, amount: u8) u32 {
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const amount = @truncate(u8, opcode >> 7 & 0x1F);
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const shift_amt = @truncate(u5, amount);
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const rm_idx = opcode & 0xF;
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const rm = if (rm_idx == 0xF) cpu.fakePC() + 4 else cpu.r[rm_idx];
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var result: u32 = undefined;
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if (amount == 0) {
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switch (@truncate(u2, opcode >> 5)) {
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0b00 => {
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// LSL #0
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result = rm;
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},
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0b01 => {
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// LSR #0 aka LSR #32
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if (S) cpu.cpsr.c.write(rm >> 31 & 1 == 1);
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result = 0x0000_0000;
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},
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0b10 => {
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// ASR #0 aka ASR #32
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result = @bitCast(u32, @bitCast(i32, rm) >> 31);
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if (S) cpu.cpsr.c.write(result >> 31 & 1 == 1);
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},
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0b11 => {
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// ROR #0 aka RRX
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const carry: u32 = @boolToInt(cpu.cpsr.c.read());
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if (S) cpu.cpsr.c.write(rm & 1 == 1);
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result = (carry << 31) | (rm >> 1);
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},
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}
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} else {
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switch (@truncate(u2, opcode >> 5)) {
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0b00 => result = logicalLeft(S, &cpu.cpsr, rm, amount),
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0b01 => result = logicalRight(S, &cpu.cpsr, rm, amount),
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0b10 => result = arithmeticRight(S, &cpu.cpsr, rm, amount),
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0b11 => result = rotateRight(S, &cpu.cpsr, rm, amount),
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}
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}
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return result;
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}
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pub fn logicalLeft(comptime S: bool, cpsr: *CPSR, rm: u32, total_amount: u8) u32 {
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const amount = @truncate(u5, total_amount);
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const bit_count: u8 = @typeInfo(u32).Int.bits;
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const bit_count: u8 = @typeInfo(u32).Int.bits;
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var result: u32 = 0x0000_0000;
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var result: u32 = 0x0000_0000;
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if (total_amount < bit_count) {
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// We can perform a well-defined shift here
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result = rm << amount;
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if (S) {
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if (amount < bit_count) {
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const carry_bit = @truncate(u5, bit_count - amount);
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// We can perform a well-defined shift here
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// FIXME: We assume cpu.r[rs] == 0 and imm_shift == 0 are equivalent
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if (S and shift_amt != 0) {
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const carry_bit = @truncate(u5, bit_count - shift_amt);
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cpsr.c.write(rm >> carry_bit & 1 == 1);
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cpsr.c.write(rm >> carry_bit & 1 == 1);
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}
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}
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result = rm << shift_amt;
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} else if (amount == bit_count) {
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// Shifted all bits out, carry bit is bit 0 of rm
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if (S) cpsr.c.write(rm & 1 == 1);
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} else {
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} else {
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if (S) {
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// Shifted all bits out, carry bit has also been shifted out
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if (total_amount == bit_count) {
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if (S) cpsr.c.write(false);
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// Shifted all bits out, carry bit is bit 0 of rm
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cpsr.c.write(rm & 1 == 1);
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} else {
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cpsr.c.write(false);
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}
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}
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}
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}
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return result;
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return result;
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}
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}
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pub fn logicalRight(comptime S: bool, cpsr: *CPSR, rm: u32, total_amount: u32) u32 {
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pub fn logicalRight(comptime S: bool, cpsr: *CPSR, rm: u32, amount: u32) u32 {
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const amount = @truncate(u5, total_amount);
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const shift_amt = @truncate(u5, amount);
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const bit_count: u8 = @typeInfo(u32).Int.bits;
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const bit_count: u8 = @typeInfo(u32).Int.bits;
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var result: u32 = 0x0000_0000;
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var result: u32 = 0x0000_0000;
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if (total_amount < bit_count) {
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if (amount == 0 or amount == bit_count) {
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// Actualy LSR #32
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if (S) cpsr.c.write(rm >> 31 & 1 == 1);
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} else if (amount < bit_count) {
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// We can perform a well-defined shift
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// We can perform a well-defined shift
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result = rm >> amount;
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const carry_bit = shift_amt - 1;
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if (S) cpsr.c.write(rm >> (amount - 1) & 1 == 1);
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if (S) cpsr.c.write(rm >> carry_bit & 1 == 1);
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result = rm >> shift_amt;
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} else {
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} else {
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if (S) {
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// All bits have been shifted out, including carry bit
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if (total_amount == bit_count) {
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if (S) cpsr.c.write(false);
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// LSR #32
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cpsr.c.write(rm >> 31 & 1 == 1);
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} else {
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// All bits have been shifted out, including carry bit
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cpsr.c.write(false);
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}
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}
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}
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}
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return result;
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return result;
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}
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}
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pub fn arithmeticRight(comptime S: bool, cpsr: *CPSR, rm: u32, total_amount: u8) u32 {
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pub fn arithmeticRight(comptime _: bool, _: *CPSR, _: u32, _: u8) u32 {
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const amount = @truncate(u5, total_amount);
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// @bitCast(u32, @bitCast(i32, r_val) >> @truncate(u5, amount))
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const bit_count: u8 = @typeInfo(u32).Int.bits;
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var result: u32 = 0x0000_0000;
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if (total_amount < bit_count) {
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result = @bitCast(u32, @bitCast(i32, rm) >> amount);
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if (S) cpsr.c.write(rm >> (amount - 1) & 1 == 1);
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} else {
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if (S) {
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// ASR #32 and ASR #>32 have the same result
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result = @bitCast(u32, @bitCast(i32, rm) >> 31);
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cpsr.c.write(result >> 31 & 1 == 1);
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}
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}
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std.debug.panic("[BarrelShifter] implement arithmetic shift right", .{});
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std.debug.panic("[BarrelShifter] implement arithmetic shift right", .{});
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}
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}
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@ -1,6 +1,6 @@
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const std = @import("std");
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const std = @import("std");
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const shifter = @import("barrel_shifter.zig");
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const BarrelShifter = @import("barrel_shifter.zig");
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const Bus = @import("../../Bus.zig");
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const Bus = @import("../../Bus.zig");
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const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
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const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
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const InstrFn = @import("../../cpu.zig").ArmInstrFn;
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const InstrFn = @import("../../cpu.zig").ArmInstrFn;
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@ -11,14 +11,21 @@ pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime instrKind: u4
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const rd = opcode >> 12 & 0xF;
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const rd = opcode >> 12 & 0xF;
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const rn = opcode >> 16 & 0xF;
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const rn = opcode >> 16 & 0xF;
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const op1 = if (rn == 0xF) cpu.fakePC() else cpu.r[rn];
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if (S and rd == 0xF) std.debug.panic("[CPU] Data Processing Instruction w/ S set and Rd == 15", .{});
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var op1: u32 = undefined;
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if (rn == 0xF) {
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op1 = cpu.fakePC();
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} else {
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op1 = cpu.r[rn];
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}
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var op2: u32 = undefined;
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var op2: u32 = undefined;
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if (I) {
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if (I) {
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const amount = @truncate(u8, (opcode >> 8 & 0xF) << 1);
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const amount = @truncate(u8, (opcode >> 8 & 0xF) << 1);
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op2 = shifter.rotateRight(S, &cpu.cpsr, opcode & 0xFF, amount);
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op2 = BarrelShifter.rotateRight(S, &cpu.cpsr, opcode & 0xFF, amount);
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} else {
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} else {
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op2 = shifter.execute(S, cpu, opcode);
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op2 = BarrelShifter.exec(S, cpu, opcode);
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}
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}
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switch (instrKind) {
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switch (instrKind) {
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@ -47,22 +54,6 @@ pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime instrKind: u4
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cpu.cpsr.v.write(((op1 ^ result) & (op2 ^ result)) >> 31 & 1 == 1);
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cpu.cpsr.v.write(((op1 ^ result) & (op2 ^ result)) >> 31 & 1 == 1);
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}
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}
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},
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},
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0x5 => {
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// ADC
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const carry = @boolToInt(cpu.cpsr.c.read());
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var result: u32 = undefined;
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const did = @addWithOverflow(u32, op1, op2, &result);
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const overflow = @addWithOverflow(u32, result, carry, &result);
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cpu.r[rd] = result;
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if (S and rd != 0xF) {
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cpu.cpsr.n.write(result >> 31 & 1 == 1);
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cpu.cpsr.z.write(result == 0);
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cpu.cpsr.c.write(did or overflow);
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cpu.cpsr.v.write(((op1 ^ result) & (op2 ^ result)) >> 31 & 1 == 1);
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}
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},
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0x8 => {
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0x8 => {
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// TST
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// TST
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const result = op1 & op2;
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const result = op1 & op2;
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@ -70,7 +61,7 @@ pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime instrKind: u4
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cpu.cpsr.n.write(result >> 31 & 1 == 1);
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cpu.cpsr.n.write(result >> 31 & 1 == 1);
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cpu.cpsr.z.write(result == 0);
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cpu.cpsr.z.write(result == 0);
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// Barrel Shifter should always calc CPSR C in TST
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// Barrel Shifter should always calc CPSR C in TST
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if (!S) _ = shifter.execute(true, cpu, opcode);
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if (!S) _ = BarrelShifter.exec(true, cpu, opcode);
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},
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},
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0x9 => {
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0x9 => {
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// TEQ
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// TEQ
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@ -79,7 +70,7 @@ pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime instrKind: u4
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cpu.cpsr.n.write(result >> 31 & 1 == 1);
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cpu.cpsr.n.write(result >> 31 & 1 == 1);
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cpu.cpsr.z.write(result == 0);
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cpu.cpsr.z.write(result == 0);
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// Barrel Shifter should always calc CPSR C in TEQ
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// Barrel Shifter should always calc CPSR C in TEQ
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if (!S) _ = shifter.execute(true, cpu, opcode);
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if (!S) _ = BarrelShifter.exec(true, cpu, opcode);
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},
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},
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0xD => {
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0xD => {
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// MOV
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// MOV
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