Compare commits
No commits in common. "997dc1314c9923a45059c54a9e23b649195b7d66" and "985fefb9f657d1003cd4bf969017f5a3d5a45d15" have entirely different histories.
997dc1314c
...
985fefb9f6
|
@ -23,13 +23,16 @@ pub fn deinit(self: Self) void {
|
||||||
}
|
}
|
||||||
|
|
||||||
pub fn get32(self: *const Self, idx: usize) u32 {
|
pub fn get32(self: *const Self, idx: usize) u32 {
|
||||||
|
std.debug.panic("[BIOS] TODO: BIOS is not implemented", .{});
|
||||||
return (@as(u32, self.buf[idx + 3]) << 24) | (@as(u32, self.buf[idx + 2]) << 16) | (@as(u32, self.buf[idx + 1]) << 8) | (@as(u32, self.buf[idx]));
|
return (@as(u32, self.buf[idx + 3]) << 24) | (@as(u32, self.buf[idx + 2]) << 16) | (@as(u32, self.buf[idx + 1]) << 8) | (@as(u32, self.buf[idx]));
|
||||||
}
|
}
|
||||||
|
|
||||||
pub fn get16(self: *const Self, idx: usize) u16 {
|
pub fn get16(self: *const Self, idx: usize) u16 {
|
||||||
|
std.debug.panic("[BIOS] TODO: BIOS is not implemented", .{});
|
||||||
return (@as(u16, self.buf[idx + 1]) << 8) | @as(u16, self.buf[idx]);
|
return (@as(u16, self.buf[idx + 1]) << 8) | @as(u16, self.buf[idx]);
|
||||||
}
|
}
|
||||||
|
|
||||||
pub fn get8(self: *const Self, idx: usize) u8 {
|
pub fn get8(self: *const Self, idx: usize) u8 {
|
||||||
|
std.debug.panic("[BIOS] TODO: BIOS is not implemented", .{});
|
||||||
return self.buf[idx];
|
return self.buf[idx];
|
||||||
}
|
}
|
||||||
|
|
14
src/cpu.zig
14
src/cpu.zig
|
@ -15,7 +15,6 @@ const halfAndSignedDataTransfer = @import("cpu/arm/half_signed_data_transfer.zig
|
||||||
const blockDataTransfer = @import("cpu/arm/block_data_transfer.zig").blockDataTransfer;
|
const blockDataTransfer = @import("cpu/arm/block_data_transfer.zig").blockDataTransfer;
|
||||||
const branch = @import("cpu/arm/branch.zig").branch;
|
const branch = @import("cpu/arm/branch.zig").branch;
|
||||||
const branchAndExchange = @import("cpu/arm/branch.zig").branchAndExchange;
|
const branchAndExchange = @import("cpu/arm/branch.zig").branchAndExchange;
|
||||||
const softwareInterrupt = @import("cpu/arm/software_interrupt.zig").softwareInterrupt;
|
|
||||||
|
|
||||||
// THUMB Instruction Groups
|
// THUMB Instruction Groups
|
||||||
const format3 = @import("cpu/thumb/format3.zig").format3;
|
const format3 = @import("cpu/thumb/format3.zig").format3;
|
||||||
|
@ -96,15 +95,12 @@ pub const Arm7tdmi = struct {
|
||||||
}
|
}
|
||||||
|
|
||||||
pub fn setCpsr(self: *Self, value: u32) void {
|
pub fn setCpsr(self: *Self, value: u32) void {
|
||||||
if (value & 0x1F != self.cpsr.raw & 0x1F) self.changeModeFromIdx(@truncate(u5, value & 0x1F));
|
if (value & 0x1F != self.cpsr.raw & 0x1F) self.changeMode(@truncate(u5, value & 0x1F));
|
||||||
self.cpsr.raw = value;
|
self.cpsr.raw = value;
|
||||||
}
|
}
|
||||||
|
|
||||||
fn changeModeFromIdx(self: *Self, next: u5) void {
|
fn changeMode(self: *Self, next_idx: u5) void {
|
||||||
self.changeMode(getMode(next));
|
const next = getMode(next_idx);
|
||||||
}
|
|
||||||
|
|
||||||
pub fn changeMode(self: *Self, next: Mode) void {
|
|
||||||
const now = getMode(self.cpsr.mode.read());
|
const now = getMode(self.cpsr.mode.read());
|
||||||
|
|
||||||
// Bank R8 -> r12
|
// Bank R8 -> r12
|
||||||
|
@ -146,7 +142,7 @@ pub const Arm7tdmi = struct {
|
||||||
},
|
},
|
||||||
}
|
}
|
||||||
|
|
||||||
self.cpsr.mode.write(@enumToInt(next));
|
self.cpsr.mode.write(next_idx);
|
||||||
}
|
}
|
||||||
|
|
||||||
pub fn skipBios(self: *Self) void {
|
pub fn skipBios(self: *Self) void {
|
||||||
|
@ -352,8 +348,6 @@ fn armPopulate() [0x1000]ArmInstrFn {
|
||||||
const L = i >> 8 & 1 == 1;
|
const L = i >> 8 & 1 == 1;
|
||||||
lut[i] = branch(L);
|
lut[i] = branch(L);
|
||||||
}
|
}
|
||||||
|
|
||||||
if (i >> 8 & 0xF == 0b1111) lut[i] = softwareInterrupt();
|
|
||||||
}
|
}
|
||||||
|
|
||||||
return lut;
|
return lut;
|
||||||
|
|
|
@ -85,7 +85,6 @@ pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime instrKind: u4
|
||||||
// TST
|
// TST
|
||||||
if (rd == 0xF) {
|
if (rd == 0xF) {
|
||||||
undefinedTestBehaviour(cpu);
|
undefinedTestBehaviour(cpu);
|
||||||
cpu.r[15] += 4; // FIXME: This is objectively wrong I think
|
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -96,7 +95,6 @@ pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime instrKind: u4
|
||||||
// TEQ
|
// TEQ
|
||||||
if (rd == 0xF) {
|
if (rd == 0xF) {
|
||||||
undefinedTestBehaviour(cpu);
|
undefinedTestBehaviour(cpu);
|
||||||
cpu.r[15] += 4; // FIXME: This is objectively wrong I think
|
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -107,7 +105,6 @@ pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime instrKind: u4
|
||||||
// CMP
|
// CMP
|
||||||
if (rd == 0xF) {
|
if (rd == 0xF) {
|
||||||
undefinedTestBehaviour(cpu);
|
undefinedTestBehaviour(cpu);
|
||||||
cpu.r[15] += 4; // FIXME: This is objectively wrong I think
|
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -122,7 +119,6 @@ pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime instrKind: u4
|
||||||
// CMN
|
// CMN
|
||||||
if (rd == 0xF) {
|
if (rd == 0xF) {
|
||||||
undefinedTestBehaviour(cpu);
|
undefinedTestBehaviour(cpu);
|
||||||
cpu.r[15] += 4; // FIXME: This is objectively wrong I think
|
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
@ -1,24 +0,0 @@
|
||||||
const std = @import("std");
|
|
||||||
|
|
||||||
const Bus = @import("../../Bus.zig");
|
|
||||||
const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
|
|
||||||
const InstrFn = @import("../../cpu.zig").ArmInstrFn;
|
|
||||||
|
|
||||||
pub fn softwareInterrupt() InstrFn {
|
|
||||||
return struct {
|
|
||||||
fn inner(cpu: *Arm7tdmi, _: *Bus, _: u32) void {
|
|
||||||
// Copy Values from Current Mode
|
|
||||||
const r15 = cpu.r[15];
|
|
||||||
const cpsr = cpu.cpsr.raw;
|
|
||||||
|
|
||||||
// Switch Mode
|
|
||||||
cpu.changeMode(.Supervisor);
|
|
||||||
cpu.cpsr.t.write(false); // Force ARM Mode
|
|
||||||
cpu.cpsr.i.write(true); // Disable normal interrupts
|
|
||||||
|
|
||||||
cpu.r[14] = r15; // Resume Execution
|
|
||||||
cpu.spsr.raw = cpsr; // Previous mode CPSR
|
|
||||||
cpu.r[15] = 0x0000_0008;
|
|
||||||
}
|
|
||||||
}.inner;
|
|
||||||
}
|
|
Loading…
Reference in New Issue