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paoda:april-fools
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compare: paoda:c2901ee0d83593aeba386ac52f3f98607016b7b8
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paoda:april-fools
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No commits in common. "99492a67828b9425d6a4656e1da138f949d42e21" and "c2901ee0d83593aeba386ac52f3f98607016b7b8" have entirely different histories.
99492a6782 ... c2901ee0d8

7 changed files with 69 additions and 143 deletions
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109
src/cpu.zig
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@ -28,7 +28,6 @@ const format3 = @import("cpu/thumb/format3.zig").format3;
const format4 = @import("cpu/thumb/format4.zig").format4;
const format5 = @import("cpu/thumb/format5.zig").format5;
const format6 = @import("cpu/thumb/format6.zig").format6;
const format78 = @import("cpu/thumb/format78.zig").format78;
const format9 = @import("cpu/thumb/format9.zig").format9;
const format10 = @import("cpu/thumb/format10.zig").format10;
const format12 = @import("cpu/thumb/format12.zig").format12;
@ -425,47 +424,60 @@ pub fn checkCond(cpsr: PSR, cond: u4) bool {
fn thumbPopulate() [0x400]ThumbInstrFn {
return comptime {
@setEvalBranchQuota(0x5000);
@setEvalBranchQuota(0xC00);
var lut = [_]ThumbInstrFn{thumbUndefined} ** 0x400;
var i: usize = 0;
while (i < lut.len) : (i += 1) {
if (i >> 4 & 0x3F == 0b010000) {
const op = i & 0xF;
if (i >> 7 & 0x7 == 0b000) {
const op = i >> 5 & 0x3;
const offset = i & 0x1F;
lut[i] = format4(op);
} else if (i >> 4 & 0x3F == 0b010001) {
const op = i >> 2 & 0x3;
const h1 = i >> 1 & 1;
const h2 = i & 1;
lut[i] = format5(op, h1, h2);
} else if (i >> 5 & 0x1F == 0b00011) {
lut[i] = format1(op, offset);
}
if (i >> 5 & 0x1F == 0b00011) {
const I = i >> 4 & 1 == 1;
const is_sub = i >> 3 & 1 == 1;
const rn = i & 0x7;
lut[i] = format2(I, is_sub, rn);
} else if (i >> 5 & 0x1F == 0b01001) {
const rd = i >> 2 & 0x7;
}
lut[i] = format6(rd);
} else if (i >> 6 & 0xF == 0b0101) {
const op = i >> 5 & 0x3;
const T = i >> 3 & 1 == 1;
lut[i] = format78(op, T);
} else if (i >> 7 & 0x7 == 0b000) {
const op = i >> 5 & 0x3;
const offset = i & 0x1F;
lut[i] = format1(op, offset);
} else if (i >> 7 & 0x7 == 0b001) {
if (i >> 7 & 0x7 == 0b001) {
const op = i >> 5 & 0x3;
const rd = i >> 2 & 0x7;
lut[i] = format3(op, rd);
} else if (i >> 7 & 0x7 == 0b011) {
}
if (i >> 4 & 0x3F == 0b010000) {
const op = i & 0xF;
lut[i] = format4(op);
}
if (i >> 4 & 0x3F == 0b010001) {
const op = i >> 2 & 0x3;
const h1 = i >> 1 & 1;
const h2 = i & 1;
lut[i] = format5(op, h1, h2);
}
if (i >> 5 & 0x1F == 0b01001) {
const rd = i >> 2 & 0x7;
lut[i] = format6(rd);
}
if (i >> 6 & 0xF == 0b1000) {
const L = i >> 5 & 1 == 1;
const offset = i & 0x1F;
lut[i] = format10(L, offset);
}
if (i >> 7 & 0x7 == 0b011) {
const B = i >> 6 & 1 == 1;
const L = i >> 5 & 1 == 1;
const offset = i & 0x1F;
@ -473,43 +485,44 @@ fn thumbPopulate() [0x400]ThumbInstrFn {
lut[i] = format9(B, L, offset);
}
if (i >> 2 & 0xFF == 0xB0) {
const S = i >> 1 & 1 == 1;
lut[i] = format13(S);
} else if (i >> 2 & 0xFF == 0xDF) {
// Format 17 | Software Interrupt
lut[i] = thumbUndefined;
} else if (i >> 6 & 0xF == 0b1000) {
const L = i >> 5 & 1 == 1;
const offset = i & 0x1F;
lut[i] = format10(L, offset);
} else if (i >> 6 & 0xF == 0b1001) {
// Format 11 | SP-relative load / store
lut[i] = thumbUndefined;
} else if (i >> 6 & 0xF == 0b1010) {
if (i >> 6 & 0xF == 0b1010) {
const isSP = i >> 5 & 1 == 1;
const rd = i >> 2 & 0x7;
lut[i] = format12(isSP, rd);
} else if (i >> 6 & 0xF == 0b1011 and i >> 3 & 0x3 == 0b10) {
}
if (i >> 2 & 0xFF == 0xB0) {
const S = i >> 1 & 1 == 1;
lut[i] = format13(S);
}
if (i >> 6 & 0xF == 0b1011 and i >> 3 & 0x3 == 0b10) {
const L = i >> 5 & 1 == 1;
const R = i >> 2 & 1 == 1;
lut[i] = format14(L, R);
} else if (i >> 6 & 0xF == 0b1100) {
}
if (i >> 6 & 0xF == 0b1100) {
const L = i >> 5 & 1 == 1;
const rb = i >> 2 & 0x7;
lut[i] = format15(L, rb);
} else if (i >> 6 & 0xF == 0b1101) {
}
if (i >> 6 & 0xF == 0b1101) {
const cond = i >> 2 & 0xF;
lut[i] = format16(cond);
} else if (i >> 5 & 0x1F == 0b11100) {
}
if (i >> 5 & 0x1F == 0b11100) {
lut[i] = format18();
} else if (i >> 6 & 0xF == 0b1111) {
}
if (i >> 6 & 0xF == 0b1111) {
const is_low = i >> 5 & 1 == 1;
lut[i] = format19(is_low);

29
src/cpu/thumb/format1.zig
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@ -14,32 +14,9 @@ pub fn format1(comptime op: u2, comptime offset: u5) InstrFn {
const rd = opcode & 0x7;
const result = switch (op) {
0b00 => blk: {
// LSL
if (offset == 0) {
break :blk cpu.r[rs];
} else {
break :blk shifter.logicalLeft(true, &cpu.cpsr, cpu.r[rs], offset);
}
},
0b01 => blk: {
// LSR
if (offset == 0) {
cpu.cpsr.c.write(cpu.r[rs] >> 31 & 1 == 1);
break :blk @as(u32, 0);
} else {
break :blk shifter.logicalRight(true, &cpu.cpsr, cpu.r[rs], offset);
}
},
0b10 => blk: {
// ASR
if (offset == 0) {
cpu.cpsr.c.write(cpu.r[rs] >> 31 & 1 == 1);
break :blk @bitCast(u32, @bitCast(i32, cpu.r[rs]) >> 31);
} else {
break :blk shifter.arithmeticRight(true, &cpu.cpsr, cpu.r[rs], offset);
}
},
0b00 => shifter.logicalLeft(true, &cpu.cpsr, cpu.r[rs], offset), // LSL
0b01 => shifter.logicalRight(true, &cpu.cpsr, cpu.r[rs], offset), // LSR
0b10 => shifter.arithmeticRight(true, &cpu.cpsr, cpu.r[rs], offset), // ASR
else => cpu.panic("[CPU|THUMB|Fmt1] {} is an invalid op", .{op}),
};

3
src/cpu/thumb/format10.zig
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@ -14,8 +14,7 @@ pub fn format10(comptime L: bool, comptime offset: u5) InstrFn {
if (L) {
// LDRH
const value = bus.read16(address & 0xFFFF_FFFE);
cpu.r[rd] = std.math.rotr(u32, @as(u32, value), 8 * (address & 1));
cpu.r[rd] = bus.read16(address & 0xFFFF_FFFE);
} else {
// STRH
bus.write16(address & 0xFFFF_FFFE, @truncate(u16, cpu.r[rd]));

5
src/cpu/thumb/format4.zig
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@ -72,7 +72,7 @@ pub fn format4(comptime op: u4) InstrFn {
},
0x9 => {
// NEG
cpu.r[rd] = sub(true, cpu, 0, cpu.r[rs]);
cpu.r[rd] = sub(true, cpu, cpu.r[rs], cpu.r[rd]); // FIXME: I think this is wrong?
},
0xA => {
// CMP
@ -90,8 +90,7 @@ pub fn format4(comptime op: u4) InstrFn {
},
0xD => {
// MUL
const temp = @as(u64, cpu.r[rs]) * @as(u64, cpu.r[rd]);
const result = @truncate(u32, temp);
const result = cpu.r[rs] * cpu.r[rd];
cpu.r[rd] = result;
cpu.cpsr.n.write(result >> 31 & 1 == 1);

3
src/cpu/thumb/format5.zig
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@ -5,7 +5,6 @@ const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
const InstrFn = @import("../../cpu.zig").ThumbInstrFn;
const cmp = @import("../arm/data_processing.zig").cmp;
const add = @import("../arm/data_processing.zig").add;
pub fn format5(comptime op: u2, comptime h1: u1, comptime h2: u1) InstrFn {
return struct {
@ -14,7 +13,6 @@ pub fn format5(comptime op: u2, comptime h1: u1, comptime h2: u1) InstrFn {
const dst = @as(u4, h1) << 3 | (opcode & 0x7);
switch (op) {
0b00 => cpu.r[dst] = add(false, cpu, cpu.r[dst], cpu.r[src]), // ADD
0b01 => cmp(cpu, cpu.r[dst], cpu.r[src]), // CMP
0b10 => cpu.r[dst] = cpu.r[src], // MOV
0b11 => {
@ -22,6 +20,7 @@ pub fn format5(comptime op: u2, comptime h1: u1, comptime h2: u1) InstrFn {
cpu.cpsr.t.write(cpu.r[src] & 1 == 1);
cpu.r[15] = cpu.r[src] & 0xFFFF_FFFE;
},
else => cpu.panic("[CPU|THUMB|Fmt5] {} is an invalid op", .{op}),
}
}
}.inner;

60
src/cpu/thumb/format78.zig
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@ -1,60 +0,0 @@
const std = @import("std");
const Bus = @import("../../Bus.zig");
const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
const InstrFn = @import("../../cpu.zig").ThumbInstrFn;
const u32SignExtend = @import("../../util.zig").u32SignExtend;
pub fn format78(comptime op: u2, comptime T: bool) InstrFn {
return struct {
fn inner(cpu: *Arm7tdmi, bus: *Bus, opcode: u16) void {
const ro = opcode >> 6 & 0x7;
const rb = opcode >> 3 & 0x7;
const rd = opcode & 0x7;
const address = cpu.r[rb] + cpu.r[ro];
if (T) {
switch (op) {
0b00 => {
// STRH
bus.write16(address & 0xFFFF_FFFE, @truncate(u16, cpu.r[rd]));
},
0b01 => {
// LDRH
const value = bus.read16(address & 0xFFFF_FFFE);
cpu.r[rd] = std.math.rotr(u32, @as(u32, value), 8 * (address & 1));
},
0b10 => {
// LDSB
cpu.r[rd] = u32SignExtend(8, @as(u32, bus.read8(address)));
},
0b11 => {
// LDSH
cpu.r[rd] = u32SignExtend(16, @as(u32, bus.read16(address & 0xFFFF_FFFE)));
},
}
} else {
switch (op) {
0b00 => {
// STR
bus.write32(address & 0xFFFF_FFFC, cpu.r[rd]);
},
0b01 => {
// STRB
bus.write8(address, @truncate(u8, cpu.r[rd]));
},
0b10 => {
// LDR
const value = bus.read32(address & 0xFFFF_FFFC);
cpu.r[rd] = std.math.rotr(u32, value, 8 * (address & 0x3));
},
0b11 => {
// LDRB
cpu.r[rd] = bus.read8(address);
},
}
}
}
}.inner;
}

3
src/cpu/thumb/format9.zig
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@ -18,8 +18,7 @@ pub fn format9(comptime B: bool, comptime L: bool, comptime offset: u5) InstrFn
} else {
// LDR
const address = cpu.r[rb] + (@as(u32, offset) << 2);
const value = bus.read32(address & 0xFFFF_FFFC);
cpu.r[rd] = std.math.rotr(u32, value, 8 * (address & 0x3));
cpu.r[rd] = bus.read32(address & 0xFFFF_FFFC);
}
} else {
if (B) {