feat(cpu): implement SWI

src/bus/Bios.zig

@@ -23,16 +23,13 @@ pub fn deinit(self: Self) void {
 }
 
 pub fn get32(self: *const Self, idx: usize) u32 {
-    std.debug.panic("[BIOS] TODO: BIOS is not implemented", .{});
     return (@as(u32, self.buf[idx + 3]) << 24) | (@as(u32, self.buf[idx + 2]) << 16) | (@as(u32, self.buf[idx + 1]) << 8) | (@as(u32, self.buf[idx]));
 }
 
 pub fn get16(self: *const Self, idx: usize) u16 {
-    std.debug.panic("[BIOS] TODO: BIOS is not implemented", .{});
     return (@as(u16, self.buf[idx + 1]) << 8) | @as(u16, self.buf[idx]);
 }
 
 pub fn get8(self: *const Self, idx: usize) u8 {
-    std.debug.panic("[BIOS] TODO: BIOS is not implemented", .{});
     return self.buf[idx];
 }

src/cpu.zig

@@ -15,6 +15,7 @@ const halfAndSignedDataTransfer = @import("cpu/arm/half_signed_data_transfer.zig
 const blockDataTransfer = @import("cpu/arm/block_data_transfer.zig").blockDataTransfer;
 const branch = @import("cpu/arm/branch.zig").branch;
 const branchAndExchange = @import("cpu/arm/branch.zig").branchAndExchange;
+const softwareInterrupt = @import("cpu/arm/software_interrupt.zig").softwareInterrupt;
 
 // THUMB Instruction Groups
 const format3 = @import("cpu/thumb/format3.zig").format3;
@@ -95,12 +96,15 @@ pub const Arm7tdmi = struct {
     }
 
     pub fn setCpsr(self: *Self, value: u32) void {
-        if (value & 0x1F != self.cpsr.raw & 0x1F) self.changeMode(@truncate(u5, value & 0x1F));
+        if (value & 0x1F != self.cpsr.raw & 0x1F) self.changeModeFromIdx(@truncate(u5, value & 0x1F));
         self.cpsr.raw = value;
     }
 
-    fn changeMode(self: *Self, next_idx: u5) void {
-        const next = getMode(next_idx);
+    fn changeModeFromIdx(self: *Self, next: u5) void {
+        self.changeMode(getMode(next));
+    }
+
+    pub fn changeMode(self: *Self, next: Mode) void {
         const now = getMode(self.cpsr.mode.read());
 
         // Bank R8 -> r12
@@ -142,7 +146,7 @@ pub const Arm7tdmi = struct {
             },
         }
 
-        self.cpsr.mode.write(next_idx);
+        self.cpsr.mode.write(@enumToInt(next));
     }
 
     pub fn skipBios(self: *Self) void {
@@ -348,6 +352,8 @@ fn armPopulate() [0x1000]ArmInstrFn {
                 const L = i >> 8 & 1 == 1;
                 lut[i] = branch(L);
             }
+
+            if (i >> 8 & 0xF == 0b1111) lut[i] = softwareInterrupt();
         }
 
         return lut;

src/cpu/arm/data_processing.zig

@@ -85,6 +85,7 @@ pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime instrKind: u4
                     // TST
                     if (rd == 0xF) {
                         undefinedTestBehaviour(cpu);
+                        cpu.r[15] += 4; // FIXME: This is objectively wrong I think
                         return;
                     }
 
@@ -95,6 +96,7 @@ pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime instrKind: u4
                     // TEQ
                     if (rd == 0xF) {
                         undefinedTestBehaviour(cpu);
+                        cpu.r[15] += 4; // FIXME: This is objectively wrong I think
                         return;
                     }
 
@@ -105,6 +107,7 @@ pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime instrKind: u4
                     // CMP
                     if (rd == 0xF) {
                         undefinedTestBehaviour(cpu);
+                        cpu.r[15] += 4; // FIXME: This is objectively wrong I think
                         return;
                     }
 
@@ -119,6 +122,7 @@ pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime instrKind: u4
                     // CMN
                     if (rd == 0xF) {
                         undefinedTestBehaviour(cpu);
+                        cpu.r[15] += 4; // FIXME: This is objectively wrong I think
                         return;
                     }
 

src/cpu/arm/software_interrupt.zig

@@ -0,0 +1,24 @@
+const std = @import("std");
+
+const Bus = @import("../../Bus.zig");
+const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
+const InstrFn = @import("../../cpu.zig").ArmInstrFn;
+
+pub fn softwareInterrupt() InstrFn {
+    return struct {
+        fn inner(cpu: *Arm7tdmi, _: *Bus, _: u32) void {
+            // Copy Values from Current Mode
+            const r15 = cpu.r[15];
+            const cpsr = cpu.cpsr.raw;
+
+            // Switch Mode
+            cpu.changeMode(.Supervisor);
+            cpu.cpsr.t.write(false); // Force ARM Mode
+            cpu.cpsr.i.write(true); // Disable normal interrupts
+
+            cpu.r[14] = r15; // Resume Execution
+            cpu.spsr.raw = cpsr; // Previous mode CPSR
+            cpu.r[15] = 0x0000_0008;
+        }
+    }.inner;
+}