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No commits in common. "8e3f48837dd4f82f3ecdb75622b64b0dcd0edb63" and "cb10dfbdfd3414fa9e2470cca5936b35eacc89ea" have entirely different histories.
8e3f48837d
...
cb10dfbdfd
30
src/Bus.zig
30
src/Bus.zig
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@ -13,8 +13,6 @@ const Allocator = std.mem.Allocator;
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const log = std.log.scoped(.Bus);
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const Self = @This();
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const panic_on_und_bus: bool = false;
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pak: GamePak,
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bios: Bios,
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ppu: Ppu,
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@ -29,7 +27,7 @@ pub fn init(alloc: Allocator, sched: *Scheduler, rom_path: []const u8, maybe_bio
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.ppu = try Ppu.init(alloc, sched),
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.iwram = try Iwram.init(alloc),
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.ewram = try Ewram.init(alloc),
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.io = Io.init(sched),
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.io = Io.init(),
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};
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}
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@ -59,7 +57,7 @@ pub fn read32(self: *const Self, addr: u32) u32 {
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0x0A00_0000...0x0BFF_FFFF => self.pak.get32(addr - 0x0A00_0000),
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0x0C00_0000...0x0DFF_FFFF => self.pak.get32(addr - 0x0C00_0000),
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else => undRead("Tried to read from 0x{X:0>8}", .{addr}),
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else => failedRead("Tried to read from 0x{X:0>8}", .{addr}),
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};
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}
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@ -77,7 +75,7 @@ pub fn write32(self: *Self, addr: u32, word: u32) void {
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0x0600_0000...0x0601_7FFF => self.ppu.vram.set32(addr - 0x0600_0000, word),
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0x0700_0000...0x07FF_FFFF => self.ppu.oam.set32(addr & 0x3FF, word),
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else => undWrite("Tried to write 0x{X:0>8} to 0x{X:0>8}", .{ word, addr }),
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else => log.warn("Tried to write 0x{X:0>8} to 0x{X:0>8}", .{ word, addr }),
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}
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}
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@ -99,7 +97,7 @@ pub fn read16(self: *const Self, addr: u32) u16 {
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0x0A00_0000...0x0BFF_FFFF => self.pak.get16(addr - 0x0A00_0000),
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0x0C00_0000...0x0DFF_FFFF => self.pak.get16(addr - 0x0C00_0000),
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else => undRead("Tried to read from 0x{X:0>8}", .{addr}),
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else => std.debug.panic("Tried to read from 0x{X:0>8}", .{addr}),
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};
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}
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@ -116,7 +114,7 @@ pub fn write16(self: *Self, addr: u32, halfword: u16) void {
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0x0600_0000...0x0601_7FFF => self.ppu.vram.set16(addr - 0x0600_0000, halfword),
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0x0700_0000...0x07FF_FFFF => self.ppu.oam.set16(addr & 0x3FF, halfword),
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else => undWrite("Tried to write 0x{X:0>4} to 0x{X:0>8}", .{ halfword, addr }),
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else => std.debug.panic("Tried to write 0x{X:0>4} to 0x{X:0>8}", .{ halfword, addr }),
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}
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}
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@ -137,9 +135,9 @@ pub fn read8(self: *const Self, addr: u32) u8 {
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0x0800_0000...0x09FF_FFFF => self.pak.get8(addr - 0x0800_0000),
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0x0A00_0000...0x0BFF_FFFF => self.pak.get8(addr - 0x0A00_0000),
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0x0C00_0000...0x0DFF_FFFF => self.pak.get8(addr - 0x0C00_0000),
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0x0E00_0000...0x0EFF_FFFF => self.pak.sram.get8(addr & 0xFFFF),
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0x0E00_0000...0x0E00_FFFF => self.pak.sram.get8(addr - 0x0E00_0000),
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else => undRead("Tried to read from 0x{X:0>2}", .{addr}),
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else => std.debug.panic("Tried to read from 0x{X:0>2}", .{addr}),
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};
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}
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@ -149,19 +147,15 @@ pub fn write8(self: *Self, addr: u32, byte: u8) void {
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0x0200_0000...0x02FF_FFFF => self.ewram.set8(addr & 0x3FFFF, byte),
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0x0300_0000...0x03FF_FFFF => self.iwram.set8(addr & 0x7FFF, byte),
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0x0400_0000...0x0400_03FE => io.write8(self, addr, byte),
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0x0400_0410 => log.info("Ignored write of 0x{X:0>2} to 0x{X:0>8}", .{ byte, addr }),
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0x0400_0410 => log.info("Wrote 0x{X:0>2} to 0x{X:0>8}. Ignored", .{ byte, addr }),
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// External Memory (Game Pak)
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0x0E00_0000...0x0E00_FFFF => self.pak.sram.set8(addr & 0xFFFF, byte),
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else => undWrite("Tried to write 0x{X:0>2} to 0x{X:0>8}", .{ byte, addr }),
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0x0E00_0000...0x0E00_FFFF => self.pak.sram.set8(addr - 0x0E00_0000, byte),
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else => std.debug.panic("Tried to write 0x{X:0>2} to 0x{X:0>8}", .{ byte, addr }),
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}
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}
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fn undRead(comptime format: []const u8, args: anytype) u8 {
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if (panic_on_und_bus) std.debug.panic(format, args) else log.warn(format, args);
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fn failedRead(comptime format: []const u8, args: anytype) u8 {
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log.warn(format, args);
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return 0;
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}
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fn undWrite(comptime format: []const u8, args: anytype) void {
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if (panic_on_und_bus) std.debug.panic(format, args) else log.warn(format, args);
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}
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189
src/bus/io.zig
189
src/bus/io.zig
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@ -4,10 +4,6 @@ const Bit = @import("bitfield").Bit;
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const Bitfield = @import("bitfield").Bitfield;
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const Bus = @import("../Bus.zig");
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const DmaController = @import("dma.zig").DmaController;
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const Timer = @import("timer.zig").Timer;
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const Scheduler = @import("../scheduler.zig").Scheduler;
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const panic_on_und_io: bool = false;
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const log = std.log.scoped(.@"I/O");
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@ -28,16 +24,9 @@ pub const Io = struct {
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dma2: DmaController(2),
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dma3: DmaController(3),
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// Timers
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// TODO: Figure out how to turn this into an array
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tim0: Timer(0),
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tim1: Timer(1),
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tim2: Timer(2),
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tim3: Timer(3),
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keyinput: KeyInput,
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pub fn init(sched: *Scheduler) Self {
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pub fn init() Self {
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return .{
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.ime = false,
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.ie = .{ .raw = 0x0000 },
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@ -46,17 +35,11 @@ pub const Io = struct {
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.postflg = .FirstBoot,
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.haltcnt = .Execute,
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// Dma Controllers
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// Dma Transfers
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.dma0 = DmaController(0).init(),
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.dma1 = DmaController(1).init(),
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.dma2 = DmaController(2).init(),
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.dma3 = DmaController(3).init(),
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// Timers
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.tim0 = Timer(0).init(sched),
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.tim1 = Timer(1).init(sched),
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.tim2 = Timer(2).init(sched),
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.tim3 = Timer(3).init(sched),
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};
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}
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@ -68,33 +51,21 @@ pub const Io = struct {
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pub fn read32(bus: *const Bus, addr: u32) u32 {
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return switch (addr) {
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// Display
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0x0400_0000 => bus.ppu.dispcnt.raw,
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0x0400_0004 => @as(u32, bus.ppu.vcount.raw) << 16 | bus.ppu.dispstat.raw,
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0x0400_0006 => @as(u32, bus.ppu.bg[0].cnt.raw) << 16 | bus.ppu.vcount.raw,
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// DMA Transfers
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0x0400_0200 => @as(u32, bus.io.irq.raw) << 16 | bus.io.ie.raw,
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0x0400_0208 => @boolToInt(bus.io.ime),
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0x0400_00B8 => @as(u32, bus.io.dma0.cnt.raw) << 16,
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0x0400_00C4 => @as(u32, bus.io.dma1.cnt.raw) << 16,
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0x0400_00D0 => @as(u32, bus.io.dma1.cnt.raw) << 16,
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0x0400_00DC => @as(u32, bus.io.dma3.cnt.raw) << 16,
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// Timers
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0x0400_0100 => @as(u32, bus.io.tim0.cnt.raw) << 16 | bus.io.tim0.counter(),
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0x0400_0104 => @as(u32, bus.io.tim1.cnt.raw) << 16 | bus.io.tim1.counter(),
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0x0400_0108 => @as(u32, bus.io.tim2.cnt.raw) << 16 | bus.io.tim2.counter(),
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0x0400_010C => @as(u32, bus.io.tim3.cnt.raw) << 16 | bus.io.tim3.counter(),
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// Interrupts
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0x0400_0200 => @as(u32, bus.io.irq.raw) << 16 | bus.io.ie.raw,
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0x0400_0208 => @boolToInt(bus.io.ime),
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else => undRead("Tried to read word from 0x{X:0>8}", .{addr}),
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else => std.debug.panic("Tried to read word from 0x{X:0>8}", .{addr}),
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};
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}
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pub fn write32(bus: *Bus, addr: u32, word: u32) void {
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switch (addr) {
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// Display
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0x0400_0000 => bus.ppu.dispcnt.raw = @truncate(u16, word),
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0x0400_0004 => {
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bus.ppu.dispstat.raw = @truncate(u16, word);
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@ -106,12 +77,8 @@ pub fn write32(bus: *Bus, addr: u32, word: u32) void {
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0x0400_0014 => bus.ppu.setBgOffsets(1, word),
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0x0400_0018 => bus.ppu.setBgOffsets(2, word),
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0x0400_001C => bus.ppu.setBgOffsets(3, word),
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// Sound
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0x0400_00A0 => log.warn("Wrote 0x{X:0>8} to FIFO_A", .{word}),
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0x0400_00A4 => log.warn("Wrote 0x{X:0>8} to FIFO_B", .{word}),
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// DMA Transfers
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0x0400_00B0 => bus.io.dma0.writeSad(word),
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0x0400_00B4 => bus.io.dma0.writeDad(word),
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0x0400_00B8 => bus.io.dma0.writeCnt(word),
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@ -124,62 +91,33 @@ pub fn write32(bus: *Bus, addr: u32, word: u32) void {
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0x0400_00D4 => bus.io.dma3.writeSad(word),
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0x0400_00D8 => bus.io.dma3.writeDad(word),
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0x0400_00DC => bus.io.dma3.writeCnt(word),
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// Timers
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0x0400_0100 => bus.io.tim0.writeCnt(word),
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0x0400_0104 => bus.io.tim1.writeCnt(word),
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0x0400_0108 => bus.io.tim2.writeCnt(word),
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0x0400_010C => bus.io.tim3.writeCnt(word),
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// Serial Communication 1
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0x0400_0120 => log.warn("Wrote 0x{X:0>8} to SIODATA32", .{word}),
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// Interrupts
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0x0400_0200 => bus.io.setIrqs(word),
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0x0400_0204 => log.warn("Wrote 0x{X:0>8} to WAITCNT", .{word}),
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0x0400_0208 => bus.io.ime = word & 1 == 1,
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else => undWrite("Tried to write 0x{X:0>8} to 0x{X:0>8}", .{ word, addr }),
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else => std.debug.panic("Tried to write 0x{X:0>8} to 0x{X:0>8}", .{ word, addr }),
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}
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}
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pub fn read16(bus: *const Bus, addr: u32) u16 {
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return switch (addr) {
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// Display
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0x0400_0000 => bus.ppu.dispcnt.raw,
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0x0400_0004 => bus.ppu.dispstat.raw,
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0x0400_0006 => bus.ppu.vcount.raw,
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// Sound
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0x0400_0088 => unimplementedRead("Read halfword from SOUNDBIAS", .{}),
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// Timers
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0x0400_0100 => bus.io.tim0.counter(),
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0x0400_0102 => bus.io.tim0.cnt.raw,
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0x0400_0104 => bus.io.tim1.counter(),
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0x0400_0106 => bus.io.tim1.cnt.raw,
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0x0400_0108 => bus.io.tim2.counter(),
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0x0400_010A => bus.io.tim2.cnt.raw,
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0x0400_010C => bus.io.tim3.counter(),
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0x0400_010E => bus.io.tim3.cnt.raw,
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// Serial Communication 1
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0x0400_0128 => unimplementedRead("Read halfword from SIOCNT", .{}),
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// Keypad Input
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0x0400_0130 => bus.io.keyinput.raw,
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// Interrupts
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0x0400_0200 => bus.io.ie.raw,
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0x0400_0202 => bus.io.irq.raw,
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0x0400_0204 => unimplementedRead("Read halfword from WAITCNT", .{}),
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0x0400_0208 => @boolToInt(bus.io.ime),
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else => undRead("Tried to read halfword from 0x{X:0>8}", .{addr}),
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0x0400_0102 => failedRead("Tried to read halfword from TM0CNT_H", .{}),
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0x0400_0106 => failedRead("Tried to read halfword from TM1CNT_H", .{}),
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0x0400_010A => failedRead("Tried to read halfword from TM2CNT_H", .{}),
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0x0400_010E => failedRead("Tried to read halfword from TM3CNT_H", .{}),
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0x0400_0204 => failedRead("Tried to read halfword from WAITCNT", .{}),
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else => std.debug.panic("Tried to read halfword from 0x{X:0>8}", .{addr}),
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};
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}
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pub fn write16(bus: *Bus, addr: u32, halfword: u16) void {
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switch (addr) {
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// Display
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0x0400_0000 => bus.ppu.dispcnt.raw = halfword,
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0x0400_0004 => bus.ppu.dispstat.raw = halfword,
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0x0400_0008 => bus.ppu.bg[0].cnt.raw = halfword,
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@ -194,10 +132,6 @@ pub fn write16(bus: *Bus, addr: u32, halfword: u16) void {
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0x0400_001A => bus.ppu.bg[2].vofs.raw = halfword,
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0x0400_001C => bus.ppu.bg[3].hofs.raw = halfword,
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0x0400_001E => bus.ppu.bg[3].vofs.raw = halfword,
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0x0400_0020 => log.warn("Wrote 0x{X:0>4} to BG2PA", .{halfword}),
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0x0400_0026 => log.warn("Wrote 0x{X:0>4} to BG2PD", .{halfword}),
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0x0400_0030 => log.warn("Wrote 0x{X:0>4} to BG3PA", .{halfword}),
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0x0400_0036 => log.warn("Wrote 0x{X:0>4} to BG3PD", .{halfword}),
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0x0400_0040 => log.warn("Wrote 0x{X:0>4} to WIN0H", .{halfword}),
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0x0400_0042 => log.warn("Wrote 0x{X:0>4} to WIN1H", .{halfword}),
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0x0400_0044 => log.warn("Wrote 0x{X:0>4} to WIN0V", .{halfword}),
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@ -208,14 +142,9 @@ pub fn write16(bus: *Bus, addr: u32, halfword: u16) void {
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0x0400_0050 => log.warn("Wrote 0x{X:0>4} to BLDCNT", .{halfword}),
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0x0400_0052 => log.warn("Wrote 0x{X:0>4} to BLDALPHA", .{halfword}),
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0x0400_0054 => log.warn("Wrote 0x{X:0>4} to BLDY", .{halfword}),
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// Sound
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0x0400_0080 => log.warn("Wrote 0x{X:0>4} to SOUNDCNT_L", .{halfword}),
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0x0400_0082 => log.warn("Wrote 0x{X:0>4} to SOUNDCNT_H", .{halfword}),
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0x0400_0084 => log.warn("Wrote 0x{X:0>4} to SOUNDCNT_X", .{halfword}),
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0x0400_0088 => log.warn("Wrote 0x{X:0>4} to SOUNDBIAS", .{halfword}),
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// Dma Transfers
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0x0400_00B8 => bus.io.dma0.writeWordCount(halfword),
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0x0400_00BA => bus.io.dma0.writeCntHigh(halfword),
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0x0400_00C4 => bus.io.dma1.writeWordCount(halfword),
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@ -224,106 +153,67 @@ pub fn write16(bus: *Bus, addr: u32, halfword: u16) void {
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0x0400_00D2 => bus.io.dma2.writeCntHigh(halfword),
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0x0400_00DC => bus.io.dma3.writeWordCount(halfword),
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0x0400_00DE => bus.io.dma3.writeCntHigh(halfword),
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// Timers
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0x0400_0100 => bus.io.tim0.writeCntLow(halfword),
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0x0400_0102 => bus.io.tim0.writeCntHigh(halfword),
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0x0400_0104 => bus.io.tim1.writeCntLow(halfword),
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0x0400_0106 => bus.io.tim1.writeCntHigh(halfword),
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0x0400_0108 => bus.io.tim2.writeCntLow(halfword),
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0x0400_010A => bus.io.tim2.writeCntHigh(halfword),
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0x0400_010C => bus.io.tim3.writeCntLow(halfword),
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0x0400_010E => bus.io.tim3.writeCntHigh(halfword),
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// Serial Communication 1
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0x0400_0100 => log.warn("Wrote 0x{X:0>4} to TM0CNT_L", .{halfword}),
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0x0400_0102 => log.warn("Wrote 0x{X:0>4} to TM0CNT_H", .{halfword}),
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0x0400_0104 => log.warn("Wrote 0x{X:0>4} to TM1CNT_L", .{halfword}),
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0x0400_0106 => log.warn("Wrote 0x{X:0>4} to TM1CNT_H", .{halfword}),
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0x0400_0108 => log.warn("Wrote 0x{X:0>4} to TM2CNT_L", .{halfword}),
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0x0400_010A => log.warn("Wrote 0x{X:0>4} to TM2CNT_H", .{halfword}),
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0x0400_010C => log.warn("Wrote 0x{X:0>4} to TM3CNT_L", .{halfword}),
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0x0400_010E => log.warn("Wrote 0x{X:0>4} to TM3CNT_H", .{halfword}),
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0x0400_0120 => log.warn("Wrote 0x{X:0>4} to SIOMULTI0", .{halfword}),
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0x0400_0122 => log.warn("Wrote 0x{X:0>4} to SIOMULTI1", .{halfword}),
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0x0400_0124 => log.warn("Wrote 0x{X:0>4} to SIOMULTI2", .{halfword}),
|
||||
0x0400_0126 => log.warn("Wrote 0x{X:0>4} to SIOMULTI3", .{halfword}),
|
||||
0x0400_0128 => log.warn("Wrote 0x{X:0>4} to SIOCNT", .{halfword}),
|
||||
0x0400_012A => log.warn("Wrote 0x{X:0>4} to SIOMLT_SEND", .{halfword}),
|
||||
|
||||
// Keypad Input
|
||||
0x0400_0130 => log.warn("Wrote 0x{X:0>4} to KEYINPUT. Ignored", .{halfword}),
|
||||
0x0400_0132 => log.warn("Wrote 0x{X:0>4} to KEYCNT", .{halfword}),
|
||||
|
||||
// Serial Communication 2
|
||||
0x0400_0134 => log.warn("Wrote 0x{X:0>4} to RCNT", .{halfword}),
|
||||
|
||||
// Interrupts
|
||||
0x0400_0200 => bus.io.ie.raw = halfword,
|
||||
0x0400_0202 => bus.io.irq.raw &= ~halfword,
|
||||
0x0400_0204 => log.warn("Wrote 0x{X:0>4} to WAITCNT", .{halfword}),
|
||||
0x0400_0208 => bus.io.ime = halfword & 1 == 1,
|
||||
else => undWrite("Tried to write 0x{X:0>4} to 0x{X:0>8}", .{ halfword, addr }),
|
||||
else => std.debug.panic("Tried to write 0x{X:0>4} to 0x{X:0>8}", .{ halfword, addr }),
|
||||
}
|
||||
}
|
||||
|
||||
pub fn read8(bus: *const Bus, addr: u32) u8 {
|
||||
return switch (addr) {
|
||||
// Display
|
||||
0x0400_0000 => @truncate(u8, bus.ppu.dispcnt.raw),
|
||||
0x0400_0004 => @truncate(u8, bus.ppu.dispstat.raw),
|
||||
0x0400_0006 => @truncate(u8, bus.ppu.vcount.raw),
|
||||
|
||||
// Sound
|
||||
0x0400_0089 => unimplementedRead("Read (high) byte from SOUNDBIAS", .{}),
|
||||
|
||||
// Serial Communication 1
|
||||
0x0400_0128 => unimplementedRead("Read (low) byte from SIOCNT", .{}),
|
||||
|
||||
// Interrupts
|
||||
0x0400_0200 => @truncate(u8, bus.io.ie.raw),
|
||||
0x0400_0300 => @enumToInt(bus.io.postflg),
|
||||
else => undRead("Tried to read byte from 0x{X:0>8}", .{addr}),
|
||||
0x0400_0006 => @truncate(u8, bus.ppu.vcount.raw),
|
||||
0x0400_0089 => failedRead("Tried to read (high) byte from SOUNDBIAS", .{}),
|
||||
else => std.debug.panic("Tried to read byte from 0x{X:0>8}", .{addr}),
|
||||
};
|
||||
}
|
||||
|
||||
pub fn write8(self: *Bus, addr: u32, byte: u8) void {
|
||||
switch (addr) {
|
||||
// Display
|
||||
0x0400_0004 => self.ppu.dispstat.raw = (self.ppu.dispstat.raw & 0xFF00) | byte,
|
||||
0x0400_0005 => self.ppu.dispstat.raw = (@as(u16, byte) << 8) | (self.ppu.dispstat.raw & 0xFF),
|
||||
|
||||
// Sound
|
||||
0x0400_0063 => log.warn("Wrote 0x{X:0>2} to SOUND1CNT_H (high)", .{byte}),
|
||||
0x0400_0065 => log.warn("Wrote 0x{X:0>2} to SOUND1CNT_X (high)", .{byte}),
|
||||
0x0400_0069 => log.warn("Wrote 0x{X:0>2} to SOUND2CNT_L (high)", .{byte}),
|
||||
0x0400_006D => log.warn("Wrote 0x{X:0>2} to SOUND2CNT_H (high)", .{byte}),
|
||||
0x0400_0070 => log.warn("Wrote 0x{X:0>2} to SOUND3CNT_L (low)", .{byte}),
|
||||
0x0400_0079 => log.warn("Wrote 0x{X:0>2} to SOUND4CNT_L (high)", .{byte}),
|
||||
0x0400_007D => log.warn("Wrote 0x{X:0>2} to SOUND4CNT_H (high)", .{byte}),
|
||||
0x0400_0080 => log.warn("Wrote 0x{X:0>2} to SOUNDCNT_L (low)", .{byte}),
|
||||
0x0400_0084 => log.warn("Wrote 0x{X:0>2} to SOUNDCNT_X (low)", .{byte}),
|
||||
0x0400_0089 => log.warn("Wrote 0x{X:0>2} to SOUNDBIAS (high)", .{byte}),
|
||||
|
||||
// Serial Communication 1
|
||||
0x0400_0128 => log.warn("Wrote 0x{X:0>2} to SIOCNT (low)", .{byte}),
|
||||
|
||||
// Serial Communication 2
|
||||
0x0400_0140 => log.warn("Wrote 0x{X:0>2} to JOYCNT (low)", .{byte}),
|
||||
|
||||
// Interrupts
|
||||
0x0400_0208 => self.io.ime = byte & 1 == 1,
|
||||
0x0400_0301 => self.io.haltcnt = if (byte >> 7 & 1 == 0) .Halt else std.debug.panic("TODO: Implement STOP", .{}),
|
||||
else => undWrite("Tried to write 0x{X:0>2} to 0x{X:0>8}", .{ byte, addr }),
|
||||
0x0400_0063 => log.warn("Tried to write 0x{X:0>2} to SOUND1CNT_H (high)", .{byte}),
|
||||
0x0400_0065 => log.warn("Tried to write 0x{X:0>2} to SOUND1CNT_X (high)", .{byte}),
|
||||
0x0400_0069 => log.warn("Tried to write 0x{X:0>2} to SOUND2CNT_L (high)", .{byte}),
|
||||
0x0400_006D => log.warn("Tried to write 0x{X:0>2} to SOUND2CNT_H (high)", .{byte}),
|
||||
0x0400_0070 => log.warn("Tried to write 0x{X:0>2} to SOUND3CNT_L (low)", .{byte}),
|
||||
0x0400_0079 => log.warn("Tried to write 0x{X:0>2} to SOUND4CNT_L (high)", .{byte}),
|
||||
0x0400_007D => log.warn("Tried to write 0x{X:0>2} to SOUND4CNT_H (high)", .{byte}),
|
||||
0x0400_0080 => log.warn("Tried to write 0x{X:0>2} to SOUNDCNT_L (low)", .{byte}),
|
||||
0x0400_0089 => log.warn("Tried to write 0x{X:0>2} to SOUNDBIAS (high)", .{byte}),
|
||||
else => std.debug.panic("Tried to write 0x{X:0>2} to 0x{X:0>8}", .{ byte, addr }),
|
||||
}
|
||||
}
|
||||
|
||||
fn undRead(comptime format: []const u8, args: anytype) u8 {
|
||||
if (panic_on_und_io) std.debug.panic(format, args) else log.warn(format, args);
|
||||
return 0;
|
||||
}
|
||||
|
||||
fn unimplementedRead(comptime format: []const u8, args: anytype) u8 {
|
||||
fn failedRead(comptime format: []const u8, args: anytype) u8 {
|
||||
log.warn(format, args);
|
||||
return 0;
|
||||
}
|
||||
|
||||
fn undWrite(comptime format: []const u8, args: anytype) void {
|
||||
if (panic_on_und_io) std.debug.panic(format, args) else log.warn(format, args);
|
||||
}
|
||||
|
||||
/// Read / Write
|
||||
pub const PostFlag = enum(u1) {
|
||||
FirstBoot = 0,
|
||||
|
|
@ -453,12 +343,3 @@ pub const DmaControl = extern union {
|
|||
enabled: Bit(u16, 15),
|
||||
raw: u16,
|
||||
};
|
||||
|
||||
/// Read / Write
|
||||
pub const TimerControl = extern union {
|
||||
frequency: Bitfield(u16, 0, 2),
|
||||
cascade: Bit(u16, 2),
|
||||
irq: Bit(u16, 6),
|
||||
enabled: Bit(u16, 7),
|
||||
raw: u16,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1,131 +0,0 @@
|
|||
const std = @import("std");
|
||||
|
||||
const TimerControl = @import("io.zig").TimerControl;
|
||||
const Io = @import("io.zig").Io;
|
||||
const Scheduler = @import("../scheduler.zig").Scheduler;
|
||||
const Event = @import("../scheduler.zig").Event;
|
||||
const Arm7tdmi = @import("../cpu.zig").Arm7tdmi;
|
||||
|
||||
const log = std.log.scoped(.Timer);
|
||||
|
||||
pub fn Timer(comptime id: u2) type {
|
||||
return struct {
|
||||
const Self = @This();
|
||||
|
||||
/// Read Only, Internal. Please use self.counter()
|
||||
_counter: u16,
|
||||
|
||||
/// Write Only, Internal. Please use self.writeCntLow()
|
||||
_reload: u16,
|
||||
|
||||
/// Write Only, Internal. Please use self.WriteCntHigh()
|
||||
cnt: TimerControl,
|
||||
|
||||
/// Internal.
|
||||
sched: *Scheduler,
|
||||
|
||||
/// Internal
|
||||
_start_timestamp: u64,
|
||||
|
||||
pub fn init(sched: *Scheduler) Self {
|
||||
return .{
|
||||
._reload = 0,
|
||||
._counter = 0,
|
||||
.cnt = .{ .raw = 0x0000 },
|
||||
.sched = sched,
|
||||
._start_timestamp = 0,
|
||||
};
|
||||
}
|
||||
|
||||
pub fn counter(self: *const Self) u16 {
|
||||
if (self.cnt.cascade.read())
|
||||
return self._counter
|
||||
else
|
||||
return self._counter +% @truncate(u16, (self.sched.now() - self._start_timestamp) / self.frequency());
|
||||
}
|
||||
|
||||
pub fn writeCnt(self: *Self, word: u32) void {
|
||||
self.writeCntLow(@truncate(u16, word));
|
||||
self.writeCntHigh(@truncate(u16, word >> 16));
|
||||
}
|
||||
|
||||
pub fn writeCntLow(self: *Self, halfword: u16) void {
|
||||
self._reload = halfword;
|
||||
}
|
||||
|
||||
pub fn writeCntHigh(self: *Self, halfword: u16) void {
|
||||
const new = TimerControl{ .raw = halfword };
|
||||
|
||||
// If Timer happens to be enabled, It will either be resheduled or disabled
|
||||
self.sched.removeScheduledEvent(.{ .TimerOverflow = id });
|
||||
|
||||
if (!self.cnt.enabled.read() and new.enabled.read()) {
|
||||
// Reload on Rising edge
|
||||
self._counter = self._reload;
|
||||
|
||||
if (!new.cascade.read()) self.scheduleOverflow();
|
||||
}
|
||||
|
||||
self.cnt.raw = halfword;
|
||||
}
|
||||
|
||||
pub fn handleOverflow(self: *Self, cpu: *Arm7tdmi, io: *Io) void {
|
||||
// Fire IRQ if enabled
|
||||
if (self.cnt.irq.read()) {
|
||||
switch (id) {
|
||||
0 => io.irq.tim0_overflow.set(),
|
||||
1 => io.irq.tim1_overflow.set(),
|
||||
2 => io.irq.tim2_overflow.set(),
|
||||
3 => io.irq.tim3_overflow.set(),
|
||||
}
|
||||
|
||||
cpu.handleInterrupt();
|
||||
}
|
||||
|
||||
// Perform Cascade Behaviour
|
||||
switch (id) {
|
||||
0 => if (io.tim1.cnt.cascade.read()) {
|
||||
io.tim1._counter +%= 1;
|
||||
|
||||
if (io.tim1._counter == 0)
|
||||
io.tim1.handleOverflow(cpu, io);
|
||||
},
|
||||
1 => if (io.tim2.cnt.cascade.read()) {
|
||||
io.tim2._counter +%= 1;
|
||||
|
||||
if (io.tim2._counter == 0)
|
||||
io.tim2.handleOverflow(cpu, io);
|
||||
},
|
||||
2 => if (io.tim3.cnt.cascade.read()) {
|
||||
io.tim3._counter +%= 1;
|
||||
|
||||
if (io.tim3._counter == 0)
|
||||
io.tim3.handleOverflow(cpu, io);
|
||||
},
|
||||
3 => {}, // There is no Timer for TIM3 to "cascade" to,
|
||||
}
|
||||
|
||||
// Reschedule Timer if we're not cascading
|
||||
if (!self.cnt.cascade.read()) {
|
||||
self._counter = self._reload;
|
||||
self.scheduleOverflow();
|
||||
}
|
||||
}
|
||||
|
||||
fn scheduleOverflow(self: *Self) void {
|
||||
const when = (@as(u64, 0x10000) - self._counter) * self.frequency();
|
||||
|
||||
self._start_timestamp = self.sched.now();
|
||||
self.sched.push(.{ .TimerOverflow = id }, self.sched.now() + when);
|
||||
}
|
||||
|
||||
fn frequency(self: *const Self) u16 {
|
||||
return switch (self.cnt.frequency.read()) {
|
||||
0 => 1,
|
||||
1 => 64,
|
||||
2 => 256,
|
||||
3 => 1024,
|
||||
};
|
||||
}
|
||||
};
|
||||
}
|
||||
|
|
@ -27,10 +27,6 @@ pub const Scheduler = struct {
|
|||
self.queue.deinit();
|
||||
}
|
||||
|
||||
pub inline fn now(self: *const Self) u64 {
|
||||
return self.tick;
|
||||
}
|
||||
|
||||
pub fn handleEvent(self: *Self, cpu: *Arm7tdmi, bus: *Bus) void {
|
||||
const should_handle = if (self.queue.peek()) |e| self.tick >= e.tick else false;
|
||||
const stat = &bus.ppu.dispstat;
|
||||
|
|
@ -43,8 +39,7 @@ pub const Scheduler = struct {
|
|||
|
||||
switch (event.kind) {
|
||||
.HeatDeath => {
|
||||
log.err("A u64 overflowered. This *actually* should never happen.", .{});
|
||||
unreachable;
|
||||
std.debug.panic("[Scheduler] Somehow, a u64 overflowed", .{});
|
||||
},
|
||||
.HBlank => {
|
||||
// The End of a Hblank (During Draw or Vblank)
|
||||
|
|
@ -115,35 +110,6 @@ pub const Scheduler = struct {
|
|||
bus.ppu.dispstat.hblank.set();
|
||||
self.push(.HBlank, self.tick + (68 * 4));
|
||||
},
|
||||
.TimerOverflow => |id| {
|
||||
// log.warn("TIM{} Overflowed", .{id});
|
||||
|
||||
switch (id) {
|
||||
0 => bus.io.tim0.handleOverflow(cpu, &bus.io),
|
||||
1 => bus.io.tim1.handleOverflow(cpu, &bus.io),
|
||||
2 => bus.io.tim2.handleOverflow(cpu, &bus.io),
|
||||
3 => bus.io.tim3.handleOverflow(cpu, &bus.io),
|
||||
}
|
||||
},
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/// Removes the **first** scheduled event of type `needle`
|
||||
pub fn removeScheduledEvent(self: *Self, needle: EventKind) void {
|
||||
var it = self.queue.iterator();
|
||||
|
||||
var i: usize = 0;
|
||||
while (it.next()) |event| : (i += 1) {
|
||||
if (std.meta.eql(event.kind, needle)) {
|
||||
|
||||
// This invalidates the iterator
|
||||
_ = self.queue.removeIndex(i);
|
||||
|
||||
// Since removing something from the PQ invalidates the iterator,
|
||||
// this implementation can safely only remove the first instance of
|
||||
// a Scheduled Event. Exit Early
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -168,10 +134,9 @@ fn lessThan(_: void, a: Event, b: Event) Order {
|
|||
return std.math.order(a.tick, b.tick);
|
||||
}
|
||||
|
||||
pub const EventKind = union(enum) {
|
||||
pub const EventKind = enum {
|
||||
HeatDeath,
|
||||
HBlank,
|
||||
VBlank,
|
||||
Draw,
|
||||
TimerOverflow: u2,
|
||||
};
|
||||
|
|
|
|||
Loading…
Reference in New Issue