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base: paoda:8ab7a178c136fcd19e4b3fe1d5a46a5f25877af2
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paoda:main
paoda:april-fools
paoda:window
paoda:apu-things
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compare: paoda:f9013cf9db2f8c4527534ffa69fc5c57be46a663
Branches Tags
paoda:main
paoda:april-fools
paoda:window
paoda:apu-things

No commits in common. "8ab7a178c136fcd19e4b3fe1d5a46a5f25877af2" and "f9013cf9db2f8c4527534ffa69fc5c57be46a663" have entirely different histories.
8ab7a178c1 ... f9013cf9db

7 changed files with 69 additions and 87 deletions
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13
src/Bus.zig
View File

@ -9,7 +9,6 @@ const Ppu = @import("ppu.zig").Ppu;
const Scheduler = @import("scheduler.zig").Scheduler; const Scheduler = @import("scheduler.zig").Scheduler;
const Allocator = std.mem.Allocator; const Allocator = std.mem.Allocator;
const log = std.log.scoped(.Bus);
const Self = @This(); const Self = @This();
pak: GamePak, pak: GamePak,
@ -57,7 +56,7 @@ pub fn read32(self: *const Self, addr: u32) u32 {
0x0C00_0000...0x0DFF_FFFF => self.pak.get32(addr - 0x0C00_0000), 0x0C00_0000...0x0DFF_FFFF => self.pak.get32(addr - 0x0C00_0000),
else => { else => {
log.warn("32-bit read from 0x{X:0>8}", .{addr}); std.log.warn("[Bus:32] ZBA tried to read from 0x{X:}", .{addr});
return 0x0000_0000; return 0x0000_0000;
}, },
}; };
@ -77,7 +76,7 @@ pub fn write32(self: *Self, addr: u32, word: u32) void {
0x0600_0000...0x0601_7FFF => self.ppu.vram.set32(addr - 0x0600_0000, word), 0x0600_0000...0x0601_7FFF => self.ppu.vram.set32(addr - 0x0600_0000, word),
0x0700_0000...0x0700_03FF => std.debug.panic("[Bus:32] wrote 0x{X:} to 0x{X:} in OAM", .{ word, addr }), 0x0700_0000...0x0700_03FF => std.debug.panic("[Bus:32] wrote 0x{X:} to 0x{X:} in OAM", .{ word, addr }),
else => log.warn("32-bit write of 0x{X:0>8} to 0x{X:0>8}", .{ word, addr }), else => std.log.warn("[Bus:32] ZBA tried to write 0x{X:} to 0x{X:}", .{ word, addr }),
} }
} }
@ -100,7 +99,7 @@ pub fn read16(self: *const Self, addr: u32) u16 {
0x0C00_0000...0x0DFF_FFFF => self.pak.get16(addr - 0x0C00_0000), 0x0C00_0000...0x0DFF_FFFF => self.pak.get16(addr - 0x0C00_0000),
else => { else => {
log.warn("16-bit read from 0x{X:0>8}", .{addr}); std.log.warn("[Bus:16] ZBA tried to read from 0x{X:}", .{addr});
return 0x0000; return 0x0000;
}, },
}; };
@ -119,7 +118,7 @@ pub fn write16(self: *Self, addr: u32, halfword: u16) void {
0x0600_0000...0x0601_7FFF => self.ppu.vram.set16(addr - 0x0600_0000, halfword), 0x0600_0000...0x0601_7FFF => self.ppu.vram.set16(addr - 0x0600_0000, halfword),
0x0700_0000...0x0700_03FF => std.debug.panic("[Bus:16] write 0x{X:} to 0x{X:} in OAM", .{ halfword, addr }), 0x0700_0000...0x0700_03FF => std.debug.panic("[Bus:16] write 0x{X:} to 0x{X:} in OAM", .{ halfword, addr }),
else => log.warn("16-bit write of 0x{X:0>4} to 0x{X:0>8}", .{ halfword, addr }), else => std.log.warn("[Bus:16] ZBA tried to write 0x{X:} to 0x{X:}", .{ halfword, addr }),
} }
} }
@ -143,7 +142,7 @@ pub fn read8(self: *const Self, addr: u32) u8 {
0x0E00_0000...0x0E00_FFFF => std.debug.panic("[Bus:8] read from 0x{X:} in Game Pak SRAM", .{addr}), 0x0E00_0000...0x0E00_FFFF => std.debug.panic("[Bus:8] read from 0x{X:} in Game Pak SRAM", .{addr}),
else => { else => {
log.warn("8-bit read from 0x{X:0>8}", .{addr}); std.log.warn("[Bus:8] ZBA tried to read from 0x{X:}", .{addr});
return 0x00; return 0x00;
}, },
}; };
@ -158,6 +157,6 @@ pub fn write8(self: *Self, addr: u32, byte: u8) void {
// External Memory (Game Pak) // External Memory (Game Pak)
0x0E00_0000...0x0E00_FFFF => std.debug.panic("[Bus:8] write 0x{X:} to 0x{X:} in Game Pak SRAM", .{ byte, addr }), 0x0E00_0000...0x0E00_FFFF => std.debug.panic("[Bus:8] write 0x{X:} to 0x{X:} in Game Pak SRAM", .{ byte, addr }),
else => log.warn("8-bit write of 0x{X:0>2} to 0x{X:0>8}", .{ byte, addr }), else => std.log.warn("[Bus:8] ZBA tried to write 0x{X:} to 0x{X:}", .{ byte, addr }),
} }
} }

105
src/cpu.zig
View File

@ -97,8 +97,8 @@ pub const Arm7tdmi = struct {
self.binary_log = is_binary; self.binary_log = is_binary;
} }
inline fn bankedIdx(mode: Mode, kind: BankedKind) usize { inline fn bankedIdx(mode: Mode) usize {
const idx: usize = switch (mode) { return switch (mode) {
.User, .System => 0, .User, .System => 0,
.Supervisor => 1, .Supervisor => 1,
.Abort => 2, .Abort => 2,
@ -106,11 +106,9 @@ pub const Arm7tdmi = struct {
.Irq => 4, .Irq => 4,
.Fiq => 5, .Fiq => 5,
}; };
return (idx * 2) + if (kind == .R14) @as(usize, 1) else 0;
} }
inline fn bankedSpsrIndex(mode: Mode) usize { inline fn spsrIdx(mode: Mode) usize {
return switch (mode) { return switch (mode) {
.Supervisor => 0, .Supervisor => 0,
.Abort => 1, .Abort => 1,
@ -121,10 +119,6 @@ pub const Arm7tdmi = struct {
}; };
} }
inline fn bankedFiqIdx(i: usize, mode: Mode) usize {
return (i * 2) + if (mode == .Fiq) @as(usize, 1) else 0;
}
pub inline fn hasSPSR(self: *const Self) bool { pub inline fn hasSPSR(self: *const Self) bool {
const mode = getModeChecked(self, self.cpsr.mode.read()); const mode = getModeChecked(self, self.cpsr.mode.read());
return switch (mode) { return switch (mode) {
@ -153,77 +147,84 @@ pub const Arm7tdmi = struct {
pub fn setUserModeRegister(self: *Self, idx: usize, value: u32) void { pub fn setUserModeRegister(self: *Self, idx: usize, value: u32) void {
const current = getModeChecked(self, self.cpsr.mode.read()); const current = getModeChecked(self, self.cpsr.mode.read());
switch (idx) { if (idx < 8) {
8...12 => { self.r[idx] = value;
} else if (idx < 13) {
if (current == .Fiq) { if (current == .Fiq) {
self.banked_fiq[bankedFiqIdx(idx - 8, .User)] = value; const user_offset: usize = 0;
self.banked_fiq[(idx - 8) * 2 + user_offset] = value;
} else self.r[idx] = value; } else self.r[idx] = value;
}, } else if (idx < 15) {
13, 14 => switch (current) { switch (current) {
.User, .System => self.r[idx] = value, .User, .System => self.r[idx] = value,
else => { else => {
const kind = std.meta.intToEnum(BankedKind, idx - 13) catch unreachable; self.banked_r[bankedIdx(.User) * 2 + (idx - 13)] = value;
self.banked_r[bankedIdx(.User, kind)] = value;
}, },
},
else => self.r[idx] = value, // R0 -> R7 and R15
} }
} else self.r[idx] = value;
} }
pub fn getUserModeRegister(self: *Self, idx: usize) u32 { pub fn getUserModeRegister(self: *Self, idx: usize) u32 {
const current = getModeChecked(self, self.cpsr.mode.read()); const current = getModeChecked(self, self.cpsr.mode.read());
return switch (idx) { var result: u32 = undefined;
8...12 => if (current == .Fiq) self.banked_fiq[bankedFiqIdx(idx - 8, .User)] else self.r[idx], if (idx < 8) {
13, 14 => switch (current) { result = self.r[idx];
.User, .System => self.r[idx], } else if (idx < 13) {
else => blk: { if (current == .Fiq) {
const kind = std.meta.intToEnum(BankedKind, idx - 13) catch unreachable; const user_offset: usize = 0;
break :blk self.banked_r[bankedIdx(.User, kind)]; result = self.banked_fiq[(idx - 8) * 2 + user_offset];
} else result = self.r[idx];
} else if (idx < 15) {
switch (current) {
.User, .System => result = self.r[idx],
else => {
result = self.banked_r[bankedIdx(.User) * 2 + (idx - 13)];
}, },
}, }
else => self.r[idx], // R0 -> R7 and R15 } else result = self.r[idx];
};
return result;
} }
pub fn changeMode(self: *Self, next: Mode) void { pub fn changeMode(self: *Self, next: Mode) void {
const now = getModeChecked(self, self.cpsr.mode.read()); const now = getModeChecked(self, self.cpsr.mode.read());
// Bank R8 -> r12 // Bank R8 -> r12
var i: usize = 0; var r: usize = 8;
while (i < 5) : (i += 1) { while (r <= 12) : (r += 1) {
self.banked_fiq[bankedFiqIdx(i, now)] = self.r[8 + i]; self.banked_fiq[(r - 8) * 2 + if (now == .Fiq) @as(usize, 1) else 0] = self.r[r];
} }
// Bank r13, r14, SPSR // Bank r13, r14, SPSR
switch (now) { switch (now) {
.User, .System => { .User, .System => {
self.banked_r[bankedIdx(now, .R13)] = self.r[13]; self.banked_r[bankedIdx(now) * 2 + 0] = self.r[13];
self.banked_r[bankedIdx(now, .R14)] = self.r[14]; self.banked_r[bankedIdx(now) * 2 + 1] = self.r[14];
}, },
else => { else => {
self.banked_r[bankedIdx(now, .R13)] = self.r[13]; self.banked_r[bankedIdx(now) * 2 + 0] = self.r[13];
self.banked_r[bankedIdx(now, .R14)] = self.r[14]; self.banked_r[bankedIdx(now) * 2 + 1] = self.r[14];
self.banked_spsr[bankedSpsrIndex(now)] = self.spsr; self.banked_spsr[spsrIdx(now)] = self.spsr;
}, },
} }
// Grab R8 -> R12 // Grab R8 -> R12
i = 0; r = 8;
while (i < 5) : (i += 1) { while (r <= 12) : (r += 1) {
self.r[8 + i] = self.banked_fiq[bankedFiqIdx(i, next)]; self.r[r] = self.banked_fiq[(r - 8) * 2 + if (next == .Fiq) @as(usize, 1) else 0];
} }
// Grab r13, r14, SPSR // Grab r13, r14, SPSR
switch (next) { switch (next) {
.User, .System => { .User, .System => {
self.r[13] = self.banked_r[bankedIdx(next, .R13)]; self.r[13] = self.banked_r[bankedIdx(next) * 2 + 0];
self.r[14] = self.banked_r[bankedIdx(next, .R14)]; self.r[14] = self.banked_r[bankedIdx(next) * 2 + 1];
}, },
else => { else => {
self.r[13] = self.banked_r[bankedIdx(next, .R13)]; self.r[13] = self.banked_r[bankedIdx(next) * 2 + 0];
self.r[14] = self.banked_r[bankedIdx(next, .R14)]; self.r[14] = self.banked_r[bankedIdx(next) * 2 + 1];
self.spsr = self.banked_spsr[bankedSpsrIndex(next)]; self.spsr = self.banked_spsr[spsrIdx(next)];
}, },
} }
@ -231,15 +232,16 @@ pub const Arm7tdmi = struct {
} }
pub fn fastBoot(self: *Self) void { pub fn fastBoot(self: *Self) void {
self.r = std.mem.zeroes([16]u32);
self.r[0] = 0x08000000; self.r[0] = 0x08000000;
self.r[1] = 0x000000EA; self.r[1] = 0x000000EA;
// GPRs 2 -> 12 *should* already be 0 initialized
self.r[13] = 0x0300_7F00; self.r[13] = 0x0300_7F00;
self.r[14] = 0x0000_0000;
self.r[15] = 0x0800_0000; self.r[15] = 0x0800_0000;
self.banked_r[bankedIdx(.Irq, .R13)] = 0x0300_7FA0; // Set r13_irq and r14_svc to their respective values
self.banked_r[bankedIdx(.Supervisor, .R13)] = 0x0300_7FE0; self.banked_r[bankedIdx(.Irq) * 2 + 0] = 0x0300_7FA0;
self.banked_r[bankedIdx(.Supervisor) * 2 + 0] = 0x0300_7FE0;
self.cpsr.raw = 0x6000001F; self.cpsr.raw = 0x6000001F;
} }
@ -494,7 +496,7 @@ fn thumbPopulate() [0x400]ThumbInstrFn {
}, },
0b001 => blk: { 0b001 => blk: {
const L = i >> 5 & 1 == 1; const L = i >> 5 & 1 == 1;
const rd = i >> 2 & 0x7; const rd = i >> 2 & 0x3;
break :blk format11(L, rd); break :blk format11(L, rd);
}, },
0b010 => blk: { 0b010 => blk: {
@ -630,11 +632,6 @@ const Mode = enum(u5) {
System = 0b11111, System = 0b11111,
}; };
const BankedKind = enum(u1) {
R13 = 0,
R14,
};
fn getMode(bits: u5) ?Mode { fn getMode(bits: u5) ?Mode {
return std.meta.intToEnum(Mode, bits) catch null; return std.meta.intToEnum(Mode, bits) catch null;
} }

6
src/cpu/arm/psr_transfer.zig
View File

@ -5,8 +5,6 @@ const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
const InstrFn = @import("../../cpu.zig").ArmInstrFn; const InstrFn = @import("../../cpu.zig").ArmInstrFn;
const PSR = @import("../../cpu.zig").PSR; const PSR = @import("../../cpu.zig").PSR;
const log = std.log.scoped(.PsrTransfer);
pub fn psrTransfer(comptime I: bool, comptime R: bool, comptime kind: u2) InstrFn { pub fn psrTransfer(comptime I: bool, comptime R: bool, comptime kind: u2) InstrFn {
return struct { return struct {
fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u32) void { fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u32) void {
@ -15,7 +13,7 @@ pub fn psrTransfer(comptime I: bool, comptime R: bool, comptime kind: u2) InstrF
// MRS // MRS
const rd = opcode >> 12 & 0xF; const rd = opcode >> 12 & 0xF;
if (R and !cpu.hasSPSR()) log.warn("Tried to read SPSR from User/System Mode", .{}); if (R and !cpu.hasSPSR()) std.log.warn("[CPU/PSR Transfer] Tried to read SPSR from User/System Mode", .{});
cpu.r[rd] = if (R) cpu.spsr.raw else cpu.cpsr.raw; cpu.r[rd] = if (R) cpu.spsr.raw else cpu.cpsr.raw;
}, },
0b10 => { 0b10 => {
@ -24,7 +22,7 @@ pub fn psrTransfer(comptime I: bool, comptime R: bool, comptime kind: u2) InstrF
const rm_idx = opcode & 0xF; const rm_idx = opcode & 0xF;
const right = if (I) std.math.rotr(u32, opcode & 0xFF, (opcode >> 8 & 0xF) << 1) else cpu.r[rm_idx]; const right = if (I) std.math.rotr(u32, opcode & 0xFF, (opcode >> 8 & 0xF) << 1) else cpu.r[rm_idx];
if (R and !cpu.hasSPSR()) log.warn("Tried to write to SPSR in User/System Mode", .{}); if (R and !cpu.hasSPSR()) std.log.warn("[CPU/PSR Transfer] Tried to write to SPSR User/System Mode", .{});
if (R) { if (R) {
if (cpu.isPrivileged()) cpu.spsr.raw = fieldMask(&cpu.spsr, field_mask, right); if (cpu.isPrivileged()) cpu.spsr.raw = fieldMask(&cpu.spsr, field_mask, right);

8
src/cpu/thumb/block_data_transfer.zig
View File

@ -5,12 +5,12 @@ const InstrFn = @import("../../cpu.zig").ThumbInstrFn;
pub fn format14(comptime L: bool, comptime R: bool) InstrFn { pub fn format14(comptime L: bool, comptime R: bool) InstrFn {
return struct { return struct {
fn inner(cpu: *Arm7tdmi, bus: *Bus, opcode: u16) void { fn inner(cpu: *Arm7tdmi, bus: *Bus, opcode: u16) void {
const count = @boolToInt(R) + countRlist(opcode); const count = countRlist(opcode);
const start = cpu.r[13] - if (!L) count * 4 else 0; const start = cpu.r[13] - if (!L) 4 * (@boolToInt(R) + count) else 0;
var end = cpu.r[13]; var end = cpu.r[13];
if (L) { if (L) {
end += count * 4; end += 4 * (@boolToInt(R) + count);
} else { } else {
end -= 4; end -= 4;
} }
@ -40,7 +40,7 @@ pub fn format14(comptime L: bool, comptime R: bool) InstrFn {
address += 4; address += 4;
} }
cpu.r[13] = if (L) end else start; cpu.r[13] = if (L) end else cpu.r[13] - 4 * (@boolToInt(R) + count);
} }
}.inner; }.inner;
} }

9
src/cpu/thumb/data_processing.zig
View File

@ -1,5 +1,3 @@
const std = @import("std");
const Bus = @import("../../Bus.zig"); const Bus = @import("../../Bus.zig");
const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi; const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
const InstrFn = @import("../../cpu.zig").ThumbInstrFn; const InstrFn = @import("../../cpu.zig").ThumbInstrFn;
@ -10,8 +8,6 @@ const sub = @import("../arm/data_processing.zig").sub;
const cmp = @import("../arm/data_processing.zig").cmp; const cmp = @import("../arm/data_processing.zig").cmp;
const setLogicOpFlags = @import("../arm/data_processing.zig").setLogicOpFlags; const setLogicOpFlags = @import("../arm/data_processing.zig").setLogicOpFlags;
const log = std.log.scoped(.Thumb1);
pub fn format1(comptime op: u2, comptime offset: u5) InstrFn { pub fn format1(comptime op: u2, comptime offset: u5) InstrFn {
return struct { return struct {
fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void { fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void {
@ -45,10 +41,7 @@ pub fn format1(comptime op: u2, comptime offset: u5) InstrFn {
break :blk shifter.arithmeticRight(true, &cpu.cpsr, cpu.r[rs], offset); break :blk shifter.arithmeticRight(true, &cpu.cpsr, cpu.r[rs], offset);
} }
}, },
else => { else => cpu.panic("[CPU|THUMB|Fmt1] {} is an invalid op", .{op}),
log.err("0b{b:0>2} is not a valid op", .{op});
// TODO: Should we panic here?
},
}; };
// Equivalent to an ARM MOVS // Equivalent to an ARM MOVS

6
src/cpu/thumb/processing_branch.zig
View File

@ -15,11 +15,7 @@ pub fn format5(comptime op: u2, comptime h1: u1, comptime h2: u1) InstrFn {
const dst = if (dst_idx == 0xF) (cpu.r[dst_idx] + 2) & 0xFFFF_FFFE else cpu.r[dst_idx]; const dst = if (dst_idx == 0xF) (cpu.r[dst_idx] + 2) & 0xFFFF_FFFE else cpu.r[dst_idx];
switch (op) { switch (op) {
0b00 => { 0b00 => cpu.r[dst_idx] = add(false, cpu, dst, src) & if (dst_idx == 0xF) 0xFFFF_FFFC else @as(u32, 0xFFF_FFFF), // ADD
// ADD
const sum = add(false, cpu, dst, src);
cpu.r[dst_idx] = if (dst_idx == 0xF) sum & 0xFFFF_FFFC else sum;
},
0b01 => cmp(cpu, dst, src), // CMP 0b01 => cmp(cpu, dst, src), // CMP
0b10 => { 0b10 => {
// MOV // MOV

3
src/scheduler.zig
View File

@ -6,7 +6,6 @@ const Arm7tdmi = @import("cpu.zig").Arm7tdmi;
const Order = std.math.Order; const Order = std.math.Order;
const PriorityQueue = std.PriorityQueue; const PriorityQueue = std.PriorityQueue;
const Allocator = std.mem.Allocator; const Allocator = std.mem.Allocator;
const log = std.log.scoped(.Scheduler);
pub const Scheduler = struct { pub const Scheduler = struct {
const Self = @This(); const Self = @This();
@ -30,7 +29,7 @@ pub const Scheduler = struct {
if (should_handle) { if (should_handle) {
const event = self.queue.remove(); const event = self.queue.remove();
// log.debug("Handle {} @ tick = {}", .{ event.kind, self.tick }); // std.log.info("[Scheduler] Handle {} at {} ticks", .{ event.kind, self.tick });
switch (event.kind) { switch (event.kind) {
.HeatDeath => { .HeatDeath => {