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base: paoda:800ed6f1a767fc2ccff084386fd3b0e97d5f5ac9
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paoda:april-fools
paoda:window
paoda:apu-things
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compare: paoda:33399e9517e726b905a703e33715a4955db2b0b5
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paoda:main
paoda:april-fools
paoda:window
paoda:apu-things

No commits in common. "800ed6f1a767fc2ccff084386fd3b0e97d5f5ac9" and "33399e9517e726b905a703e33715a4955db2b0b5" have entirely different histories.
800ed6f1a7 ... 33399e9517

4 changed files with 7 additions and 56 deletions
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11
src/cpu.zig
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@ -31,13 +31,11 @@ const format6 = @import("cpu/thumb/format6.zig").format6;
const format78 = @import("cpu/thumb/format78.zig").format78;
const format9 = @import("cpu/thumb/format9.zig").format9;
const format10 = @import("cpu/thumb/format10.zig").format10;
const format11 = @import("cpu/thumb/format11.zig").format11;
const format12 = @import("cpu/thumb/format12.zig").format12;
const format13 = @import("cpu/thumb/format13.zig").format13;
const format14 = @import("cpu/thumb/format14.zig").format14;
const format15 = @import("cpu/thumb/format15.zig").format15;
const format16 = @import("cpu/thumb/format16.zig").format16;
const format17 = @import("cpu/thumb/format17.zig").format17;
const format18 = @import("cpu/thumb/format18.zig").format18;
const format19 = @import("cpu/thumb/format19.zig").format19;
@ -480,17 +478,16 @@ fn thumbPopulate() [0x400]ThumbInstrFn {
lut[i] = format13(S);
} else if (i >> 2 & 0xFF == 0xDF) {
lut[i] = format17();
// Format 17 | Software Interrupt
lut[i] = thumbUndefined;
} else if (i >> 6 & 0xF == 0b1000) {
const L = i >> 5 & 1 == 1;
const offset = i & 0x1F;
lut[i] = format10(L, offset);
} else if (i >> 6 & 0xF == 0b1001) {
const L = i >> 5 & 1 == 1;
const rd = i >> 2 & 0x3;
lut[i] = format11(L, rd);
// Format 11 | SP-relative load / store
lut[i] = thumbUndefined;
} else if (i >> 6 & 0xF == 0b1010) {
const isSP = i >> 5 & 1 == 1;
const rd = i >> 2 & 0x7;

21
src/cpu/thumb/format11.zig
View File

@ -1,21 +0,0 @@
const std = @import("std");
const Bus = @import("../../Bus.zig");
const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
const InstrFn = @import("../../cpu.zig").ThumbInstrFn;
pub fn format11(comptime L: bool, comptime rd: u3) InstrFn {
return struct {
fn inner(cpu: *Arm7tdmi, bus: *Bus, opcode: u16) void {
const offset = (opcode & 0xFF) << 2;
const address = cpu.r[13] + offset;
if (L) {
const value = bus.read32(address & 0xFFFF_FFFC);
cpu.r[rd] = std.math.rotr(u32, value, 8 * (address & 0x3));
} else {
bus.write32(address & 0xFFFF_FFFC, cpu.r[rd]);
}
}
}.inner;
}

7
src/cpu/thumb/format13.zig
View File

@ -4,11 +4,10 @@ const Bus = @import("../../Bus.zig");
const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
const InstrFn = @import("../../cpu.zig").ThumbInstrFn;
pub fn format13(comptime S: bool) InstrFn {
pub fn format13(comptime _: bool) InstrFn {
return struct {
fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void {
const offset = (opcode & 0x7F) << 2;
cpu.r[13] = if (S) cpu.r[13] - offset else cpu.r[13] + offset;
fn inner(cpu: *Arm7tdmi, _: *Bus, _: u16) void {
cpu.panic("[CPU|THUMB|Fmt13] Implement Format 13 THUMB Instructions", .{});
}
}.inner;
}

24
src/cpu/thumb/format17.zig
View File

@ -1,24 +0,0 @@
const std = @import("std");
const Bus = @import("../../Bus.zig");
const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
const InstrFn = @import("../../cpu.zig").ThumbInstrFn;
pub fn format17() InstrFn {
return struct {
fn inner(cpu: *Arm7tdmi, _: *Bus, _: u16) void {
// Copy Values from Current Mode
const r15 = cpu.r[15];
const cpsr = cpu.cpsr.raw;
// Switch Mode
cpu.changeMode(.Supervisor);
cpu.cpsr.t.write(false); // Force ARM Mode
cpu.cpsr.i.write(true); // Disable normal interrupts
cpu.r[14] = r15; // Resume Execution
cpu.spsr.raw = cpsr; // Previous mode CPSR
cpu.r[15] = 0x0000_0008;
}
}.inner;
}