src/bus/io.zig

@@ -22,7 +22,6 @@ pub const Io = struct {
         return switch (addr) {
             0x0400_0000 => @as(u32, self.dispcnt.raw),
             0x0400_0004 => @as(u32, self.dispstat.raw),
-            0x0400_0006 => @as(u32, self.vcount.raw),
             else => std.debug.panic("[I/O:32] tried to read from {X:}", .{addr}),
         };
     }
@@ -31,7 +30,6 @@ pub const Io = struct {
         return switch (addr) {
             0x0400_0000 => self.dispcnt.raw,
             0x0400_0004 => self.dispstat.raw,
-            0x0400_0006 => self.vcount.raw,
             else => std.debug.panic("[I/O:16] tried to read from {X:}", .{addr}),
         };
     }
@@ -48,7 +46,6 @@ pub const Io = struct {
         return switch (addr) {
             0x0400_0000 => @truncate(u8, self.dispcnt.raw),
             0x0400_0004 => @truncate(u8, self.dispstat.raw),
-            0x0400_0006 => @truncate(u8, self.vcount.raw),
             else => std.debug.panic("[I/O:8] tried to read from {X:}", .{addr}),
         };
     }
@@ -57,7 +54,7 @@ pub const Io = struct {
 const DispCnt = extern union {
     bg_mode: Bitfield(u16, 0, 3),
     frame_select: Bit(u16, 4),
-    hblank_interval_free: Bit(u16, 5),
+    hblank_interraw_free: Bit(u16, 5),
     obj_mapping: Bit(u16, 6),
     forced_blank: Bit(u16, 7),
     bg_enable: Bitfield(u16, 8, 4),
@@ -70,11 +67,11 @@ const DispCnt = extern union {
 const DispStat = extern union {
     vblank: Bit(u16, 0),
     hblank: Bit(u16, 1),
-    coincidence: Bit(u16, 2),
+    vcount: Bit(u16, 2),
     vblank_irq: Bit(u16, 3),
     hblank_irq: Bit(u16, 4),
     vcount_irq: Bit(u16, 5),
-    vcount_trigger: Bitfield(u16, 8, 8),
+    vcount_setting: Bitfield(u16, 8, 7),
     raw: u16,
 };
 

src/cpu.zig

@@ -10,7 +10,6 @@ const Scheduler = @import("scheduler.zig").Scheduler;
 const dataProcessing = @import("cpu/data_processing.zig").dataProcessing;
 const singleDataTransfer = @import("cpu/single_data_transfer.zig").singleDataTransfer;
 const halfAndSignedDataTransfer = @import("cpu/half_signed_data_transfer.zig").halfAndSignedDataTransfer;
-const blockDataTransfer = @import("cpu/block_data_transfer.zig").blockDataTransfer;
 const branch = @import("cpu/branch.zig").branch;
 
 pub const InstrFn = fn (*Arm7tdmi, *Bus, u32) void;
@@ -154,16 +153,6 @@ fn populate() [0x1000]InstrFn {
                 lut[i] = singleDataTransfer(I, P, U, B, W, L);
             }
 
-            if (i >> 9 & 0x7 == 0b100) {
-                const P = i >> 8 & 1 == 1;
-                const U = i >> 7 & 1 == 1;
-                const S = i >> 6 & 1 == 1;
-                const W = i >> 5 & 1 == 1;
-                const L = i >> 4 & 1 == 1;
-
-                lut[i] = blockDataTransfer(P, U, S, W, L);
-            }
-
             if (i >> 9 & 0x7 == 0b101) {
                 const L = i >> 8 & 1 == 1;
                 lut[i] = branch(L);

src/cpu/block_data_transfer.zig

@@ -1,55 +0,0 @@
-const std = @import("std");
-
-const Bus = @import("../Bus.zig");
-const Arm7tdmi = @import("../cpu.zig").Arm7tdmi;
-const InstrFn = @import("../cpu.zig").InstrFn;
-
-pub fn blockDataTransfer(comptime P: bool, comptime U: bool, comptime S: bool, comptime W: bool, comptime L: bool) InstrFn {
-    return struct {
-        fn inner(cpu: *Arm7tdmi, bus: *Bus, opcode: u32) void {
-            const rn = opcode >> 16 & 0xF;
-            var base = cpu.r[rn];
-
-            // TODO: For Performance (?) if U we got from 0 -> 0xF, if !U, 0xF -> 0
-            // we can do this and have it be fast because of comptime, baby!
-
-            if (!U) {
-                var count: u32 = 0;
-                var i: u5 = 0;
-                while (i < 0x10) : (i += 1) {
-                    count += opcode >> i & 1;
-                }
-
-                base -= count * 4;
-            }
-
-            var address = if (@boolToInt(P) ^ @boolToInt(U) == 0) base + 4 else base;
-            if (S and opcode >> 15 & 1 == 0) std.debug.panic("[CPU] TODO: STM/LDM with S set but R15 not in transfer list", .{});
-
-            var i: u5 = 0;
-            while (i < 0x10) : (i += 1) {
-                if (opcode >> i & 1 == 1) {
-                    if (L) {
-                        cpu.r[i] = bus.read32(address);
-                        if (S and i == 0xF) std.debug.panic("[CPU] TODO: SPSR_<mode> is transferred to CPSR", .{});
-                    } else {
-                        if (i == 0xF) {
-                            if (!S) {
-                                // TODO: Assure that this is Address of STM instruction + 12
-                                bus.write32(address, cpu.r[i] + (12 - 4));
-                            } else {
-                                std.debug.panic("[CPU] TODO: STM with S set and R15 in transfer list", .{});
-                            }
-                        } else {
-                            bus.write32(address, cpu.r[i]);
-                        }
-                    }
-
-                    address += 4;
-                }
-            }
-
-            if (W and P or !P) cpu.r[rn] = if (U) address - 4 else base;
-        }
-    }.inner;
-}

src/cpu/branch.zig

@@ -8,8 +8,7 @@ pub fn branch(comptime L: bool) InstrFn {
     return struct {
         fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u32) void {
             if (L) {
-                // TODO: Debugging beeg.gba w/ MGBA seems to suggest that I don't do anything here
+                cpu.r[14] = cpu.r[15] - 4;
-                cpu.r[14] = cpu.r[15];
             }
 
             cpu.r[15] = cpu.fakePC() +% util.u32SignExtend(24, opcode << 2);

src/ppu.zig

@@ -44,29 +44,12 @@ pub const Ppu = struct {
 
         switch (bg_mode) {
             0x3 => {
+                // Mode 3
                 const start = buf_pitch * @as(usize, scanline);
                 const end = start + buf_pitch;
 
                 std.mem.copy(u8, self.frame_buf[start..end], self.vram.buf[start..end]);
             },
-            0x4 => {
-                const frame_select = io.dispcnt.frame_select.read();
-
-                const fb_start = buf_pitch * @as(usize, scanline);
-                const vram_start = width * @as(usize, scanline);
-
-                const start = if (frame_select) 0xA000 + vram_start else vram_start;
-                const end = start + width;
-
-                for (self.vram.buf[start..end]) |byte, i| {
-                    const fb_i = i * @sizeOf(u16);
-                    const colour = self.palette.buf[byte];
-                    var bgr555: u16 = colour & 0x3 | (colour & 0x1C >> 2) << 5 | @as(u16, colour >> 5) << 10;
-
-                    self.frame_buf[fb_start + fb_i + 1] = @truncate(u8, bgr555 >> 8);
-                    self.frame_buf[fb_start + fb_i] = @truncate(u8, bgr555);
-                }
-            },
             else => std.debug.panic("[PPU] TODO: Implement BG Mode {}", .{bg_mode}),
         }
     }

src/scheduler.zig

@@ -44,6 +44,7 @@ pub const Scheduler = struct {
                     bus.ppu.drawScanline(&bus.io);
 
                     bus.io.vcount.scanline.write(new_scanline);
+                    bus.io.dispstat.hblank.unset();
 
                     if (new_scanline < 160) {
                         // Transitioning to another Draw
@@ -68,8 +69,6 @@ pub const Scheduler = struct {
                     const new_scanline = scanline + 1;
                     bus.io.vcount.scanline.write(new_scanline);
 
-                    if (new_scanline == 227) bus.io.dispstat.vblank.unset();
-
                     if (new_scanline < 228) {
                         // Transition to another Vblank
                         self.push(.VBlank, self.tick + (308 * 4));
@@ -77,7 +76,7 @@ pub const Scheduler = struct {
                         // Transition to another Draw
                         bus.io.vcount.scanline.write(0); // Reset Scanline
 
-                        // DISPSTAT was disabled on scanline 227
+                        bus.io.dispstat.vblank.unset();
                         self.push(.Draw, self.tick + (240 * 4));
                     }
                 },