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76789aa8bc
...
37a360ec07
163
src/Bus.zig
163
src/Bus.zig
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@ -54,81 +54,136 @@ pub fn deinit(self: Self) void {
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self.ppu.deinit();
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}
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pub fn read(self: *const Self, comptime T: type, address: u32) T {
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const page = @truncate(u8, address >> 24);
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const align_addr = alignAddress(T, address);
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pub fn read32(self: *const Self, address: u32) u32 {
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const align_addr = address & 0xFFFF_FFFC; // Force Aligned
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return switch (page) {
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return switch (address) {
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// General Internal Memory
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0x00 => self.bios.read(T, align_addr),
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0x02 => self.ewram.read(T, align_addr),
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0x03 => self.iwram.read(T, align_addr),
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0x04 => io.read(self, T, align_addr),
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0x0000_0000...0x0000_3FFF => self.bios.read(u32, align_addr),
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0x0200_0000...0x02FF_FFFF => self.ewram.read(u32, align_addr),
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0x0300_0000...0x03FF_FFFF => self.iwram.read(u32, align_addr),
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0x0400_0000...0x0400_03FE => io.read32(self, align_addr),
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// Internal Display Memory
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0x05 => self.ppu.palette.read(T, align_addr),
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0x06 => self.ppu.vram.read(T, align_addr),
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0x07 => self.ppu.oam.read(T, align_addr),
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0x0500_0000...0x05FF_FFFF => self.ppu.palette.read(u32, align_addr),
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0x0600_0000...0x06FF_FFFF => self.ppu.vram.read(u32, align_addr),
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0x0700_0000...0x07FF_FFFF => self.ppu.oam.read(u32, align_addr),
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// External Memory (Game Pak)
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0x08...0x0D => self.pak.read(T, align_addr),
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0x0E...0x0F => blk: {
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const value = self.pak.backup.read(address);
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0x0800_0000...0x09FF_FFFF => self.pak.read(u32, align_addr),
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0x0A00_0000...0x0BFF_FFFF => self.pak.read(u32, align_addr),
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0x0C00_0000...0x0DFF_FFFF => self.pak.read(u32, align_addr),
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0x0E00_0000...0x0FFF_FFFF => @as(u32, self.pak.backup.read(address)) * 0x01010101,
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const multiplier = switch (T) {
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u32 => 0x01010101,
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u16 => 0x0101,
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u8 => 1,
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else => @compileError("Backup: Unsupported read width"),
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};
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break :blk @as(T, value) * multiplier;
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},
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else => undRead("Tried to read {} from 0x{X:0>8}", .{ T, address }),
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else => undRead("Tried to read from 0x{X:0>8}", .{address}),
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};
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}
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pub fn write(self: *Self, comptime T: type, address: u32, value: T) void {
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const page = @truncate(u8, address >> 24);
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const align_addr = alignAddress(T, address);
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pub fn write32(self: *Self, address: u32, word: u32) void {
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const align_addr = address & 0xFFFF_FFFC; // Force Aligned
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switch (page) {
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switch (address) {
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// General Internal Memory
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0x00 => self.bios.write(T, align_addr, value),
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0x02 => self.ewram.write(T, align_addr, value),
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0x03 => self.iwram.write(T, align_addr, value),
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0x04 => io.write(self, T, align_addr, value),
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0x0200_0000...0x02FF_FFFF => self.ewram.write(u32, align_addr, word),
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0x0300_0000...0x03FF_FFFF => self.iwram.write(u32, align_addr, word),
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0x0400_0000...0x0400_03FE => io.write32(self, align_addr, word),
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// Internal Display Memory
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0x05 => self.ppu.palette.write(T, align_addr, value),
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0x06 => self.ppu.vram.write(T, align_addr, value),
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0x07 => self.ppu.oam.write(T, align_addr, value),
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0x0500_0000...0x05FF_FFFF => self.ppu.palette.write(u32, align_addr, word),
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0x0600_0000...0x06FF_FFFF => self.ppu.vram.write(u32, align_addr, word),
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0x0700_0000...0x07FF_FFFF => self.ppu.oam.write(u32, align_addr, word),
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0x0E00_0000...0x0FFF_FFFF => self.pak.backup.write(address, @truncate(u8, rotr(u32, word, 8 * (address & 3)))),
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// External Memory (Game Pak)
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0x08...0x0D => {},
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0x0E...0x0F => {
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const rotate_by = switch (T) {
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u32 => address & 3,
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u16 => address & 1,
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u8 => 0,
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else => @compileError("Backup: Unsupported write width"),
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};
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self.pak.backup.write(address, @truncate(u8, rotr(T, value, 8 * rotate_by)));
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},
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else => undWrite("Tried to write {} 0x{X:} to 0x{X:0>8}", .{ T, value, address }),
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else => undWrite("Tried to write 0x{X:0>8} to 0x{X:0>8}", .{ word, address }),
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}
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}
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fn alignAddress(comptime T: type, address: u32) u32 {
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return switch (T) {
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u32 => address & 0xFFFF_FFFC,
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u16 => address & 0xFFFF_FFFE,
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u8 => address,
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else => @compileError("Bus: Invalid read/write type"),
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pub fn read16(self: *const Self, address: u32) u16 {
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const align_addr = address & 0xFFFF_FFFE; // Force Aligned
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return switch (address) {
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// General Internal Memory
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0x0000_0000...0x0000_3FFF => self.bios.read(u16, align_addr),
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0x0200_0000...0x02FF_FFFF => self.ewram.read(u16, align_addr),
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0x0300_0000...0x03FF_FFFF => self.iwram.read(u16, align_addr),
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0x0400_0000...0x0400_03FE => io.read16(self, align_addr),
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// Internal Display Memory
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0x0500_0000...0x05FF_FFFF => self.ppu.palette.read(u16, align_addr),
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0x0600_0000...0x06FF_FFFF => self.ppu.vram.read(u16, align_addr),
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0x0700_0000...0x07FF_FFFF => self.ppu.oam.read(u16, align_addr),
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// External Memory (Game Pak)
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0x0800_0000...0x09FF_FFFF => self.pak.read(u16, align_addr),
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0x0A00_0000...0x0BFF_FFFF => self.pak.read(u16, align_addr),
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0x0C00_0000...0x0DFF_FFFF => self.pak.read(u16, align_addr),
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0x0E00_0000...0x0FFF_FFFF => @as(u16, self.pak.backup.read(address)) * 0x0101,
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else => undRead("Tried to read from 0x{X:0>8}", .{address}),
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};
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}
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pub fn write16(self: *Self, address: u32, halfword: u16) void {
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const align_addr = address & 0xFFFF_FFFE;
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switch (address) {
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// General Internal Memory
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0x0200_0000...0x02FF_FFFF => self.ewram.write(u16, align_addr, halfword),
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0x0300_0000...0x03FF_FFFF => self.iwram.write(u16, align_addr, halfword),
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0x0400_0000...0x0400_03FE => io.write16(self, align_addr, halfword),
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// Internal Display Memory
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0x0500_0000...0x05FF_FFFF => self.ppu.palette.write(u16, align_addr, halfword),
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0x0600_0000...0x06FF_FFFF => self.ppu.vram.write(u16, align_addr, halfword),
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0x0700_0000...0x07FF_FFFF => self.ppu.oam.write(u16, align_addr, halfword),
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0x0800_00C4, 0x0800_00C6, 0x0800_00C8 => log.warn("Tried to write 0x{X:0>4} to GPIO", .{halfword}),
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// External Memory (Game Pak)
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0x0E00_0000...0x0FFF_FFFF => {
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self.pak.backup.write(address, @truncate(u8, rotr(u16, halfword, 8 * (address & 1))));
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},
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else => undWrite("Tried to write 0x{X:0>4} to 0x{X:0>8}", .{ halfword, address }),
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}
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}
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pub fn read8(self: *const Self, address: u32) u8 {
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return switch (address) {
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// General Internal Memory
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0x0000_0000...0x0000_3FFF => self.bios.read(u8, address),
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0x0200_0000...0x02FF_FFFF => self.ewram.read(u8, address),
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0x0300_0000...0x03FF_FFFF => self.iwram.read(u8, address),
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0x0400_0000...0x0400_03FE => io.read8(self, address),
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// Internal Display Memory
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0x0500_0000...0x05FF_FFFF => self.ppu.palette.read(u8, address),
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0x0600_0000...0x06FF_FFFF => self.ppu.vram.read(u8, address),
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0x0700_0000...0x07FF_FFFF => self.ppu.oam.read(u8, address),
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// External Memory (Game Pak)
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0x0800_0000...0x09FF_FFFF => self.pak.read(u8, address),
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0x0A00_0000...0x0BFF_FFFF => self.pak.read(u8, address),
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0x0C00_0000...0x0DFF_FFFF => self.pak.read(u8, address),
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0x0E00_0000...0x0FFF_FFFF => self.pak.backup.read(address),
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else => undRead("Tried to read from 0x{X:0>2}", .{address}),
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};
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}
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pub fn write8(self: *Self, address: u32, byte: u8) void {
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switch (address) {
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// General Internal Memory
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0x0200_0000...0x02FF_FFFF => self.ewram.write(u8, address, byte),
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0x0300_0000...0x03FF_FFFF => self.iwram.write(u8, address, byte),
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0x0400_0000...0x0400_03FE => io.write8(self, address, byte),
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0x0400_0410 => log.info("Ignored write of 0x{X:0>2} to 0x{X:0>8}", .{ byte, address }),
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// External Memory (Game Pak)
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0x0E00_0000...0x0FFF_FFFF => self.pak.backup.write(address, byte),
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else => undWrite("Tried to write 0x{X:0>2} to 0x{X:0>8}", .{ byte, address }),
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}
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}
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fn undRead(comptime format: []const u8, args: anytype) u8 {
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if (panic_on_und_bus) std.debug.panic(format, args) else log.warn(format, args);
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return 0;
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@ -1,7 +1,6 @@
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const std = @import("std");
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const Allocator = std.mem.Allocator;
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const log = std.log.scoped(.Bios);
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const Self = @This();
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buf: ?[]u8,
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@ -39,8 +38,3 @@ pub fn read(self: *const Self, comptime T: type, addr: usize) T {
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std.debug.panic("[BIOS] ZBA tried to read {} from 0x{X:0>8} but not BIOS was present", .{ T, addr });
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}
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pub fn write(_: *Self, comptime T: type, addr: usize, value: T) void {
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@setCold(true);
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log.err("Tried to write {} 0x{X:} to 0x{X:0>8} ", .{ T, value, addr });
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}
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@ -123,12 +123,12 @@ fn DmaController(comptime id: u2) type {
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var offset: u32 = 0;
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if (self.cnt.transfer_type.read()) {
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offset = @sizeOf(u32); // 32-bit Transfer
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const word = bus.read(u32, self._sad);
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bus.write(u32, self._dad, word);
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const word = bus.read32(self._sad);
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bus.write32(self._dad, word);
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} else {
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offset = @sizeOf(u16); // 16-bit Transfer
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const halfword = bus.read(u16, self._sad);
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bus.write(u16, self._dad, halfword);
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const halfword = bus.read16(self._sad);
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bus.write16(self._dad, halfword);
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}
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switch (sad_adj) {
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388
src/bus/io.zig
388
src/bus/io.zig
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@ -38,32 +38,84 @@ pub const Io = struct {
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}
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};
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pub fn read(bus: *const Bus, comptime T: type, address: u32) T {
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return switch (T) {
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u32 => switch (address) {
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pub fn read32(bus: *const Bus, addr: u32) u32 {
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return switch (addr) {
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// Display
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0x0400_0000 => bus.ppu.dispcnt.raw,
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0x0400_0004 => @as(T, bus.ppu.vcount.raw) << 16 | bus.ppu.dispstat.raw,
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0x0400_0006 => @as(T, bus.ppu.bg[0].cnt.raw) << 16 | bus.ppu.vcount.raw,
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0x0400_0004 => @as(u32, bus.ppu.vcount.raw) << 16 | bus.ppu.dispstat.raw,
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0x0400_0006 => @as(u32, bus.ppu.bg[0].cnt.raw) << 16 | bus.ppu.vcount.raw,
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// DMA Transfers
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0x0400_00B8 => @as(T, bus.dma._0.cnt.raw) << 16,
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0x0400_00C4 => @as(T, bus.dma._1.cnt.raw) << 16,
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0x0400_00D0 => @as(T, bus.dma._1.cnt.raw) << 16,
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0x0400_00DC => @as(T, bus.dma._3.cnt.raw) << 16,
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0x0400_00B8 => @as(u32, bus.dma._0.cnt.raw) << 16,
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0x0400_00C4 => @as(u32, bus.dma._1.cnt.raw) << 16,
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0x0400_00D0 => @as(u32, bus.dma._1.cnt.raw) << 16,
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0x0400_00DC => @as(u32, bus.dma._3.cnt.raw) << 16,
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// Timers
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0x0400_0100 => @as(T, bus.tim._0.cnt.raw) << 16 | bus.tim._0.counter(),
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0x0400_0104 => @as(T, bus.tim._1.cnt.raw) << 16 | bus.tim._1.counter(),
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0x0400_0108 => @as(T, bus.tim._2.cnt.raw) << 16 | bus.tim._2.counter(),
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0x0400_010C => @as(T, bus.tim._3.cnt.raw) << 16 | bus.tim._3.counter(),
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0x0400_0100 => @as(u32, bus.tim._0.cnt.raw) << 16 | bus.tim._0.counter(),
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0x0400_0104 => @as(u32, bus.tim._1.cnt.raw) << 16 | bus.tim._1.counter(),
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0x0400_0108 => @as(u32, bus.tim._2.cnt.raw) << 16 | bus.tim._2.counter(),
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0x0400_010C => @as(u32, bus.tim._3.cnt.raw) << 16 | bus.tim._3.counter(),
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// Interrupts
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0x0400_0200 => @as(T, bus.io.irq.raw) << 16 | bus.io.ie.raw,
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0x0400_0200 => @as(u32, bus.io.irq.raw) << 16 | bus.io.ie.raw,
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0x0400_0208 => @boolToInt(bus.io.ime),
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else => undRead("Tried to read {} from 0x{X:0>8}", .{ T, address }),
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else => undRead("Tried to read word from 0x{X:0>8}", .{addr}),
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};
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}
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pub fn write32(bus: *Bus, addr: u32, word: u32) void {
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switch (addr) {
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// Display
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0x0400_0000 => bus.ppu.dispcnt.raw = @truncate(u16, word),
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0x0400_0004 => {
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bus.ppu.dispstat.raw = @truncate(u16, word);
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bus.ppu.vcount.raw = @truncate(u16, word >> 16);
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},
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u16 => switch (address) {
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0x0400_0008 => bus.ppu.setAdjCnts(0, word),
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0x0400_000C => bus.ppu.setAdjCnts(2, word),
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0x0400_0010 => bus.ppu.setBgOffsets(0, word),
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0x0400_0014 => bus.ppu.setBgOffsets(1, word),
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0x0400_0018 => bus.ppu.setBgOffsets(2, word),
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0x0400_001C => bus.ppu.setBgOffsets(3, word),
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// Sound
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0x0400_00A0 => log.warn("Wrote 0x{X:0>8} to FIFO_A", .{word}),
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0x0400_00A4 => log.warn("Wrote 0x{X:0>8} to FIFO_B", .{word}),
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// DMA Transfers
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0x0400_00B0 => bus.dma._0.writeSad(word),
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0x0400_00B4 => bus.dma._0.writeDad(word),
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0x0400_00B8 => bus.dma._0.writeCnt(word),
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0x0400_00BC => bus.dma._1.writeSad(word),
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0x0400_00C0 => bus.dma._1.writeDad(word),
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0x0400_00C4 => bus.dma._1.writeCnt(word),
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0x0400_00C8 => bus.dma._2.writeSad(word),
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0x0400_00CC => bus.dma._2.writeDad(word),
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0x0400_00D0 => bus.dma._2.writeCnt(word),
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0x0400_00D4 => bus.dma._3.writeSad(word),
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0x0400_00D8 => bus.dma._3.writeDad(word),
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0x0400_00DC => bus.dma._3.writeCnt(word),
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// Timers
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0x0400_0100 => bus.tim._0.writeCnt(word),
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0x0400_0104 => bus.tim._1.writeCnt(word),
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0x0400_0108 => bus.tim._2.writeCnt(word),
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0x0400_010C => bus.tim._3.writeCnt(word),
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// Serial Communication 1
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0x0400_0120 => log.warn("Wrote 0x{X:0>8} to SIODATA32", .{word}),
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// Interrupts
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0x0400_0200 => bus.io.setIrqs(word),
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0x0400_0204 => log.warn("Wrote 0x{X:0>8} to WAITCNT", .{word}),
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0x0400_0208 => bus.io.ime = word & 1 == 1,
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else => undWrite("Tried to write 0x{X:0>8} to 0x{X:0>8}", .{ word, addr }),
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}
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}
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pub fn read16(bus: *const Bus, addr: u32) u16 {
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return switch (addr) {
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// Display
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||||
0x0400_0000 => bus.ppu.dispcnt.raw,
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0x0400_0004 => bus.ppu.dispstat.raw,
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@ -96,13 +148,100 @@ pub fn read(bus: *const Bus, comptime T: type, address: u32) T {
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0x0400_0202 => bus.io.irq.raw,
|
||||
0x0400_0204 => unimplementedRead("Read halfword from WAITCNT", .{}),
|
||||
0x0400_0208 => @boolToInt(bus.io.ime),
|
||||
else => undRead("Tried to read halfword from 0x{X:0>8}", .{address}),
|
||||
},
|
||||
u8 => return switch (address) {
|
||||
else => undRead("Tried to read halfword from 0x{X:0>8}", .{addr}),
|
||||
};
|
||||
}
|
||||
|
||||
pub fn write16(bus: *Bus, addr: u32, halfword: u16) void {
|
||||
switch (addr) {
|
||||
// Display
|
||||
0x0400_0000 => @truncate(T, bus.ppu.dispcnt.raw),
|
||||
0x0400_0004 => @truncate(T, bus.ppu.dispstat.raw),
|
||||
0x0400_0006 => @truncate(T, bus.ppu.vcount.raw),
|
||||
0x0400_0000 => bus.ppu.dispcnt.raw = halfword,
|
||||
0x0400_0004 => bus.ppu.dispstat.raw = halfword,
|
||||
0x0400_0008 => bus.ppu.bg[0].cnt.raw = halfword,
|
||||
0x0400_000A => bus.ppu.bg[1].cnt.raw = halfword,
|
||||
0x0400_000C => bus.ppu.bg[2].cnt.raw = halfword,
|
||||
0x0400_000E => bus.ppu.bg[3].cnt.raw = halfword,
|
||||
0x0400_0010 => bus.ppu.bg[0].hofs.raw = halfword, // TODO: Don't write out every HOFS / VOFS?
|
||||
0x0400_0012 => bus.ppu.bg[0].vofs.raw = halfword,
|
||||
0x0400_0014 => bus.ppu.bg[1].hofs.raw = halfword,
|
||||
0x0400_0016 => bus.ppu.bg[1].vofs.raw = halfword,
|
||||
0x0400_0018 => bus.ppu.bg[2].hofs.raw = halfword,
|
||||
0x0400_001A => bus.ppu.bg[2].vofs.raw = halfword,
|
||||
0x0400_001C => bus.ppu.bg[3].hofs.raw = halfword,
|
||||
0x0400_001E => bus.ppu.bg[3].vofs.raw = halfword,
|
||||
0x0400_0020 => log.warn("Wrote 0x{X:0>4} to BG2PA", .{halfword}),
|
||||
0x0400_0026 => log.warn("Wrote 0x{X:0>4} to BG2PD", .{halfword}),
|
||||
0x0400_0030 => log.warn("Wrote 0x{X:0>4} to BG3PA", .{halfword}),
|
||||
0x0400_0036 => log.warn("Wrote 0x{X:0>4} to BG3PD", .{halfword}),
|
||||
0x0400_0040 => log.warn("Wrote 0x{X:0>4} to WIN0H", .{halfword}),
|
||||
0x0400_0042 => log.warn("Wrote 0x{X:0>4} to WIN1H", .{halfword}),
|
||||
0x0400_0044 => log.warn("Wrote 0x{X:0>4} to WIN0V", .{halfword}),
|
||||
0x0400_0046 => log.warn("Wrote 0x{X:0>4} to WIN1V", .{halfword}),
|
||||
0x0400_0048 => log.warn("Wrote 0x{X:0>4} to WININ", .{halfword}),
|
||||
0x0400_004A => log.warn("Wrote 0x{X:0>4} to WINOUT", .{halfword}),
|
||||
0x0400_004C => log.warn("Wrote 0x{X:0>4} to MOSAIC", .{halfword}),
|
||||
0x0400_0050 => log.warn("Wrote 0x{X:0>4} to BLDCNT", .{halfword}),
|
||||
0x0400_0052 => log.warn("Wrote 0x{X:0>4} to BLDALPHA", .{halfword}),
|
||||
0x0400_0054 => log.warn("Wrote 0x{X:0>4} to BLDY", .{halfword}),
|
||||
|
||||
// Sound
|
||||
0x0400_0080 => bus.apu.ch_vol_cnt.raw = halfword,
|
||||
0x0400_0082 => bus.apu.dma_cnt.raw = halfword,
|
||||
0x0400_0084 => bus.apu.setSoundCntX(halfword >> 7 & 1 == 1),
|
||||
0x0400_0088 => bus.apu.bias.raw = halfword,
|
||||
|
||||
// Dma Transfers
|
||||
0x0400_00B8 => bus.dma._0.writeWordCount(halfword),
|
||||
0x0400_00BA => bus.dma._0.writeCntHigh(halfword),
|
||||
0x0400_00C4 => bus.dma._1.writeWordCount(halfword),
|
||||
0x0400_00C6 => bus.dma._1.writeCntHigh(halfword),
|
||||
0x0400_00D0 => bus.dma._2.writeWordCount(halfword),
|
||||
0x0400_00D2 => bus.dma._2.writeCntHigh(halfword),
|
||||
0x0400_00DC => bus.dma._3.writeWordCount(halfword),
|
||||
0x0400_00DE => bus.dma._3.writeCntHigh(halfword),
|
||||
|
||||
// Timers
|
||||
0x0400_0100 => bus.tim._0.writeCntLow(halfword),
|
||||
0x0400_0102 => bus.tim._0.writeCntHigh(halfword),
|
||||
0x0400_0104 => bus.tim._1.writeCntLow(halfword),
|
||||
0x0400_0106 => bus.tim._1.writeCntHigh(halfword),
|
||||
0x0400_0108 => bus.tim._2.writeCntLow(halfword),
|
||||
0x0400_010A => bus.tim._2.writeCntHigh(halfword),
|
||||
0x0400_010C => bus.tim._3.writeCntLow(halfword),
|
||||
0x0400_010E => bus.tim._3.writeCntHigh(halfword),
|
||||
|
||||
// Serial Communication 1
|
||||
0x0400_0120 => log.warn("Wrote 0x{X:0>4} to SIOMULTI0", .{halfword}),
|
||||
0x0400_0122 => log.warn("Wrote 0x{X:0>4} to SIOMULTI1", .{halfword}),
|
||||
0x0400_0124 => log.warn("Wrote 0x{X:0>4} to SIOMULTI2", .{halfword}),
|
||||
0x0400_0126 => log.warn("Wrote 0x{X:0>4} to SIOMULTI3", .{halfword}),
|
||||
0x0400_0128 => log.warn("Wrote 0x{X:0>4} to SIOCNT", .{halfword}),
|
||||
0x0400_012A => log.warn("Wrote 0x{X:0>4} to SIOMLT_SEND", .{halfword}),
|
||||
|
||||
// Keypad Input
|
||||
0x0400_0130 => log.warn("Wrote 0x{X:0>4} to KEYINPUT. Ignored", .{halfword}),
|
||||
0x0400_0132 => log.warn("Wrote 0x{X:0>4} to KEYCNT", .{halfword}),
|
||||
|
||||
// Serial Communication 2
|
||||
0x0400_0134 => log.warn("Wrote 0x{X:0>4} to RCNT", .{halfword}),
|
||||
0x0400_0140 => log.warn("Wrote 0x{X:0>4} to JOYCNT", .{halfword}),
|
||||
0x0400_0158 => log.warn("Wrote 0x{X:0>4} to JOYSTAT", .{halfword}),
|
||||
|
||||
// Interrupts
|
||||
0x0400_0200 => bus.io.ie.raw = halfword,
|
||||
0x0400_0202 => bus.io.irq.raw &= ~halfword,
|
||||
0x0400_0204 => log.warn("Wrote 0x{X:0>4} to WAITCNT", .{halfword}),
|
||||
0x0400_0208 => bus.io.ime = halfword & 1 == 1,
|
||||
else => undWrite("Tried to write 0x{X:0>4} to 0x{X:0>8}", .{ halfword, addr }),
|
||||
}
|
||||
}
|
||||
|
||||
pub fn read8(bus: *const Bus, addr: u32) u8 {
|
||||
return switch (addr) {
|
||||
// Display
|
||||
0x0400_0000 => @truncate(u8, bus.ppu.dispcnt.raw),
|
||||
0x0400_0004 => @truncate(u8, bus.ppu.dispstat.raw),
|
||||
0x0400_0006 => @truncate(u8, bus.ppu.vcount.raw),
|
||||
|
||||
// Sound
|
||||
0x0400_0060 => bus.apu.ch1.sweep.raw,
|
||||
|
|
@ -111,193 +250,60 @@ pub fn read(bus: *const Bus, comptime T: type, address: u32) T {
|
|||
0x0400_0073 => bus.apu.ch3.vol.raw,
|
||||
0x0400_0079 => bus.apu.ch4.envelope.raw,
|
||||
0x0400_007C => bus.apu.ch4.poly.raw,
|
||||
0x0400_0081 => @truncate(T, bus.apu.ch_vol_cnt.raw >> 8),
|
||||
0x0400_0089 => @truncate(T, bus.apu.bias.raw >> 8),
|
||||
0x0400_0081 => @truncate(u8, bus.apu.ch_vol_cnt.raw >> 8),
|
||||
0x0400_0089 => @truncate(u8, bus.apu.bias.raw >> 8),
|
||||
|
||||
// Serial Communication 1
|
||||
0x0400_0128 => unimplementedRead("Read (low) byte from SIOCNT", .{}),
|
||||
|
||||
// Interrupts
|
||||
0x0400_0200 => @truncate(T, bus.io.ie.raw),
|
||||
0x0400_0200 => @truncate(u8, bus.io.ie.raw),
|
||||
0x0400_0300 => @enumToInt(bus.io.postflg),
|
||||
else => undRead("Tried to read byte from 0x{X:0>8}", .{address}),
|
||||
},
|
||||
else => @compileError("I/O: Unsupported read width"),
|
||||
else => undRead("Tried to read byte from 0x{X:0>8}", .{addr}),
|
||||
};
|
||||
}
|
||||
|
||||
pub fn write(bus: *Bus, comptime T: type, address: u32, value: T) void {
|
||||
return switch (T) {
|
||||
u32 => switch (address) {
|
||||
pub fn write8(bus: *Bus, addr: u32, byte: u8) void {
|
||||
switch (addr) {
|
||||
// Display
|
||||
0x0400_0000 => bus.ppu.dispcnt.raw = @truncate(u16, value),
|
||||
0x0400_0004 => {
|
||||
bus.ppu.dispstat.raw = @truncate(u16, value);
|
||||
bus.ppu.vcount.raw = @truncate(u16, value >> 16);
|
||||
},
|
||||
0x0400_0008 => bus.ppu.setAdjCnts(0, value),
|
||||
0x0400_000C => bus.ppu.setAdjCnts(2, value),
|
||||
0x0400_0010 => bus.ppu.setBgOffsets(0, value),
|
||||
0x0400_0014 => bus.ppu.setBgOffsets(1, value),
|
||||
0x0400_0018 => bus.ppu.setBgOffsets(2, value),
|
||||
0x0400_001C => bus.ppu.setBgOffsets(3, value),
|
||||
0x0400_0004 => bus.ppu.dispstat.raw = (bus.ppu.dispstat.raw & 0xFF00) | byte,
|
||||
0x0400_0005 => bus.ppu.dispstat.raw = (@as(u16, byte) << 8) | (bus.ppu.dispstat.raw & 0xFF),
|
||||
|
||||
// Sound
|
||||
0x0400_00A0 => log.warn("Wrote 0x{X:0>8} to FIFO_A", .{value}),
|
||||
0x0400_00A4 => log.warn("Wrote 0x{X:0>8} to FIFO_B", .{value}),
|
||||
|
||||
// DMA Transfers
|
||||
0x0400_00B0 => bus.dma._0.writeSad(value),
|
||||
0x0400_00B4 => bus.dma._0.writeDad(value),
|
||||
0x0400_00B8 => bus.dma._0.writeCnt(value),
|
||||
0x0400_00BC => bus.dma._1.writeSad(value),
|
||||
0x0400_00C0 => bus.dma._1.writeDad(value),
|
||||
0x0400_00C4 => bus.dma._1.writeCnt(value),
|
||||
0x0400_00C8 => bus.dma._2.writeSad(value),
|
||||
0x0400_00CC => bus.dma._2.writeDad(value),
|
||||
0x0400_00D0 => bus.dma._2.writeCnt(value),
|
||||
0x0400_00D4 => bus.dma._3.writeSad(value),
|
||||
0x0400_00D8 => bus.dma._3.writeDad(value),
|
||||
0x0400_00DC => bus.dma._3.writeCnt(value),
|
||||
|
||||
// Timers
|
||||
0x0400_0100 => bus.tim._0.writeCnt(value),
|
||||
0x0400_0104 => bus.tim._1.writeCnt(value),
|
||||
0x0400_0108 => bus.tim._2.writeCnt(value),
|
||||
0x0400_010C => bus.tim._3.writeCnt(value),
|
||||
0x0400_0060 => bus.apu.ch1.sweep.raw = byte,
|
||||
0x0400_0062 => bus.apu.ch1.duty.raw = byte,
|
||||
0x0400_0063 => bus.apu.ch1.envelope.raw = byte,
|
||||
0x0400_0064 => bus.apu.ch1.setFreqLow(byte),
|
||||
0x0400_0065 => bus.apu.ch1.setFreqHigh(byte),
|
||||
0x0400_0068 => bus.apu.ch2.duty.raw = byte,
|
||||
0x0400_0069 => bus.apu.ch2.envelope.raw = byte,
|
||||
0x0400_006C => bus.apu.ch2.setFreqLow(byte),
|
||||
0x0400_006D => bus.apu.ch2.setFreqHigh(byte),
|
||||
0x0400_0070 => bus.apu.ch3.select.raw = byte,
|
||||
0x0400_0072 => bus.apu.ch3.length = byte,
|
||||
0x0400_0073 => bus.apu.ch3.vol.raw = byte,
|
||||
0x0400_0074 => bus.apu.ch3.setFreqLow(byte),
|
||||
0x0400_0075 => bus.apu.ch3.setFreqHigh(byte),
|
||||
0x0400_0078 => bus.apu.ch4.len = @truncate(u6, byte),
|
||||
0x0400_0079 => bus.apu.ch4.envelope.raw = byte,
|
||||
0x0400_007C => bus.apu.ch4.poly.raw = byte,
|
||||
0x0400_007D => bus.apu.ch4.cnt.raw = byte,
|
||||
0x0400_0080 => bus.apu.setSoundCntLLow(byte),
|
||||
0x0400_0081 => bus.apu.setSoundCntLHigh(byte),
|
||||
0x0400_0084 => bus.apu.setSoundCntX(byte >> 7 & 1 == 1),
|
||||
0x0400_0089 => bus.apu.setBiasHigh(byte),
|
||||
|
||||
// Serial Communication 1
|
||||
0x0400_0120 => log.warn("Wrote 0x{X:0>8} to SIODATA32", .{value}),
|
||||
|
||||
// Interrupts
|
||||
0x0400_0200 => bus.io.setIrqs(value),
|
||||
0x0400_0204 => log.warn("Wrote 0x{X:0>8} to WAITCNT", .{value}),
|
||||
0x0400_0208 => bus.io.ime = value & 1 == 1,
|
||||
else => undWrite("Tried to write {} 0x{X:0>8} to 0x{X:0>8}", .{ T, value, address }),
|
||||
},
|
||||
u16 => switch (address) {
|
||||
// Display
|
||||
0x0400_0000 => bus.ppu.dispcnt.raw = value,
|
||||
0x0400_0004 => bus.ppu.dispstat.raw = value,
|
||||
0x0400_0008 => bus.ppu.bg[0].cnt.raw = value,
|
||||
0x0400_000A => bus.ppu.bg[1].cnt.raw = value,
|
||||
0x0400_000C => bus.ppu.bg[2].cnt.raw = value,
|
||||
0x0400_000E => bus.ppu.bg[3].cnt.raw = value,
|
||||
0x0400_0010 => bus.ppu.bg[0].hofs.raw = value, // TODO: Don't write out every HOFS / VOFS?
|
||||
0x0400_0012 => bus.ppu.bg[0].vofs.raw = value,
|
||||
0x0400_0014 => bus.ppu.bg[1].hofs.raw = value,
|
||||
0x0400_0016 => bus.ppu.bg[1].vofs.raw = value,
|
||||
0x0400_0018 => bus.ppu.bg[2].hofs.raw = value,
|
||||
0x0400_001A => bus.ppu.bg[2].vofs.raw = value,
|
||||
0x0400_001C => bus.ppu.bg[3].hofs.raw = value,
|
||||
0x0400_001E => bus.ppu.bg[3].vofs.raw = value,
|
||||
0x0400_0020 => log.warn("Wrote 0x{X:0>4} to BG2PA", .{value}),
|
||||
0x0400_0026 => log.warn("Wrote 0x{X:0>4} to BG2PD", .{value}),
|
||||
0x0400_0030 => log.warn("Wrote 0x{X:0>4} to BG3PA", .{value}),
|
||||
0x0400_0036 => log.warn("Wrote 0x{X:0>4} to BG3PD", .{value}),
|
||||
0x0400_0040 => log.warn("Wrote 0x{X:0>4} to WIN0H", .{value}),
|
||||
0x0400_0042 => log.warn("Wrote 0x{X:0>4} to WIN1H", .{value}),
|
||||
0x0400_0044 => log.warn("Wrote 0x{X:0>4} to WIN0V", .{value}),
|
||||
0x0400_0046 => log.warn("Wrote 0x{X:0>4} to WIN1V", .{value}),
|
||||
0x0400_0048 => log.warn("Wrote 0x{X:0>4} to WININ", .{value}),
|
||||
0x0400_004A => log.warn("Wrote 0x{X:0>4} to WINOUT", .{value}),
|
||||
0x0400_004C => log.warn("Wrote 0x{X:0>4} to MOSAIC", .{value}),
|
||||
0x0400_0050 => log.warn("Wrote 0x{X:0>4} to BLDCNT", .{value}),
|
||||
0x0400_0052 => log.warn("Wrote 0x{X:0>4} to BLDALPHA", .{value}),
|
||||
0x0400_0054 => log.warn("Wrote 0x{X:0>4} to BLDY", .{value}),
|
||||
|
||||
// Sound
|
||||
0x0400_0080 => bus.apu.ch_vol_cnt.raw = value,
|
||||
0x0400_0082 => bus.apu.dma_cnt.raw = value,
|
||||
0x0400_0084 => bus.apu.setSoundCntX(value >> 7 & 1 == 1),
|
||||
0x0400_0088 => bus.apu.bias.raw = value,
|
||||
|
||||
// Dma Transfers
|
||||
0x0400_00B8 => bus.dma._0.writeWordCount(value),
|
||||
0x0400_00BA => bus.dma._0.writeCntHigh(value),
|
||||
0x0400_00C4 => bus.dma._1.writeWordCount(value),
|
||||
0x0400_00C6 => bus.dma._1.writeCntHigh(value),
|
||||
0x0400_00D0 => bus.dma._2.writeWordCount(value),
|
||||
0x0400_00D2 => bus.dma._2.writeCntHigh(value),
|
||||
0x0400_00DC => bus.dma._3.writeWordCount(value),
|
||||
0x0400_00DE => bus.dma._3.writeCntHigh(value),
|
||||
|
||||
// Timers
|
||||
0x0400_0100 => bus.tim._0.writeCntLow(value),
|
||||
0x0400_0102 => bus.tim._0.writeCntHigh(value),
|
||||
0x0400_0104 => bus.tim._1.writeCntLow(value),
|
||||
0x0400_0106 => bus.tim._1.writeCntHigh(value),
|
||||
0x0400_0108 => bus.tim._2.writeCntLow(value),
|
||||
0x0400_010A => bus.tim._2.writeCntHigh(value),
|
||||
0x0400_010C => bus.tim._3.writeCntLow(value),
|
||||
0x0400_010E => bus.tim._3.writeCntHigh(value),
|
||||
|
||||
// Serial Communication 1
|
||||
0x0400_0120 => log.warn("Wrote 0x{X:0>4} to SIOMULTI0", .{value}),
|
||||
0x0400_0122 => log.warn("Wrote 0x{X:0>4} to SIOMULTI1", .{value}),
|
||||
0x0400_0124 => log.warn("Wrote 0x{X:0>4} to SIOMULTI2", .{value}),
|
||||
0x0400_0126 => log.warn("Wrote 0x{X:0>4} to SIOMULTI3", .{value}),
|
||||
0x0400_0128 => log.warn("Wrote 0x{X:0>4} to SIOCNT", .{value}),
|
||||
0x0400_012A => log.warn("Wrote 0x{X:0>4} to SIOMLT_SEND", .{value}),
|
||||
|
||||
// Keypad Input
|
||||
0x0400_0130 => log.warn("Wrote 0x{X:0>4} to KEYINPUT. Ignored", .{value}),
|
||||
0x0400_0132 => log.warn("Wrote 0x{X:0>4} to KEYCNT", .{value}),
|
||||
0x0400_0128 => log.warn("Wrote 0x{X:0>2} to SIOCNT (low)", .{byte}),
|
||||
|
||||
// Serial Communication 2
|
||||
0x0400_0134 => log.warn("Wrote 0x{X:0>4} to RCNT", .{value}),
|
||||
0x0400_0140 => log.warn("Wrote 0x{X:0>4} to JOYCNT", .{value}),
|
||||
0x0400_0158 => log.warn("Wrote 0x{X:0>4} to JOYSTAT", .{value}),
|
||||
0x0400_0140 => log.warn("Wrote 0x{X:0>2} to JOYCNT (low)", .{byte}),
|
||||
|
||||
// Interrupts
|
||||
0x0400_0200 => bus.io.ie.raw = value,
|
||||
0x0400_0202 => bus.io.irq.raw &= ~value,
|
||||
0x0400_0204 => log.warn("Wrote 0x{X:0>4} to WAITCNT", .{value}),
|
||||
0x0400_0208 => bus.io.ime = value & 1 == 1,
|
||||
else => undWrite("Tried to write 0x{X:0>4} to 0x{X:0>8}", .{ value, address }),
|
||||
},
|
||||
u8 => switch (address) {
|
||||
// Display
|
||||
0x0400_0004 => bus.ppu.dispstat.raw = (bus.ppu.dispstat.raw & 0xFF00) | value,
|
||||
0x0400_0005 => bus.ppu.dispstat.raw = (@as(u16, value) << 8) | (bus.ppu.dispstat.raw & 0xFF),
|
||||
|
||||
// Sound
|
||||
0x0400_0060 => bus.apu.ch1.sweep.raw = value,
|
||||
0x0400_0062 => bus.apu.ch1.duty.raw = value,
|
||||
0x0400_0063 => bus.apu.ch1.envelope.raw = value,
|
||||
0x0400_0064 => bus.apu.ch1.setFreqLow(value),
|
||||
0x0400_0065 => bus.apu.ch1.setFreqHigh(value),
|
||||
0x0400_0068 => bus.apu.ch2.duty.raw = value,
|
||||
0x0400_0069 => bus.apu.ch2.envelope.raw = value,
|
||||
0x0400_006C => bus.apu.ch2.setFreqLow(value),
|
||||
0x0400_006D => bus.apu.ch2.setFreqHigh(value),
|
||||
0x0400_0070 => bus.apu.ch3.select.raw = value,
|
||||
0x0400_0072 => bus.apu.ch3.length = value,
|
||||
0x0400_0073 => bus.apu.ch3.vol.raw = value,
|
||||
0x0400_0074 => bus.apu.ch3.setFreqLow(value),
|
||||
0x0400_0075 => bus.apu.ch3.setFreqHigh(value),
|
||||
0x0400_0078 => bus.apu.ch4.len = @truncate(u6, value),
|
||||
0x0400_0079 => bus.apu.ch4.envelope.raw = value,
|
||||
0x0400_007C => bus.apu.ch4.poly.raw = value,
|
||||
0x0400_007D => bus.apu.ch4.cnt.raw = value,
|
||||
0x0400_0080 => bus.apu.setSoundCntLLow(value),
|
||||
0x0400_0081 => bus.apu.setSoundCntLHigh(value),
|
||||
0x0400_0084 => bus.apu.setSoundCntX(value >> 7 & 1 == 1),
|
||||
0x0400_0089 => bus.apu.setBiasHigh(value),
|
||||
|
||||
// Serial Communication 1
|
||||
0x0400_0128 => log.warn("Wrote 0x{X:0>2} to SIOCNT (low)", .{value}),
|
||||
|
||||
// Serial Communication 2
|
||||
0x0400_0140 => log.warn("Wrote 0x{X:0>2} to JOYCNT (low)", .{value}),
|
||||
|
||||
// Interrupts
|
||||
0x0400_0208 => bus.io.ime = value & 1 == 1,
|
||||
0x0400_0301 => bus.io.haltcnt = if (value >> 7 & 1 == 0) .Halt else std.debug.panic("TODO: Implement STOP", .{}),
|
||||
else => undWrite("Tried to write 0x{X:0>2} to 0x{X:0>8}", .{ value, address }),
|
||||
},
|
||||
else => @compileError("I/O: Unsupported write width"),
|
||||
};
|
||||
0x0400_0208 => bus.io.ime = byte & 1 == 1,
|
||||
0x0400_0301 => bus.io.haltcnt = if (byte >> 7 & 1 == 0) .Halt else std.debug.panic("TODO: Implement STOP", .{}),
|
||||
else => undWrite("Tried to write 0x{X:0>2} to 0x{X:0>8}", .{ byte, addr }),
|
||||
}
|
||||
}
|
||||
|
||||
fn undRead(comptime format: []const u8, args: anytype) u8 {
|
||||
|
|
|
|||
10
src/cpu.zig
10
src/cpu.zig
|
|
@ -306,12 +306,12 @@ pub const Arm7tdmi = struct {
|
|||
|
||||
fn thumbFetch(self: *Self) u16 {
|
||||
defer self.r[15] += 2;
|
||||
return self.bus.read(u16, self.r[15]);
|
||||
return self.bus.read16(self.r[15]);
|
||||
}
|
||||
|
||||
fn fetch(self: *Self) u32 {
|
||||
defer self.r[15] += 4;
|
||||
return self.bus.read(u32, self.r[15]);
|
||||
return self.bus.read32(self.r[15]);
|
||||
}
|
||||
|
||||
pub fn fakePC(self: *const Self) u32 {
|
||||
|
|
@ -341,11 +341,11 @@ pub const Arm7tdmi = struct {
|
|||
prettyPrintPsr(&self.spsr);
|
||||
|
||||
if (self.cpsr.t.read()) {
|
||||
const opcode = self.bus.read(u16, self.r[15] - 4);
|
||||
const opcode = self.bus.read16(self.r[15] - 4);
|
||||
const id = thumbIdx(opcode);
|
||||
std.debug.print("opcode: ID: 0x{b:0>10} 0x{X:0>4}\n", .{ id, opcode });
|
||||
} else {
|
||||
const opcode = self.bus.read(u32, self.r[15] - 4);
|
||||
const opcode = self.bus.read32(self.r[15] - 4);
|
||||
const id = armIdx(opcode);
|
||||
std.debug.print("opcode: ID: 0x{X:0>3} 0x{X:0>8}\n", .{ id, opcode });
|
||||
}
|
||||
|
|
@ -432,7 +432,7 @@ pub const Arm7tdmi = struct {
|
|||
if (self.cpsr.t.read()) {
|
||||
if (opcode >> 11 == 0x1E) {
|
||||
// Instruction 1 of a BL Opcode, print in ARM mode
|
||||
const tmp_opcode = self.bus.read(u32, self.r[15] - 2);
|
||||
const tmp_opcode = self.bus.read32(self.r[15] - 2);
|
||||
const be_opcode = tmp_opcode << 16 | tmp_opcode >> 16;
|
||||
log_str = try std.fmt.bufPrint(&buf, arm_fmt, .{ r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r13, r14, r15, c_psr, be_opcode });
|
||||
} else {
|
||||
|
|
|
|||
|
|
@ -54,9 +54,9 @@ pub fn blockDataTransfer(comptime P: bool, comptime U: bool, comptime S: bool, c
|
|||
}
|
||||
|
||||
if (L) {
|
||||
cpu.r[15] = bus.read(u32, und_addr);
|
||||
cpu.r[15] = bus.read32(und_addr);
|
||||
} else {
|
||||
bus.write(u32, und_addr, cpu.r[15] + 8);
|
||||
bus.write32(und_addr, cpu.r[15] + 8);
|
||||
}
|
||||
|
||||
cpu.r[rn] = if (U) cpu.r[rn] + 0x40 else cpu.r[rn] - 0x40;
|
||||
|
|
@ -83,9 +83,9 @@ pub fn blockDataTransfer(comptime P: bool, comptime U: bool, comptime S: bool, c
|
|||
if (L) {
|
||||
if (S and !r15_present) {
|
||||
// Always Transfer User mode Registers
|
||||
cpu.setUserModeRegister(i, bus.read(u32, address));
|
||||
cpu.setUserModeRegister(i, bus.read32(address));
|
||||
} else {
|
||||
const value = bus.read(u32, address);
|
||||
const value = bus.read32(address);
|
||||
cpu.r[i] = if (i == 0xF) value & 0xFFFF_FFFC else value;
|
||||
if (S and i == 0xF) cpu.setCpsr(cpu.spsr.raw);
|
||||
}
|
||||
|
|
@ -94,9 +94,9 @@ pub fn blockDataTransfer(comptime P: bool, comptime U: bool, comptime S: bool, c
|
|||
// Always Transfer User mode Registers
|
||||
// This happens regardless if r15 is in the list
|
||||
const value = cpu.getUserModeRegister(i);
|
||||
bus.write(u32, address, value + if (i == 0xF) 8 else @as(u32, 0)); // PC is already 4 ahead to make 12
|
||||
bus.write32(address, value + if (i == 0xF) 8 else @as(u32, 0)); // PC is already 4 ahead to make 12
|
||||
} else {
|
||||
bus.write(u32, address, cpu.r[i] + if (i == 0xF) 8 else @as(u32, 0));
|
||||
bus.write32(address, cpu.r[i] + if (i == 0xF) 8 else @as(u32, 0));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -38,19 +38,19 @@ pub fn halfAndSignedDataTransfer(comptime P: bool, comptime U: bool, comptime I:
|
|||
switch (@truncate(u2, opcode >> 5)) {
|
||||
0b01 => {
|
||||
// LDRH
|
||||
const value = bus.read(u16, address);
|
||||
const value = bus.read16(address);
|
||||
result = rotr(u32, value, 8 * (address & 1));
|
||||
},
|
||||
0b10 => {
|
||||
// LDRSB
|
||||
result = sext(8, bus.read(u8, address));
|
||||
result = sext(8, bus.read8(address));
|
||||
},
|
||||
0b11 => {
|
||||
// LDRSH
|
||||
const value = if (address & 1 == 1) blk: {
|
||||
break :blk sext(8, bus.read(u8, address));
|
||||
break :blk sext(8, bus.read8(address));
|
||||
} else blk: {
|
||||
break :blk sext(16, bus.read(u16, address));
|
||||
break :blk sext(16, bus.read16(address));
|
||||
};
|
||||
|
||||
result = rotr(u32, value, 8 * (address & 1));
|
||||
|
|
@ -60,7 +60,7 @@ pub fn halfAndSignedDataTransfer(comptime P: bool, comptime U: bool, comptime I:
|
|||
} else {
|
||||
if (opcode >> 5 & 0x01 == 0x01) {
|
||||
// STRH
|
||||
bus.write(u16, address, @truncate(u16, cpu.r[rd]));
|
||||
bus.write16(address, @truncate(u16, cpu.r[rd]));
|
||||
} else unreachable; // SWP
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -17,13 +17,13 @@ pub fn singleDataSwap(comptime B: bool) InstrFn {
|
|||
|
||||
if (B) {
|
||||
// SWPB
|
||||
const value = bus.read(u8, address);
|
||||
bus.write(u8, address, @truncate(u8, cpu.r[rm]));
|
||||
const value = bus.read8(address);
|
||||
bus.write8(address, @truncate(u8, cpu.r[rm]));
|
||||
cpu.r[rd] = value;
|
||||
} else {
|
||||
// SWP
|
||||
const value = rotr(u32, bus.read(u32, address), 8 * (address & 0x3));
|
||||
bus.write(u32, address, cpu.r[rm]);
|
||||
const value = rotr(u32, bus.read32(address), 8 * (address & 0x3));
|
||||
bus.write32(address, cpu.r[rm]);
|
||||
cpu.r[rd] = value;
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -31,21 +31,21 @@ pub fn singleDataTransfer(comptime I: bool, comptime P: bool, comptime U: bool,
|
|||
if (L) {
|
||||
if (B) {
|
||||
// LDRB
|
||||
result = bus.read(u8, address);
|
||||
result = bus.read8(address);
|
||||
} else {
|
||||
// LDR
|
||||
const value = bus.read(u32, address);
|
||||
const value = bus.read32(address);
|
||||
result = rotr(u32, value, 8 * (address & 0x3));
|
||||
}
|
||||
} else {
|
||||
if (B) {
|
||||
// STRB
|
||||
const value = if (rd == 0xF) cpu.r[rd] + 8 else cpu.r[rd];
|
||||
bus.write(u8, address, @truncate(u8, value));
|
||||
bus.write8(address, @truncate(u8, value));
|
||||
} else {
|
||||
// STR
|
||||
const value = if (rd == 0xF) cpu.r[rd] + 8 else cpu.r[rd];
|
||||
bus.write(u32, address, value);
|
||||
bus.write32(address, value);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -21,9 +21,9 @@ pub fn format14(comptime L: bool, comptime R: bool) InstrFn {
|
|||
while (i < 8) : (i += 1) {
|
||||
if (opcode >> i & 1 == 1) {
|
||||
if (L) {
|
||||
cpu.r[i] = bus.read(u32, address);
|
||||
cpu.r[i] = bus.read32(address);
|
||||
} else {
|
||||
bus.write(u32, address, cpu.r[i]);
|
||||
bus.write32(address, cpu.r[i]);
|
||||
}
|
||||
|
||||
address += 4;
|
||||
|
|
@ -32,10 +32,10 @@ pub fn format14(comptime L: bool, comptime R: bool) InstrFn {
|
|||
|
||||
if (R) {
|
||||
if (L) {
|
||||
const value = bus.read(u32, address);
|
||||
const value = bus.read32(address);
|
||||
cpu.r[15] = value & 0xFFFF_FFFE;
|
||||
} else {
|
||||
bus.write(u32, address, cpu.r[14]);
|
||||
bus.write32(address, cpu.r[14]);
|
||||
}
|
||||
address += 4;
|
||||
}
|
||||
|
|
@ -52,7 +52,7 @@ pub fn format15(comptime L: bool, comptime rb: u3) InstrFn {
|
|||
const end_address = cpu.r[rb] + 4 * countRlist(opcode);
|
||||
|
||||
if (opcode & 0xFF == 0) {
|
||||
if (L) cpu.r[15] = bus.read(u32, address) else bus.write(u32, address, cpu.r[15] + 4);
|
||||
if (L) cpu.r[15] = bus.read32(address) else bus.write32(address, cpu.r[15] + 4);
|
||||
cpu.r[rb] += 0x40;
|
||||
return;
|
||||
}
|
||||
|
|
@ -63,9 +63,9 @@ pub fn format15(comptime L: bool, comptime rb: u3) InstrFn {
|
|||
while (i < 8) : (i += 1) {
|
||||
if (opcode >> i & 1 == 1) {
|
||||
if (L) {
|
||||
cpu.r[i] = bus.read(u32, address);
|
||||
cpu.r[i] = bus.read32(address);
|
||||
} else {
|
||||
bus.write(u32, address, cpu.r[i]);
|
||||
bus.write32(address, cpu.r[i]);
|
||||
}
|
||||
|
||||
if (!L and first_write) {
|
||||
|
|
|
|||
|
|
@ -11,7 +11,7 @@ pub fn format6(comptime rd: u3) InstrFn {
|
|||
fn inner(cpu: *Arm7tdmi, bus: *Bus, opcode: u16) void {
|
||||
// LDR
|
||||
const offset = (opcode & 0xFF) << 2;
|
||||
cpu.r[rd] = bus.read(u32, (cpu.r[15] + 2 & 0xFFFF_FFFD) + offset);
|
||||
cpu.r[rd] = bus.read32((cpu.r[15] + 2 & 0xFFFF_FFFD) + offset);
|
||||
}
|
||||
}.inner;
|
||||
}
|
||||
|
|
@ -32,23 +32,23 @@ pub fn format78(comptime op: u2, comptime T: bool) InstrFn {
|
|||
switch (op) {
|
||||
0b00 => {
|
||||
// STRH
|
||||
bus.write(u16, address, @truncate(u16, cpu.r[rd]));
|
||||
bus.write16(address, @truncate(u16, cpu.r[rd]));
|
||||
},
|
||||
0b01 => {
|
||||
// LDSB
|
||||
cpu.r[rd] = sext(8, bus.read(u8, address));
|
||||
cpu.r[rd] = sext(8, bus.read8(address));
|
||||
},
|
||||
0b10 => {
|
||||
// LDRH
|
||||
const value = bus.read(u16, address);
|
||||
const value = bus.read16(address);
|
||||
cpu.r[rd] = rotr(u32, value, 8 * (address & 1));
|
||||
},
|
||||
0b11 => {
|
||||
// LDRSH
|
||||
const value = if (address & 1 == 1) blk: {
|
||||
break :blk sext(8, bus.read(u8, address));
|
||||
break :blk sext(8, bus.read8(address));
|
||||
} else blk: {
|
||||
break :blk sext(16, bus.read(u16, address));
|
||||
break :blk sext(16, bus.read16(address));
|
||||
};
|
||||
|
||||
cpu.r[rd] = rotr(u32, value, 8 * (address & 1));
|
||||
|
|
@ -59,20 +59,20 @@ pub fn format78(comptime op: u2, comptime T: bool) InstrFn {
|
|||
switch (op) {
|
||||
0b00 => {
|
||||
// STR
|
||||
bus.write(u32, address, cpu.r[rd]);
|
||||
bus.write32(address, cpu.r[rd]);
|
||||
},
|
||||
0b01 => {
|
||||
// STRB
|
||||
bus.write(u8, address, @truncate(u8, cpu.r[rd]));
|
||||
bus.write8(address, @truncate(u8, cpu.r[rd]));
|
||||
},
|
||||
0b10 => {
|
||||
// LDR
|
||||
const value = bus.read(u32, address);
|
||||
const value = bus.read32(address);
|
||||
cpu.r[rd] = rotr(u32, value, 8 * (address & 0x3));
|
||||
},
|
||||
0b11 => {
|
||||
// LDRB
|
||||
cpu.r[rd] = bus.read(u8, address);
|
||||
cpu.r[rd] = bus.read8(address);
|
||||
},
|
||||
}
|
||||
}
|
||||
|
|
@ -90,22 +90,22 @@ pub fn format9(comptime B: bool, comptime L: bool, comptime offset: u5) InstrFn
|
|||
if (B) {
|
||||
// LDRB
|
||||
const address = cpu.r[rb] + offset;
|
||||
cpu.r[rd] = bus.read(u8, address);
|
||||
cpu.r[rd] = bus.read8(address);
|
||||
} else {
|
||||
// LDR
|
||||
const address = cpu.r[rb] + (@as(u32, offset) << 2);
|
||||
const value = bus.read(u32, address);
|
||||
const value = bus.read32(address);
|
||||
cpu.r[rd] = rotr(u32, value, 8 * (address & 0x3));
|
||||
}
|
||||
} else {
|
||||
if (B) {
|
||||
// STRB
|
||||
const address = cpu.r[rb] + offset;
|
||||
bus.write(u8, address, @truncate(u8, cpu.r[rd]));
|
||||
bus.write8(address, @truncate(u8, cpu.r[rd]));
|
||||
} else {
|
||||
// STR
|
||||
const address = cpu.r[rb] + (@as(u32, offset) << 2);
|
||||
bus.write(u32, address, cpu.r[rd]);
|
||||
bus.write32(address, cpu.r[rd]);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -122,11 +122,11 @@ pub fn format10(comptime L: bool, comptime offset: u5) InstrFn {
|
|||
|
||||
if (L) {
|
||||
// LDRH
|
||||
const value = bus.read(u16, address);
|
||||
const value = bus.read16(address);
|
||||
cpu.r[rd] = rotr(u32, value, 8 * (address & 1));
|
||||
} else {
|
||||
// STRH
|
||||
bus.write(u16, address, @truncate(u16, cpu.r[rd]));
|
||||
bus.write16(address, @truncate(u16, cpu.r[rd]));
|
||||
}
|
||||
}
|
||||
}.inner;
|
||||
|
|
@ -140,11 +140,11 @@ pub fn format11(comptime L: bool, comptime rd: u3) InstrFn {
|
|||
|
||||
if (L) {
|
||||
// LDR
|
||||
const value = bus.read(u32, address);
|
||||
const value = bus.read32(address);
|
||||
cpu.r[rd] = rotr(u32, value, 8 * (address & 0x3));
|
||||
} else {
|
||||
// STR
|
||||
bus.write(u32, address, cpu.r[rd]);
|
||||
bus.write32(address, cpu.r[rd]);
|
||||
}
|
||||
}
|
||||
}.inner;
|
||||
|
|
|
|||
|
|
@ -457,7 +457,6 @@ const Palette = struct {
|
|||
self.buf[addr + 1] = @truncate(u8, value >> 8);
|
||||
self.buf[addr + 0] = @truncate(u8, value >> 0);
|
||||
},
|
||||
u8 => log.err("Tried to write {} 0x{X:0>2} to 0x{X:0>8}", .{ T, value, address }),
|
||||
else => @compileError("PALRAM: Unsupported write width"),
|
||||
}
|
||||
}
|
||||
|
|
@ -512,7 +511,6 @@ const Vram = struct {
|
|||
self.buf[addr + 1] = @truncate(u8, value >> 8);
|
||||
self.buf[addr + 0] = @truncate(u8, value >> 0);
|
||||
},
|
||||
u8 => log.err("Tried to write {} 0x{X:0>2} to 0x{X:0>8}", .{ T, value, address }),
|
||||
else => @compileError("VRAM: Unsupported write width"),
|
||||
}
|
||||
}
|
||||
|
|
@ -568,7 +566,6 @@ const Oam = struct {
|
|||
self.buf[addr + 1] = @truncate(u8, value >> 8);
|
||||
self.buf[addr + 0] = @truncate(u8, value >> 0);
|
||||
},
|
||||
u8 => log.err("Tried to write {} 0x{X:0>2} to 0x{X:0>8}", .{ T, value, address }),
|
||||
else => @compileError("OAM: Unsupported write width"),
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue