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base: paoda:75ba9a4bf942171f7c0a0eacbcab4a7f8f27f32b
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paoda:main
paoda:april-fools
paoda:window
paoda:apu-things
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compare: paoda:24def29fc848fe81618111ac326535f2b86a12c7
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paoda:main
paoda:april-fools
paoda:window
paoda:apu-things

2 Commits
75ba9a4bf9 ... 24def29fc8

Author SHA1 Message Date
Rekai Nyangadzayi Musuka 24def29fc8 feat: panic on unimplemented I/O in ReleaseSafe/Debug but not ReleaseFast 2022-04-21 10:44:03 -03:00
Rekai Nyangadzayi Musuka 9cce4d9859 chore: misc improvements 2022-04-21 10:15:52 -03:00
12 changed files with 99 additions and 118 deletions
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13
src/Bus.zig
View File

@ -21,8 +21,6 @@ const log = std.log.scoped(.Bus);
const rotr = @import("util.zig").rotr;
const Self = @This();
const panic_on_und_bus: bool = false;
pak: GamePak,
bios: Bios,
ppu: Ppu,
@ -73,7 +71,7 @@ pub fn handleDMATransfers(self: *Self) void {
}
}
fn isDmaRunning(self: *const Self) bool {
inline fn isDmaRunning(self: *const Self) bool {
return self.dma._0.active or
self.dma._1.active or
self.dma._2.active or
@ -198,12 +196,3 @@ fn alignAddress(comptime T: type, address: u32) u32 {
else => @compileError("Bus: Invalid read/write type"),
};
}
fn undRead(comptime format: []const u8, args: anytype) u8 {
if (panic_on_und_bus) std.debug.panic(format, args) else log.warn(format, args);
return 0;
}
fn undWrite(comptime format: []const u8, args: anytype) void {
if (panic_on_und_bus) std.debug.panic(format, args) else log.warn(format, args);
}

10
src/apu.zig
View File

@ -192,7 +192,7 @@ pub const Apu = struct {
const right = (chA_right + chB_right + (psg_right * 0.05)) / 3;
if (self.sampling_cycle != self.bias.sampling_cycle.read()) {
log.warn("Sampling Cycle changed from {} to {}", .{ self.sampling_cycle, self.bias.sampling_cycle.read() });
log.info("Sampling Cycle changed from {} to {}", .{ self.sampling_cycle, self.bias.sampling_cycle.read() });
// Sample Rate Changed, Create a new Resampler since i can't figure out how to change
// the parameters of the old one
@ -203,17 +203,17 @@ pub const Apu = struct {
self.stream = SDL.SDL_NewAudioStream(SDL.AUDIO_F32, 2, @intCast(c_int, self.sampleRate()), SDL.AUDIO_F32, 2, host_sample_rate) orelse unreachable;
}
while (SDL.SDL_AudioStreamAvailable(self.stream) > (@sizeOf(f32) * 2 * 0x800)) {}
// while (SDL.SDL_AudioStreamAvailable(self.stream) > (@sizeOf(f32) * 2 * 0x800)) {}
_ = SDL.SDL_AudioStreamPut(self.stream, &[2]f32{ left, right }, 2 * @sizeOf(f32));
self.sched.push(.SampleAudio, self.sched.now() + self.sampleTicks() - late);
}
inline fn sampleTicks(self: *const Self) u64 {
fn sampleTicks(self: *const Self) u64 {
return (1 << 24) / self.sampleRate();
}
inline fn sampleRate(self: *const Self) u64 {
fn sampleRate(self: *const Self) u64 {
return @as(u64, 1) << (15 + @as(u6, self.bias.sampling_cycle.read()));
}
@ -1046,7 +1046,7 @@ const WaveDevice = struct {
u8 => {
self.buf[base + addr - 0x0400_0090] = value;
},
else => log.err("Unhandled {} write to Ch3 Wave RAM", .{T}),
else => @compileError("Ch3 WAVERAM: Unsupported write width"),
}
}
};

4
src/bus/Bios.zig
View File

@ -31,7 +31,7 @@ pub fn deinit(self: Self) void {
pub fn read(self: *const Self, comptime T: type, addr: usize) T {
if (self.buf) |buf| {
if (addr > buf.len) {
log.err("Tried to read {} from {X:0>8} (open bus)", .{ T, addr });
log.debug("Tried to read {} from {X:0>8} (open bus)", .{ T, addr });
return 0;
}
@ -48,5 +48,5 @@ pub fn read(self: *const Self, comptime T: type, addr: usize) T {
pub fn write(_: *Self, comptime T: type, addr: usize, value: T) void {
@setCold(true);
log.err("Tried to write {} 0x{X:} to 0x{X:0>8} ", .{ T, value, addr });
log.debug("Tried to write {} 0x{X:} to 0x{X:0>8} ", .{ T, value, addr });
}

2
src/bus/backup.zig
View File

@ -86,7 +86,7 @@ pub const Backup = struct {
return log.info("Loaded Save from {s}", .{file_path});
}
log.err("{s} is {} bytes, but we expected {} bytes", .{ file_path, file_buf.len, self.buf.len });
log.debug("{s} is {} bytes, but we expected {} bytes", .{ file_path, file_buf.len, self.buf.len });
},
else => return SaveError.UnsupportedBackupKind,
}

7
src/bus/dma.zig
View File

@ -111,13 +111,6 @@ fn DmaController(comptime id: u2) type {
self.writeCntHigh(@truncate(u16, word >> 16));
}
pub inline fn check(self: *Self, bus: *Bus) bool {
if (!self.active) return false; // FIXME: Check CNT register?
self.step(bus);
return true;
}
pub fn step(self: *Self, bus: *Bus) bool {
if (!self.active) return false;

114
src/bus/io.zig
View File

@ -1,4 +1,5 @@
const std = @import("std");
const builtin = @import("builtin");
const Bit = @import("bitfield").Bit;
const Bitfield = @import("bitfield").Bitfield;
@ -6,8 +7,6 @@ const Bus = @import("../Bus.zig");
const DmaController = @import("dma.zig").DmaController;
const Scheduler = @import("../scheduler.zig").Scheduler;
const panic_on_und_io: bool = false;
const log = std.log.scoped(.@"I/O");
pub const Io = struct {
@ -61,7 +60,7 @@ pub fn read(bus: *const Bus, comptime T: type, address: u32) T {
// Interrupts
0x0400_0200 => @as(T, bus.io.irq.raw) << 16 | bus.io.ie.raw,
0x0400_0208 => @boolToInt(bus.io.ime),
else => undRead("Tried to read {} from 0x{X:0>8}", .{ T, address }),
else => undefinedRead("Tried to read {} from 0x{X:0>8}", .{ T, address }),
},
u16 => switch (address) {
// Display
@ -103,7 +102,7 @@ pub fn read(bus: *const Bus, comptime T: type, address: u32) T {
0x0400_0202 => bus.io.irq.raw,
0x0400_0204 => unimplementedRead("Read halfword from WAITCNT", .{}),
0x0400_0208 => @boolToInt(bus.io.ime),
else => undRead("Tried to read {} from 0x{X:0>8}", .{ T, address }),
else => undefinedRead("Tried to read {} from 0x{X:0>8}", .{ T, address }),
},
u8 => return switch (address) {
// Display
@ -127,7 +126,7 @@ pub fn read(bus: *const Bus, comptime T: type, address: u32) T {
// Interrupts
0x0400_0200 => @truncate(T, bus.io.ie.raw),
0x0400_0300 => @enumToInt(bus.io.postflg),
else => undRead("Tried to read byte from 0x{X:0>8}", .{address}),
else => undefinedRead("Tried to read {} from 0x{X:0>8}", .{ T, address }),
},
else => @compileError("I/O: Unsupported read width"),
};
@ -179,13 +178,13 @@ pub fn write(bus: *Bus, comptime T: type, address: u32, value: T) void {
0x0400_010C => bus.tim._3.writeCnt(value),
// Serial Communication 1
0x0400_0120 => log.warn("Wrote 0x{X:0>8} to SIODATA32", .{value}),
0x0400_0120 => log.debug("Wrote 0x{X:0>8} to SIODATA32", .{value}),
// Interrupts
0x0400_0200 => bus.io.setIrqs(value),
0x0400_0204 => log.warn("Wrote 0x{X:0>8} to WAITCNT", .{value}),
0x0400_0204 => log.debug("Wrote 0x{X:0>8} to WAITCNT", .{value}),
0x0400_0208 => bus.io.ime = value & 1 == 1,
else => undWrite("Tried to write {} 0x{X:0>8} to 0x{X:0>8}", .{ T, value, address }),
else => undefinedWrite("Tried to write {} 0x{X:0>8} to 0x{X:0>8}", .{ T, value, address }),
},
u16 => switch (address) {
// Display
@ -204,32 +203,32 @@ pub fn write(bus: *Bus, comptime T: type, address: u32, value: T) void {
0x0400_001A => bus.ppu.bg[2].vofs.raw = value,
0x0400_001C => bus.ppu.bg[3].hofs.raw = value,
0x0400_001E => bus.ppu.bg[3].vofs.raw = value,
0x0400_0020 => log.warn("Wrote 0x{X:0>4} to BG2PA", .{value}),
0x0400_0022 => log.warn("Wrote 0x{X:0>4} to BG2PB", .{value}),
0x0400_0024 => log.warn("Wrote 0x{X:0>4} to BG2PC", .{value}),
0x0400_0026 => log.warn("Wrote 0x{X:0>4} to BG2PD", .{value}),
0x0400_0028 => log.warn("Wrote 0x{X:0>4} to BG2X_L", .{value}),
0x0400_002A => log.warn("Wrote 0x{X:0>4} to BG2X_H", .{value}),
0x0400_002C => log.warn("Wrote 0x{X:0>4} to BG2Y_L", .{value}),
0x0400_002E => log.warn("Wrote 0x{X:0>4} to BG2Y_H", .{value}),
0x0400_0030 => log.warn("Wrote 0x{X:0>4} to BG3PA", .{value}),
0x0400_0032 => log.warn("Wrote 0x{X:0>4} to BG3PB", .{value}),
0x0400_0034 => log.warn("Wrote 0x{X:0>4} to BG3PC", .{value}),
0x0400_0036 => log.warn("Wrote 0x{X:0>4} to BG3PD", .{value}),
0x0400_0038 => log.warn("Wrote 0x{X:0>4} to BG3X_L", .{value}),
0x0400_003A => log.warn("Wrote 0x{X:0>4} to BG3X_H", .{value}),
0x0400_003C => log.warn("Wrote 0x{X:0>4} to BG3Y_L", .{value}),
0x0400_003E => log.warn("Wrote 0x{X:0>4} to BG3Y_H", .{value}),
0x0400_0040 => log.warn("Wrote 0x{X:0>4} to WIN0H", .{value}),
0x0400_0042 => log.warn("Wrote 0x{X:0>4} to WIN1H", .{value}),
0x0400_0044 => log.warn("Wrote 0x{X:0>4} to WIN0V", .{value}),
0x0400_0046 => log.warn("Wrote 0x{X:0>4} to WIN1V", .{value}),
0x0400_0048 => log.warn("Wrote 0x{X:0>4} to WININ", .{value}),
0x0400_004A => log.warn("Wrote 0x{X:0>4} to WINOUT", .{value}),
0x0400_004C => log.warn("Wrote 0x{X:0>4} to MOSAIC", .{value}),
0x0400_0050 => log.warn("Wrote 0x{X:0>4} to BLDCNT", .{value}),
0x0400_0052 => log.warn("Wrote 0x{X:0>4} to BLDALPHA", .{value}),
0x0400_0054 => log.warn("Wrote 0x{X:0>4} to BLDY", .{value}),
0x0400_0020 => log.debug("Wrote 0x{X:0>4} to BG2PA", .{value}),
0x0400_0022 => log.debug("Wrote 0x{X:0>4} to BG2PB", .{value}),
0x0400_0024 => log.debug("Wrote 0x{X:0>4} to BG2PC", .{value}),
0x0400_0026 => log.debug("Wrote 0x{X:0>4} to BG2PD", .{value}),
0x0400_0028 => log.debug("Wrote 0x{X:0>4} to BG2X_L", .{value}),
0x0400_002A => log.debug("Wrote 0x{X:0>4} to BG2X_H", .{value}),
0x0400_002C => log.debug("Wrote 0x{X:0>4} to BG2Y_L", .{value}),
0x0400_002E => log.debug("Wrote 0x{X:0>4} to BG2Y_H", .{value}),
0x0400_0030 => log.debug("Wrote 0x{X:0>4} to BG3PA", .{value}),
0x0400_0032 => log.debug("Wrote 0x{X:0>4} to BG3PB", .{value}),
0x0400_0034 => log.debug("Wrote 0x{X:0>4} to BG3PC", .{value}),
0x0400_0036 => log.debug("Wrote 0x{X:0>4} to BG3PD", .{value}),
0x0400_0038 => log.debug("Wrote 0x{X:0>4} to BG3X_L", .{value}),
0x0400_003A => log.debug("Wrote 0x{X:0>4} to BG3X_H", .{value}),
0x0400_003C => log.debug("Wrote 0x{X:0>4} to BG3Y_L", .{value}),
0x0400_003E => log.debug("Wrote 0x{X:0>4} to BG3Y_H", .{value}),
0x0400_0040 => log.debug("Wrote 0x{X:0>4} to WIN0H", .{value}),
0x0400_0042 => log.debug("Wrote 0x{X:0>4} to WIN1H", .{value}),
0x0400_0044 => log.debug("Wrote 0x{X:0>4} to WIN0V", .{value}),
0x0400_0046 => log.debug("Wrote 0x{X:0>4} to WIN1V", .{value}),
0x0400_0048 => log.debug("Wrote 0x{X:0>4} to WININ", .{value}),
0x0400_004A => log.debug("Wrote 0x{X:0>4} to WINOUT", .{value}),
0x0400_004C => log.debug("Wrote 0x{X:0>4} to MOSAIC", .{value}),
0x0400_0050 => log.debug("Wrote 0x{X:0>4} to BLDCNT", .{value}),
0x0400_0052 => log.debug("Wrote 0x{X:0>4} to BLDALPHA", .{value}),
0x0400_0054 => log.debug("Wrote 0x{X:0>4} to BLDY", .{value}),
0x0400_004E, 0x0400_0056 => {}, // Not used
// Sound
@ -294,30 +293,30 @@ pub fn write(bus: *Bus, comptime T: type, address: u32, value: T) void {
0x0400_0110 => {}, // Not Used
// Serial Communication 1
0x0400_0120 => log.warn("Wrote 0x{X:0>4} to SIOMULTI0", .{value}),
0x0400_0122 => log.warn("Wrote 0x{X:0>4} to SIOMULTI1", .{value}),
0x0400_0124 => log.warn("Wrote 0x{X:0>4} to SIOMULTI2", .{value}),
0x0400_0126 => log.warn("Wrote 0x{X:0>4} to SIOMULTI3", .{value}),
0x0400_0128 => log.warn("Wrote 0x{X:0>4} to SIOCNT", .{value}),
0x0400_012A => log.warn("Wrote 0x{X:0>4} to SIOMLT_SEND", .{value}),
0x0400_0120 => log.debug("Wrote 0x{X:0>4} to SIOMULTI0", .{value}),
0x0400_0122 => log.debug("Wrote 0x{X:0>4} to SIOMULTI1", .{value}),
0x0400_0124 => log.debug("Wrote 0x{X:0>4} to SIOMULTI2", .{value}),
0x0400_0126 => log.debug("Wrote 0x{X:0>4} to SIOMULTI3", .{value}),
0x0400_0128 => log.debug("Wrote 0x{X:0>4} to SIOCNT", .{value}),
0x0400_012A => log.debug("Wrote 0x{X:0>4} to SIOMLT_SEND", .{value}),
// Keypad Input
0x0400_0130 => log.warn("Wrote 0x{X:0>4} to KEYINPUT. Ignored", .{value}),
0x0400_0132 => log.warn("Wrote 0x{X:0>4} to KEYCNT", .{value}),
0x0400_0130 => log.debug("Wrote 0x{X:0>4} to KEYINPUT. Ignored", .{value}),
0x0400_0132 => log.debug("Wrote 0x{X:0>4} to KEYCNT", .{value}),
// Serial Communication 2
0x0400_0134 => log.warn("Wrote 0x{X:0>4} to RCNT", .{value}),
0x0400_0140 => log.warn("Wrote 0x{X:0>4} to JOYCNT", .{value}),
0x0400_0158 => log.warn("Wrote 0x{X:0>4} to JOYSTAT", .{value}),
0x0400_0134 => log.debug("Wrote 0x{X:0>4} to RCNT", .{value}),
0x0400_0140 => log.debug("Wrote 0x{X:0>4} to JOYCNT", .{value}),
0x0400_0158 => log.debug("Wrote 0x{X:0>4} to JOYSTAT", .{value}),
0x0400_0142, 0x0400_015A => {}, // Not Used
// Interrupts
0x0400_0200 => bus.io.ie.raw = value,
0x0400_0202 => bus.io.irq.raw &= ~value,
0x0400_0204 => log.warn("Wrote 0x{X:0>4} to WAITCNT", .{value}),
0x0400_0204 => log.debug("Wrote 0x{X:0>4} to WAITCNT", .{value}),
0x0400_0208 => bus.io.ime = value & 1 == 1,
0x0400_0206, 0x0400_020A => {}, // Not Used
else => undWrite("Tried to write {} 0x{X:0>4} to 0x{X:0>8}", .{ T, value, address }),
else => undefinedWrite("Tried to write {} 0x{X:0>4} to 0x{X:0>8}", .{ T, value, address }),
},
u8 => switch (address) {
// Display
@ -354,32 +353,37 @@ pub fn write(bus: *Bus, comptime T: type, address: u32, value: T) void {
0x0400_0090...0x0400_009F => bus.apu.ch3.wave_dev.write(T, bus.apu.ch3.select, address, value),
// Serial Communication 1
0x0400_0128 => log.warn("Wrote 0x{X:0>2} to SIOCNT (low)", .{value}),
0x0400_0128 => log.debug("Wrote 0x{X:0>2} to SIOCNT (low)", .{value}),
// Serial Communication 2
0x0400_0140 => log.warn("Wrote 0x{X:0>2} to JOYCNT (low)", .{value}),
0x0400_0140 => log.debug("Wrote 0x{X:0>2} to JOYCNT (low)", .{value}),
// Interrupts
0x0400_0208 => bus.io.ime = value & 1 == 1,
0x0400_0301 => bus.io.haltcnt = if (value >> 7 & 1 == 0) .Halt else std.debug.panic("TODO: Implement STOP", .{}),
else => undWrite("Tried to write 0x{X:0>2} to 0x{X:0>8}", .{ value, address }),
else => undefinedWrite("Tried to write {} 0x{X:0>2} to 0x{X:0>8}", .{ T, value, address }),
},
else => @compileError("I/O: Unsupported write width"),
};
}
fn undRead(comptime format: []const u8, args: anytype) u8 {
if (panic_on_und_io) std.debug.panic(format, args) else log.warn(format, args);
fn undefinedRead(comptime format: []const u8, args: anytype) u8 {
log.debug(format, args);
if (builtin.mode == .Debug) std.debug.panic("TODO: Implement I/O Register", .{});
return 0;
}
fn unimplementedRead(comptime format: []const u8, args: anytype) u8 {
log.warn(format, args);
log.debug(format, args);
if (builtin.mode == .Debug) std.debug.panic("TODO: Implement I/O Register", .{});
return 0;
}
fn undWrite(comptime format: []const u8, args: anytype) void {
if (panic_on_und_io) std.debug.panic(format, args) else log.warn(format, args);
fn undefinedWrite(comptime format: []const u8, args: anytype) void {
log.debug(format, args);
if (builtin.mode == .Debug) std.debug.panic("TODO: Implement I/O Register", .{});
}
/// Read / Write

19
src/cpu.zig
View File

@ -253,12 +253,12 @@ pub const Arm7tdmi = struct {
pub fn step(self: *Self) void {
if (self.cpsr.t.read()) {
const opcode = self.thumbFetch();
const opcode = self.fetch(u16);
if (enable_logging) if (self.log_file) |file| self.debug_log(file, opcode);
thumb_lut[thumbIdx(opcode)](self, &self.bus, opcode);
} else {
const opcode = self.fetch();
const opcode = self.fetch(u32);
if (enable_logging) if (self.log_file) |file| self.debug_log(file, opcode);
if (checkCond(self.cpsr, @truncate(u4, opcode >> 28))) {
@ -272,12 +272,12 @@ pub const Arm7tdmi = struct {
if (should_handle != 0) {
self.bus.io.haltcnt = .Execute;
// log.info("An Interrupt was Fired!", .{});
// log.debug("An Interrupt was Fired!", .{});
// Either IME is not true or I in CPSR is true
// Don't handle interrupts
if (!self.bus.io.ime or self.cpsr.i.read()) return;
// log.info("An interrupt was Handled!", .{});
// log.debug("An interrupt was Handled!", .{});
// retAddr.gba says r15 on it's own is off by -04h in both ARM and THUMB mode
const r15 = self.r[15] + 4;
@ -293,14 +293,11 @@ pub const Arm7tdmi = struct {
}
}
fn thumbFetch(self: *Self) u16 {
defer self.r[15] += 2;
return self.bus.read(u16, self.r[15]);
}
inline fn fetch(self: *Self, comptime T: type) T {
comptime std.debug.assert(T == u32 or T == u16); // Opcode may be 32-bit (ARM) or 16-bit (THUMB)
defer self.r[15] += if (T == u32) 4 else 2;
fn fetch(self: *Self) u32 {
defer self.r[15] += 4;
return self.bus.read(u32, self.r[15]);
return self.bus.read(T, self.r[15]);
}
pub fn fakePC(self: *const Self) u32 {

4
src/cpu/arm/psr_transfer.zig
View File

@ -17,7 +17,7 @@ pub fn psrTransfer(comptime I: bool, comptime R: bool, comptime kind: u2) InstrF
// MRS
const rd = opcode >> 12 & 0xF;
if (R and !cpu.hasSPSR()) log.warn("Tried to read SPSR from User/System Mode", .{});
if (R and !cpu.hasSPSR()) log.err("Tried to read SPSR from User/System Mode", .{});
cpu.r[rd] = if (R) cpu.spsr.raw else cpu.cpsr.raw;
},
0b10 => {
@ -26,7 +26,7 @@ pub fn psrTransfer(comptime I: bool, comptime R: bool, comptime kind: u2) InstrF
const rm_idx = opcode & 0xF;
const right = if (I) rotr(u32, opcode & 0xFF, (opcode >> 8 & 0xF) << 1) else cpu.r[rm_idx];
if (R and !cpu.hasSPSR()) log.warn("Tried to write to SPSR in User/System Mode", .{});
if (R and !cpu.hasSPSR()) log.err("Tried to write to SPSR in User/System Mode", .{});
if (R) {
if (cpu.isPrivileged()) cpu.spsr.raw = fieldMask(&cpu.spsr, field_mask, right);

10
src/emu.zig
View File

@ -57,12 +57,12 @@ pub fn runFrame(sched: *Scheduler, cpu: *Arm7tdmi) void {
}
pub fn runUnsync(quit: *Atomic(bool), sched: *Scheduler, cpu: *Arm7tdmi) void {
log.info("Unsynchronized EmuThread has begun", .{});
log.info("Start unsynchronized emu thread", .{});
while (!quit.load(.Unordered)) runFrame(sched, cpu);
}
pub fn runSync(quit: *Atomic(bool), sched: *Scheduler, cpu: *Arm7tdmi) void {
log.info("Synchronized EmuThread has begun", .{});
log.info("Start synchronized emu thread", .{});
var timer = Timer.start() catch unreachable;
var wake_time: u64 = frame_period;
@ -79,7 +79,7 @@ pub fn runSync(quit: *Atomic(bool), sched: *Scheduler, cpu: *Arm7tdmi) void {
}
pub fn runUnsyncFps(quit: *Atomic(bool), fps: *FpsAverage, sched: *Scheduler, cpu: *Arm7tdmi) void {
log.info("Unsynchronized EmuThread with FPS Tracking has begun", .{});
log.info("Start unsynchronized emu thread w/ fps tracking", .{});
var fps_timer = Timer.start() catch unreachable;
while (!quit.load(.Unordered)) {
@ -89,7 +89,7 @@ pub fn runUnsyncFps(quit: *Atomic(bool), fps: *FpsAverage, sched: *Scheduler, cp
}
pub fn runSyncFps(quit: *Atomic(bool), fps: *FpsAverage, sched: *Scheduler, cpu: *Arm7tdmi) void {
log.info("Synchronized EmuThread has begun", .{});
log.info("Start synchronized emu thread w/ fps tracking", .{});
var timer = Timer.start() catch unreachable;
var fps_timer = Timer.start() catch unreachable;
var wake_time: u64 = frame_period;
@ -110,7 +110,7 @@ pub fn runSyncFps(quit: *Atomic(bool), fps: *FpsAverage, sched: *Scheduler, cpu:
}
pub fn runBusyLoop(quit: *Atomic(bool), sched: *Scheduler, cpu: *Arm7tdmi) void {
log.info("Run EmuThread with spin-loop sync", .{});
log.info("Start synchronized emu thread using busy loop", .{});
var timer = Timer.start() catch unreachable;
var wake_time: u64 = frame_period;

12
src/main.zig
View File

@ -65,9 +65,9 @@ pub fn main() anyerror!void {
};
// Determine Save Directory
const save_path = try setupSavePath(alloc);
defer if (save_path) |path| alloc.free(path);
log.info("Save Path: {s}", .{save_path});
const save_dir = try setupSavePath(alloc);
defer if (save_dir) |path| alloc.free(path);
log.info("Found save directory: {s}", .{save_dir});
// Initialize SDL
_ = initSdl2();
@ -77,7 +77,7 @@ pub fn main() anyerror!void {
var scheduler = Scheduler.init(alloc);
defer scheduler.deinit();
const paths = .{ .bios = bios_path, .rom = rom_path, .save = save_path };
const paths = .{ .bios = bios_path, .rom = rom_path, .save = save_dir };
var cpu = try Arm7tdmi.init(alloc, &scheduler, paths);
defer cpu.deinit();
@ -266,7 +266,5 @@ fn initAudio(apu: *Apu) SDL.SDL_AudioDeviceID {
export fn audioCallback(userdata: ?*anyopaque, stream: [*c]u8, len: c_int) void {
const apu = @ptrCast(*Apu, @alignCast(8, userdata));
const result = SDL.SDL_AudioStreamGet(apu.stream, stream, len);
if (result < 0) log.err("Audio Callback Underflow", .{});
_ = SDL.SDL_AudioStreamGet(apu.stream, stream, len);
}

20
src/ppu.zig
View File

@ -645,43 +645,43 @@ const Sprite = struct {
};
}
inline fn x(self: *const Self) u9 {
fn x(self: *const Self) u9 {
return self.attr1.x.read();
}
inline fn y(self: *const Self) u8 {
fn y(self: *const Self) u8 {
return self.attr0.y.read();
}
inline fn is_8bpp(self: *const Self) bool {
fn is_8bpp(self: *const Self) bool {
return self.attr0.is_8bpp.read();
}
inline fn shape(self: *const Self) u2 {
fn shape(self: *const Self) u2 {
return self.attr0.shape.read();
}
inline fn size(self: *const Self) u2 {
fn size(self: *const Self) u2 {
return self.attr1.size.read();
}
inline fn tile_id(self: *const Self) u10 {
fn tile_id(self: *const Self) u10 {
return self.attr2.tile_id.read();
}
inline fn pal_bank(self: *const Self) u4 {
fn pal_bank(self: *const Self) u4 {
return self.attr2.pal_bank.read();
}
inline fn h_flip(self: *const Self) bool {
fn h_flip(self: *const Self) bool {
return self.attr1.h_flip.read();
}
inline fn v_flip(self: *const Self) bool {
fn v_flip(self: *const Self) bool {
return self.attr1.v_flip.read();
}
inline fn priority(self: *const Self) u2 {
fn priority(self: *const Self) u2 {
return self.attr2.rel_prio.read();
}
};

2
src/scheduler.zig
View File

@ -35,7 +35,7 @@ pub const Scheduler = struct {
switch (event.kind) {
.HeatDeath => {
log.err("A u64 overflowered. This *actually* should never happen.", .{});
log.err("u64 overflow. This *actually* should never happen.", .{});
unreachable;
},
.Draw => {