fix: flush pipeline on specific LDR/STR regsiter writes

src/cpu/arm/half_signed_data_transfer.zig

@@ -15,7 +15,7 @@ pub fn halfAndSignedDataTransfer(comptime P: bool, comptime U: bool, comptime I:
             const rm = opcode & 0xF;
             const imm_offset_high = opcode >> 8 & 0xF;
 
-            const base = cpu.r[rn] + if (!L) 4 else @as(u32, 0);
+            const base = cpu.r[rn] + if (!L and rn == 0xF) 4 else @as(u32, 0);
             const offset = if (I) imm_offset_high << 4 | rm else cpu.r[rm];
 
             const modified_base = if (U) base +% offset else base -% offset;

src/cpu/arm/single_data_transfer.zig

@@ -45,8 +45,16 @@ pub fn singleDataTransfer(comptime I: bool, comptime P: bool, comptime U: bool,
             }
 
             address = modified_base;
-            if (W and P or !P) cpu.r[rn] = address;
-            if (L) cpu.r[rd] = result; // This emulates the LDR rd == rn behaviour
+            if (W and P or !P) {
+                cpu.r[rn] = address;
+                if (rn == 0xF) cpu.pipe.flush();
+            }
+
+            if (L) {
+                // This emulates the LDR rd == rn behaviour
+                cpu.r[rd] = result;
+                if (rd == 0xF) cpu.pipe.flush();
+            }
         }
     }.inner;
 }