chore: dedup code in THUMB instructions

src/cpu.zig

@@ -1,7 +1,6 @@
 const std = @import("std");
 const util = @import("util.zig");
 
-const BarrelShifter = @import("cpu/arm/barrel_shifter.zig");
 const Bus = @import("Bus.zig");
 const Bit = @import("bitfield").Bit;
 const Bitfield = @import("bitfield").Bitfield;
@@ -20,9 +19,14 @@ const branchAndExchange = @import("cpu/arm/branch.zig").branchAndExchange;
 const softwareInterrupt = @import("cpu/arm/software_interrupt.zig").softwareInterrupt;
 
 // THUMB Instruction Groups
+const format1 = @import("cpu/thumb/format1.zig").format1;
 const format3 = @import("cpu/thumb/format3.zig").format3;
+const format2 = @import("cpu/thumb/format2.zig").format2;
 const format5 = @import("cpu/thumb/format5.zig").format5;
+const format6 = @import("cpu/thumb/format6.zig").format6;
 const format12 = @import("cpu/thumb/format12.zig").format12;
+const format16 = @import("cpu/thumb/format16.zig").format16;
+const format19 = @import("cpu/thumb/format19.zig").format19;
 
 pub const ArmInstrFn = fn (*Arm7tdmi, *Bus, u32) void;
 pub const ThumbInstrFn = fn (*Arm7tdmi, *Bus, u16) void;
@@ -269,7 +273,14 @@ pub const Arm7tdmi = struct {
 
         var log_str: []u8 = undefined;
         if (self.cpsr.t.read()) {
+            if (opcode >> 11 == 0x1E) {
+                // Instruction 1 of a BL Opcode, print in ARM mode
+                const tmp_opcode = self.bus.read32(self.r[15] - 2);
+                const be_opcode = tmp_opcode << 16 | tmp_opcode >> 16;
+                log_str = try std.fmt.bufPrint(&buf, arm_fmt, .{ r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r13, r14, r15, c_psr, be_opcode });
+            } else {
                 log_str = try std.fmt.bufPrint(&buf, thumb_fmt, .{ r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r13, r14, r15, c_psr, opcode });
+            }
         } else {
             log_str = try std.fmt.bufPrint(&buf, arm_fmt, .{ r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r13, r14, r15, c_psr, opcode });
         }
@@ -286,7 +297,7 @@ inline fn thumbIdx(opcode: u16) u10 {
     return @truncate(u10, opcode >> 6);
 }
 
-fn checkCond(cpsr: PSR, cond: u4) bool {
+pub fn checkCond(cpsr: PSR, cond: u4) bool {
     // TODO: Should I implement an enum?
     return switch (cond) {
         0x0 => cpsr.z.read(), // EQ - Equal
@@ -315,6 +326,20 @@ fn thumbPopulate() [0x400]ThumbInstrFn {
 
         var i: usize = 0;
         while (i < lut.len) : (i += 1) {
+            if (i >> 7 & 0x7 == 0b000) {
+                const op = i >> 5 & 0x3;
+                const offset = i & 0x1F;
+
+                lut[i] = format1(op, offset);
+            }
+            if (i >> 5 & 0x1F == 0b00011) {
+                const I = i >> 4 & 1 == 1;
+                const is_sub = i >> 3 & 1 == 1;
+                const rn = i & 0x7;
+
+                lut[i] = format2(I, is_sub, rn);
+            }
+
             if (i >> 7 & 0x7 == 0b001) {
                 const op = i >> 5 & 0x3;
                 const rd = i >> 2 & 0x7;
@@ -330,12 +355,30 @@ fn thumbPopulate() [0x400]ThumbInstrFn {
                 lut[i] = format5(op, h1, h2);
             }
 
+            if (i >> 5 & 0x1F == 0b01001) {
+                const rd = i >> 2 & 0x7;
+
+                lut[i] = format6(rd);
+            }
+
             if (i >> 6 & 0xF == 0b1010) {
                 const isSP = i >> 5 & 1 == 1;
                 const rd = i >> 2 & 0x7;
 
                 lut[i] = format12(isSP, rd);
             }
+
+            if (i >> 6 & 0xF == 0b1101) {
+                const cond = i >> 2 & 0xF;
+
+                lut[i] = format16(cond);
+            }
+
+            if (i >> 6 & 0xF == 0b1111) {
+                const is_low = i >> 5 & 1 == 1;
+
+                lut[i] = format19(is_low);
+            }
         }
 
         return lut;

src/cpu/arm/data_processing.zig

@@ -1,6 +1,6 @@
 const std = @import("std");
 
-const shifter = @import("barrel_shifter.zig");
+const shifter = @import("../barrel_shifter.zig");
 const Bus = @import("../../Bus.zig");
 const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
 const InstrFn = @import("../../cpu.zig").ArmInstrFn;
@@ -33,184 +33,245 @@ pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime instrKind: u4
                     // AND
                     const result = op1 & op2;
                     cpu.r[rd] = result;
-                    logicFlags(S, cpu, rd, result);
+                    setArmLogicOpFlags(S, cpu, rd, result);
                 },
                 0x1 => {
                     // EOR
                     const result = op1 ^ op2;
                     cpu.r[rd] = result;
-                    logicFlags(S, cpu, rd, result);
+                    setArmLogicOpFlags(S, cpu, rd, result);
+                },
+                0x2 => {
+                    // SUB
+                    cpu.r[rd] = armSub(S, cpu, rd, op1, op2);
+                },
+                0x3 => {
+                    // RSB
+                    cpu.r[rd] = armSub(S, cpu, rd, op2, op1);
                 },
-                0x2 => cpu.r[rd] = sub(S, cpu, rd, op1, op2), // SUB
-                0x3 => cpu.r[rd] = sub(S, cpu, rd, op2, op1), // RSB
                 0x4 => {
                     // ADD
-                    var result: u32 = undefined;
-                    const didOverflow = @addWithOverflow(u32, op1, op2, &result);
-                    cpu.r[rd] = result;
-
-                    if (S) {
-                        if (rd == 0xF) {
-                            cpu.setCpsr(cpu.spsr.raw);
-                        } else {
-                            cpu.cpsr.n.write(result >> 31 & 1 == 1);
-                            cpu.cpsr.z.write(result == 0);
-                            cpu.cpsr.c.write(didOverflow);
-                            cpu.cpsr.v.write(((op1 ^ result) & (op2 ^ result)) >> 31 & 1 == 1);
-                        }
-                    }
+                    cpu.r[rd] = armAdd(S, cpu, rd, op1, op2);
                 },
                 0x5 => {
                     // ADC
-                    var result: u32 = undefined;
-
-                    const did = @addWithOverflow(u32, op1, op2, &result);
-                    const overflow = @addWithOverflow(u32, result, old_carry, &result);
-                    cpu.r[rd] = result;
-
-                    if (S) {
-                        if (rd == 0xF) {
-                            cpu.setCpsr(cpu.spsr.raw);
-                        } else {
-                            cpu.cpsr.n.write(result >> 31 & 1 == 1);
-                            cpu.cpsr.z.write(result == 0);
-                            cpu.cpsr.c.write(did or overflow);
-                            cpu.cpsr.v.write(((op1 ^ result) & (op2 ^ result)) >> 31 & 1 == 1);
-                        }
-                    }
+                    cpu.r[rd] = armAdc(S, cpu, rd, op1, op2, old_carry);
+                },
+                0x6 => {
+                    // SBC
+                    cpu.r[rd] = armSbc(S, cpu, rd, op1, op2, old_carry);
+                },
+                0x7 => {
+                    // RSC
+                    cpu.r[rd] = armSbc(S, cpu, rd, op2, op1, old_carry);
                 },
-                0x6 => cpu.r[rd] = sbc(S, cpu, rd, op1, op2, old_carry), // SBC
-                0x7 => cpu.r[rd] = sbc(S, cpu, rd, op2, op1, old_carry), // RSC
                 0x8 => {
                     // TST
                     if (rd == 0xF) {
                         undefinedTestBehaviour(cpu);
-
                         return;
                     }
 
                     const result = op1 & op2;
-                    testFlags(S, cpu, opcode, result);
+                    setTestOpFlags(S, cpu, opcode, result);
                 },
                 0x9 => {
                     // TEQ
                     if (rd == 0xF) {
                         undefinedTestBehaviour(cpu);
-
                         return;
                     }
 
                     const result = op1 ^ op2;
-                    testFlags(S, cpu, opcode, result);
+                    setTestOpFlags(S, cpu, opcode, result);
                 },
                 0xA => {
                     // CMP
                     if (rd == 0xF) {
                         undefinedTestBehaviour(cpu);
-
                         return;
                     }
 
-                    const result = op1 -% op2;
-
-                    cpu.cpsr.n.write(result >> 31 & 1 == 1);
-                    cpu.cpsr.z.write(result == 0);
-                    cpu.cpsr.c.write(op2 <= op1);
-                    cpu.cpsr.v.write(((op1 ^ result) & (~op2 ^ result)) >> 31 & 1 == 1);
+                    cmp(cpu, op1, op2);
                 },
                 0xB => {
                     // CMN
                     if (rd == 0xF) {
                         undefinedTestBehaviour(cpu);
-
                         return;
                     }
 
-                    var result: u32 = undefined;
-                    const didOverflow = @addWithOverflow(u32, op1, op2, &result);
-
-                    cpu.cpsr.n.write(result >> 31 & 1 == 1);
-                    cpu.cpsr.z.write(result == 0);
-                    cpu.cpsr.c.write(didOverflow);
-                    cpu.cpsr.v.write(((op1 ^ result) & (op2 ^ result)) >> 31 & 1 == 1);
+                    cmn(cpu, op1, op2);
                 },
                 0xC => {
                     // ORR
                     const result = op1 | op2;
                     cpu.r[rd] = result;
-                    logicFlags(S, cpu, rd, result);
+                    setArmLogicOpFlags(S, cpu, rd, result);
                 },
                 0xD => {
                     // MOV
                     cpu.r[rd] = op2;
-                    logicFlags(S, cpu, rd, op2);
+                    setArmLogicOpFlags(S, cpu, rd, op2);
                 },
                 0xE => {
                     // BIC
                     const result = op1 & ~op2;
                     cpu.r[rd] = result;
-                    logicFlags(S, cpu, rd, result);
+                    setArmLogicOpFlags(S, cpu, rd, result);
                 },
                 0xF => {
                     // MVN
                     const result = ~op2;
                     cpu.r[rd] = result;
-                    logicFlags(S, cpu, rd, result);
+                    setArmLogicOpFlags(S, cpu, rd, result);
                 },
             }
         }
     }.inner;
 }
 
-fn sbc(comptime S: bool, cpu: *Arm7tdmi, rd: u4, left: u32, right: u32, old_carry: u1) u32 {
+fn armSbc(comptime S: bool, cpu: *Arm7tdmi, rd: u4, left: u32, right: u32, old_carry: u1) u32 {
+    var result: u32 = undefined;
+    if (S and rd == 0xF) {
+        result = sbc(false, cpu, left, right, old_carry);
+        cpu.setCpsr(cpu.spsr.raw);
+    } else {
+        result = sbc(S, cpu, left, right, old_carry);
+    }
+
+    return result;
+}
+
+pub fn sbc(comptime S: bool, cpu: *Arm7tdmi, left: u32, right: u32, old_carry: u1) u32 {
     // TODO: Make your own version (thanks peach.bot)
     const subtrahend = @as(u64, right) - old_carry + 1;
     const result = @truncate(u32, left -% subtrahend);
 
     if (S) {
-        if (rd == 0xF) {
-            cpu.setCpsr(cpu.spsr.raw);
-        } else {
         cpu.cpsr.n.write(result >> 31 & 1 == 1);
         cpu.cpsr.z.write(result == 0);
         cpu.cpsr.c.write(subtrahend <= left);
         cpu.cpsr.v.write(((left ^ result) & (~right ^ result)) >> 31 & 1 == 1);
     }
+
+    return result;
+}
+
+fn armSub(comptime S: bool, cpu: *Arm7tdmi, rd: u4, left: u32, right: u32) u32 {
+    var result: u32 = undefined;
+    if (S and rd == 0xF) {
+        result = sub(false, cpu, left, right);
+        cpu.setCpsr(cpu.spsr.raw);
+    } else {
+        result = sub(S, cpu, left, right);
     }
 
     return result;
 }
 
-fn sub(comptime S: bool, cpu: *Arm7tdmi, rd: u4, left: u32, right: u32) u32 {
+pub fn sub(comptime S: bool, cpu: *Arm7tdmi, left: u32, right: u32) u32 {
     const result = left -% right;
 
     if (S) {
-        if (rd == 0xF) {
-            cpu.setCpsr(cpu.spsr.raw);
-        } else {
         cpu.cpsr.n.write(result >> 31 & 1 == 1);
         cpu.cpsr.z.write(result == 0);
         cpu.cpsr.c.write(right <= left);
         cpu.cpsr.v.write(((left ^ result) & (~right ^ result)) >> 31 & 1 == 1);
     }
+
+    return result;
+}
+
+fn armAdd(comptime S: bool, cpu: *Arm7tdmi, rd: u4, left: u32, right: u32) u32 {
+    var result: u32 = undefined;
+    if (S and rd == 0xF) {
+        result = add(false, cpu, left, right);
+        cpu.setCpsr(cpu.spsr.raw);
+    } else {
+        result = add(S, cpu, left, right);
     }
 
     return result;
 }
 
-fn logicFlags(comptime S: bool, cpu: *Arm7tdmi, rd: u4, result: u32) void {
+pub fn add(comptime S: bool, cpu: *Arm7tdmi, left: u32, right: u32) u32 {
+    var result: u32 = undefined;
+    const didOverflow = @addWithOverflow(u32, left, right, &result);
+
     if (S) {
-        if (rd == 0xF) {
+        cpu.cpsr.n.write(result >> 31 & 1 == 1);
+        cpu.cpsr.z.write(result == 0);
+        cpu.cpsr.c.write(didOverflow);
+        cpu.cpsr.v.write(((left ^ result) & (right ^ result)) >> 31 & 1 == 1);
+    }
+
+    return result;
+}
+
+fn armAdc(comptime S: bool, cpu: *Arm7tdmi, rd: u4, left: u32, right: u32, old_carry: u1) u32 {
+    var result: u32 = undefined;
+    if (S and rd == 0xF) {
+        result = adc(false, cpu, left, right, old_carry);
         cpu.setCpsr(cpu.spsr.raw);
     } else {
+        result = adc(S, cpu, left, right, old_carry);
+    }
+
+    return result;
+}
+
+pub fn adc(comptime S: bool, cpu: *Arm7tdmi, left: u32, right: u32, old_carry: u1) u32 {
+    var result: u32 = undefined;
+    const did = @addWithOverflow(u32, left, right, &result);
+    const overflow = @addWithOverflow(u32, result, old_carry, &result);
+
+    if (S) {
+        cpu.cpsr.n.write(result >> 31 & 1 == 1);
+        cpu.cpsr.z.write(result == 0);
+        cpu.cpsr.c.write(did or overflow);
+        cpu.cpsr.v.write(((left ^ result) & (right ^ result)) >> 31 & 1 == 1);
+    }
+
+    return result;
+}
+
+pub fn cmp(cpu: *Arm7tdmi, left: u32, right: u32) void {
+    const result = left -% right;
+
+    cpu.cpsr.n.write(result >> 31 & 1 == 1);
+    cpu.cpsr.z.write(result == 0);
+    cpu.cpsr.c.write(right <= left);
+    cpu.cpsr.v.write(((left ^ result) & (~right ^ result)) >> 31 & 1 == 1);
+}
+
+pub fn cmn(cpu: *Arm7tdmi, left: u32, right: u32) void {
+    var result: u32 = undefined;
+    const didOverflow = @addWithOverflow(u32, left, right, &result);
+
+    cpu.cpsr.n.write(result >> 31 & 1 == 1);
+    cpu.cpsr.z.write(result == 0);
+    cpu.cpsr.c.write(didOverflow);
+    cpu.cpsr.v.write(((left ^ result) & (right ^ result)) >> 31 & 1 == 1);
+}
+
+fn setArmLogicOpFlags(comptime S: bool, cpu: *Arm7tdmi, rd: u4, result: u32) void {
+    if (S and rd == 0xF) {
+        cpu.setCpsr(cpu.spsr.raw);
+    } else {
+        setLogicOpFlags(S, cpu, result);
+    }
+}
+
+pub fn setLogicOpFlags(comptime S: bool, cpu: *Arm7tdmi, result: u32) void {
+    if (S) {
         cpu.cpsr.n.write(result >> 31 & 1 == 1);
         cpu.cpsr.z.write(result == 0);
         // C set by Barrel Shifter, V is unaffected
     }
-    }
 }
 
-fn testFlags(comptime S: bool, cpu: *Arm7tdmi, opcode: u32, result: u32) void {
+fn setTestOpFlags(comptime S: bool, cpu: *Arm7tdmi, opcode: u32, result: u32) void {
     cpu.cpsr.n.write(result >> 31 & 1 == 1);
     cpu.cpsr.z.write(result == 0);
     // Barrel Shifter should always calc CPSR C in TST

src/cpu/arm/single_data_transfer.zig

@@ -1,7 +1,7 @@
 const std = @import("std");
 const util = @import("../../util.zig");
 
-const BarrelShifter = @import("barrel_shifter.zig");
+const shifter = @import("../barrel_shifter.zig");
 const Bus = @import("../../Bus.zig");
 const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
 const InstrFn = @import("../../cpu.zig").ArmInstrFn;
@@ -58,9 +58,9 @@ fn registerOffset(cpu: *Arm7tdmi, opcode: u32) u32 {
     const rm = cpu.r[opcode & 0xF];
 
     return switch (@truncate(u2, opcode >> 5)) {
-        0b00 => BarrelShifter.logicalLeft(false, &cpu.cpsr, rm, amount),
-        0b01 => BarrelShifter.logicalRight(false, &cpu.cpsr, rm, amount),
-        0b10 => BarrelShifter.arithmeticRight(false, &cpu.cpsr, rm, amount),
-        0b11 => BarrelShifter.rotateRight(false, &cpu.cpsr, rm, amount),
+        0b00 => shifter.logicalLeft(false, &cpu.cpsr, rm, amount),
+        0b01 => shifter.logicalRight(false, &cpu.cpsr, rm, amount),
+        0b10 => shifter.arithmeticRight(false, &cpu.cpsr, rm, amount),
+        0b11 => shifter.rotateRight(false, &cpu.cpsr, rm, amount),
     };
 }

src/cpu/barrel_shifter.zig

@@ -1,7 +1,7 @@
 const std = @import("std");
 
-const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
-const CPSR = @import("../../cpu.zig").PSR;
+const Arm7tdmi = @import("../cpu.zig").Arm7tdmi;
+const CPSR = @import("../cpu.zig").PSR;
 
 pub fn execute(comptime S: bool, cpu: *Arm7tdmi, opcode: u32) u32 {
     var result: u32 = undefined;

src/cpu/thumb/format1.zig

@@ -0,0 +1,28 @@
+const std = @import("std");
+
+const Bus = @import("../../Bus.zig");
+const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
+const InstrFn = @import("../../cpu.zig").ThumbInstrFn;
+const shifter = @import("../barrel_shifter.zig");
+
+const setLogicOpFlags = @import("../arm/data_processing.zig").setLogicOpFlags;
+
+pub fn format1(comptime op: u2, comptime offset: u5) InstrFn {
+    return struct {
+        fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void {
+            const rs = opcode >> 3 & 0x7;
+            const rd = opcode & 0x7;
+
+            const result = switch (op) {
+                0b00 => shifter.logicalLeft(true, &cpu.cpsr, cpu.r[rs], offset), // LSL
+                0b01 => shifter.logicalRight(true, &cpu.cpsr, cpu.r[rs], offset), // LSR
+                0b10 => shifter.arithmeticRight(true, &cpu.cpsr, cpu.r[rs], offset), // ASR
+                else => std.debug.panic("[CPU|THUMB|Fmt1] {} is an invalid op", .{op}),
+            };
+
+            // Equivalent to an ARM MOVS
+            cpu.r[rd] = result;
+            setLogicOpFlags(true, cpu, result);
+        }
+    }.inner;
+}

src/cpu/thumb/format12.zig

@@ -7,8 +7,9 @@ const InstrFn = @import("../../cpu.zig").ThumbInstrFn;
 pub fn format12(comptime isSP: bool, comptime rd: u3) InstrFn {
     return struct {
         fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void {
-            const left = if (isSP) cpu.r[13] else cpu.r[15] + 2 & 0xFFFF_FFFD; // fetch (+2)
-            const right = @truncate(u10, opcode & 0xFF) << 2;
+            // ADD
+            const left = if (isSP) cpu.r[13] else cpu.fakePC() & 0xFFFF_FFFC;
+            const right = (opcode & 0xFF) << 2;
             const result = left + right; // TODO: What about overflows?
             cpu.r[rd] = result;
         }

src/cpu/thumb/format16.zig

@@ -0,0 +1,26 @@
+const std = @import("std");
+
+const Bus = @import("../../Bus.zig");
+const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
+const InstrFn = @import("../../cpu.zig").ThumbInstrFn;
+
+const checkCond = @import("../../cpu.zig").checkCond;
+const u32SignExtend = @import("../../util.zig").u32SignExtend;
+
+pub fn format16(comptime cond: u4) InstrFn {
+    return struct {
+        fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void {
+            // B
+            const offset = u32SignExtend(8, opcode & 0xFF) << 1;
+
+            const should_execute = switch (cond) {
+                0xE, 0xF => std.debug.panic("[CPU/THUMB] Undefined conditional branch with condition {}", .{cond}),
+                else => checkCond(cpu.cpsr, cond),
+            };
+
+            if (should_execute) {
+                cpu.r[15] = (cpu.fakePC() & 0xFFFF_FFFC) +% offset;
+            }
+        }
+    }.inner;
+}

src/cpu/thumb/format19.zig

@@ -0,0 +1,26 @@
+const std = @import("std");
+
+const Bus = @import("../../Bus.zig");
+const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
+const InstrFn = @import("../../cpu.zig").ThumbInstrFn;
+const u32SignExtend = @import("../../util.zig").u32SignExtend;
+
+pub fn format19(comptime is_low: bool) InstrFn {
+    return struct {
+        fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void {
+            // BL
+            const offset = opcode & 0x3FF;
+
+            if (is_low) {
+                // Instruction 2
+                const old_pc = cpu.r[15];
+
+                cpu.r[15] = cpu.r[14] + (offset << 1);
+                cpu.r[14] = old_pc | 1;
+            } else {
+                // Instruction 1
+                cpu.r[14] = (cpu.fakePC() & 0xFFFF_FFFC) + (u32SignExtend(11, @as(u32, offset)) << 12);
+            }
+        }
+    }.inner;
+}

src/cpu/thumb/format2.zig

@@ -0,0 +1,33 @@
+const std = @import("std");
+
+const Bus = @import("../../Bus.zig");
+const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
+const InstrFn = @import("../../cpu.zig").ThumbInstrFn;
+
+const add = @import("../arm/data_processing.zig").add;
+const sub = @import("../arm/data_processing.zig").sub;
+
+pub fn format2(comptime I: bool, is_sub: bool, rn: u3) InstrFn {
+    return struct {
+        fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void {
+            const rs = opcode >> 3 & 0x7;
+            const rd = @truncate(u3, opcode);
+
+            if (is_sub) {
+                // SUB
+                cpu.r[rd] = if (I) blk: {
+                    break :blk sub(true, cpu, cpu.r[rs], @as(u32, rn));
+                } else blk: {
+                    break :blk sub(true, cpu, cpu.r[rs], cpu.r[rn]);
+                };
+            } else {
+                // ADD
+                cpu.r[rd] = if (I) blk: {
+                    break :blk add(true, cpu, cpu.r[rs], @as(u32, rn));
+                } else blk: {
+                    break :blk add(true, cpu, cpu.r[rs], cpu.r[rn]);
+                };
+            }
+        }
+    }.inner;
+}

src/cpu/thumb/format3.zig

@@ -4,6 +4,11 @@ const Bus = @import("../../Bus.zig");
 const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
 const InstrFn = @import("../../cpu.zig").ThumbInstrFn;
 
+const add = @import("../arm/data_processing.zig").add;
+const sub = @import("../arm/data_processing.zig").sub;
+const cmp = @import("../arm/data_processing.zig").cmp;
+const setLogicOpFlags = @import("../arm/data_processing.zig").setLogicOpFlags;
+
 pub fn format3(comptime op: u2, comptime rd: u3) InstrFn {
     return struct {
         fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void {
@@ -13,44 +18,11 @@ pub fn format3(comptime op: u2, comptime rd: u3) InstrFn {
                 0b00 => {
                     // MOV
                     cpu.r[rd] = offset;
-
-                    cpu.cpsr.n.unset();
-                    cpu.cpsr.z.write(offset == 0);
-                },
-                0b01 => {
-                    // CMP
-                    const left = cpu.r[rd];
-                    const result = left -% offset;
-
-                    cpu.cpsr.n.write(result >> 31 & 1 == 1);
-                    cpu.cpsr.z.write(result == 0);
-                    cpu.cpsr.c.write(offset <= left);
-                    cpu.cpsr.v.write(((left ^ result) & (~offset ^ result)) >> 31 & 1 == 1);
-                },
-                0b10 => {
-                    // ADD
-                    const left = cpu.r[rd];
-
-                    var result: u32 = undefined;
-                    const didOverflow = @addWithOverflow(u32, left, offset, &result);
-                    cpu.r[rd] = result;
-
-                    cpu.cpsr.n.write(result >> 31 & 1 == 1);
-                    cpu.cpsr.z.write(result == 0);
-                    cpu.cpsr.c.write(didOverflow);
-                    cpu.cpsr.v.write(((left ^ result) & (offset ^ result)) >> 31 & 1 == 1);
-                },
-                0b11 => {
-                    // SUB
-                    const left = cpu.r[rd];
-                    const result = left -% offset;
-                    cpu.r[rd] = result;
-
-                    cpu.cpsr.n.write(result >> 31 & 1 == 1);
-                    cpu.cpsr.z.write(result == 0);
-                    cpu.cpsr.c.write(offset <= left);
-                    cpu.cpsr.v.write(((left ^ result) & (~offset ^ result)) >> 31 & 1 == 1);
+                    setLogicOpFlags(true, cpu, offset);
                 },
+                0b01 => cmp(cpu, cpu.r[rd], offset), // CMP
+                0b10 => cpu.r[rd] = add(true, cpu, cpu.r[rd], offset), // ADD
+                0b11 => cpu.r[rd] = sub(true, cpu, cpu.r[rd], offset), // SUB
             }
         }
     }.inner;

src/cpu/thumb/format5.zig

@@ -4,6 +4,8 @@ const Bus = @import("../../Bus.zig");
 const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
 const InstrFn = @import("../../cpu.zig").ThumbInstrFn;
 
+const cmp = @import("../arm/data_processing.zig").cmp;
+
 pub fn format5(comptime op: u2, comptime h1: u1, comptime h2: u1) InstrFn {
     return struct {
         fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void {
@@ -11,24 +13,14 @@ pub fn format5(comptime op: u2, comptime h1: u1, comptime h2: u1) InstrFn {
             const dst = @as(u4, h1) << 3 | (opcode & 0x7);
 
             switch (op) {
-                0b01 => {
-                    // CMP
-                    const left = cpu.r[dst];
-                    const right = cpu.r[src];
-                    const result = left -% right;
-
-                    cpu.cpsr.n.write(result >> 31 & 1 == 1);
-                    cpu.cpsr.z.write(result == 0);
-                    cpu.cpsr.c.write(right <= left);
-                    cpu.cpsr.v.write(((left ^ result) & (~right ^ result)) >> 31 & 1 == 1);
-                },
+                0b01 => cmp(cpu, cpu.r[dst], cpu.r[src]), // CMP
                 0b10 => cpu.r[dst] = cpu.r[src], // MOV
                 0b11 => {
                     // BX
                     cpu.cpsr.t.write(cpu.r[src] & 1 == 1);
                     cpu.r[15] = cpu.r[src] & 0xFFFF_FFFE;
                 },
-                else => std.debug.panic("[CPU] Op #{} is invalid for THUMB Format 5", .{op}),
+                else => std.debug.panic("[CPU|THUMB|Fmt5] {} is an invalid op", .{op}),
             }
         }
     }.inner;

src/cpu/thumb/format6.zig

@@ -0,0 +1,17 @@
+const std = @import("std");
+
+const Bus = @import("../../Bus.zig");
+const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
+const InstrFn = @import("../../cpu.zig").ThumbInstrFn;
+
+pub fn format6(comptime rd: u3) InstrFn {
+    return struct {
+        fn inner(cpu: *Arm7tdmi, bus: *Bus, opcode: u16) void {
+            // LDR
+            const offset = (opcode & 0xFF) << 2;
+
+            // FIXME: Should this overflow?
+            cpu.r[rd] = bus.read32((cpu.fakePC() & 0xFFFF_FFFC) + offset);
+        }
+    }.inner;
+}

src/main.zig

@@ -9,6 +9,7 @@ const Scheduler = @import("scheduler.zig").Scheduler;
 const Timer = std.time.Timer;
 const Thread = std.Thread;
 const Atomic = std.atomic.Atomic;
+const File = std.fs.File;
 
 const window_scale = 3;
 const gba_width = @import("ppu.zig").width;
@@ -48,14 +49,15 @@ pub fn main() anyerror!void {
     var cpu = Arm7tdmi.init(&scheduler, &bus);
     cpu.fastBoot();
 
+    var log_file: ?File = undefined;
     if (enable_logging) {
-        const file_name = if (is_binary) "zba.bin" else "zba.log";
-
+        const file_name: []const u8 = if (is_binary) "zba.bin" else "zba.log";
         const file = try std.fs.cwd().createFile(file_name, .{ .read = true });
-        defer file.close();
-
         cpu.useLogger(&file, is_binary);
+
+        log_file = file;
     }
+    defer if (log_file) |file| file.close();
 
     // Init Atomics
     var quit = Atomic(bool).init(false);
@@ -70,7 +72,7 @@ pub fn main() anyerror!void {
     defer SDL.SDL_Quit();
 
     var window = SDL.SDL_CreateWindow(
-        "Gameboy Advance Emulator",
+        "ZBA",
         SDL.SDL_WINDOWPOS_CENTERED,
         SDL.SDL_WINDOWPOS_CENTERED,
         gba_width * window_scale,
@@ -106,7 +108,7 @@ pub fn main() anyerror!void {
         SDL.SDL_RenderPresent(renderer);
 
         const fps = std.time.ns_per_s / timer.lap();
-        const title = std.fmt.bufPrint(&title_buf, "Gameboy Advance Emulator FPS: {d}", .{fps}) catch unreachable;
+        const title = std.fmt.bufPrint(&title_buf, "ZBA FPS: {d}", .{fps}) catch unreachable;
         SDL.SDL_SetWindowTitle(window, title.ptr);
     }