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660c8a2d62
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d5443d9c2f
11
src/Bus.zig
11
src/Bus.zig
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@ -64,7 +64,16 @@ pub fn attach(self: *Self, cpu: *Arm7tdmi) void {
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self.cpu = cpu;
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}
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pub inline fn isDmaRunning(self: *const Self) bool {
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pub fn handleDMATransfers(self: *Self) void {
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while (self.isDmaRunning()) {
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if (self.dma[1].step(self)) continue;
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if (self.dma[0].step(self)) continue;
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if (self.dma[2].step(self)) continue;
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if (self.dma[3].step(self)) continue;
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}
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}
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inline fn isDmaRunning(self: *const Self) bool {
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return self.dma[0].active or
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self.dma[1].active or
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self.dma[2].active or
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@ -263,12 +263,12 @@ pub const Apu = struct {
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if (@boolToInt(self.dma_cnt.chA_timer.read()) == tim_id) {
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self.chA.updateSample();
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if (self.chA.len() <= 15) cpu.bus.dma[1].requestSoundDma(0x0400_00A0);
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if (self.chA.len() <= 15) cpu.bus.dma[1].enableSoundDma(0x0400_00A0);
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}
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if (@boolToInt(self.dma_cnt.chB_timer.read()) == tim_id) {
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self.chB.updateSample();
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if (self.chB.len() <= 15) cpu.bus.dma[2].requestSoundDma(0x0400_00A4);
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if (self.chB.len() <= 15) cpu.bus.dma[2].enableSoundDma(0x0400_00A4);
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}
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}
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@ -2,7 +2,6 @@ const std = @import("std");
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const DmaControl = @import("io.zig").DmaControl;
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const Bus = @import("../Bus.zig");
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const Arm7tdmi = @import("../cpu.zig").Arm7tdmi;
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pub const DmaTuple = std.meta.Tuple(&[_]type{ DmaController(0), DmaController(1), DmaController(2), DmaController(3) });
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const log = std.log.scoped(.DmaTransfer);
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@ -99,35 +98,62 @@ fn DmaController(comptime id: u2) type {
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self.writeCntHigh(@truncate(u16, word >> 16));
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}
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pub fn step(self: *Self, cpu: *Arm7tdmi) bool {
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pub fn step(self: *Self, bus: *Bus) bool {
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if (!self.active) return false;
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const sad_adj = std.meta.intToEnum(Adjustment, self.cnt.sad_adj.read()) catch unreachable;
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const dad_adj = std.meta.intToEnum(Adjustment, self.cnt.dad_adj.read()) catch unreachable;
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const is_fifo = (self.id == 1 or self.id == 2) and self.cnt.start_timing.read() == 0b11;
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const sad_adj = Self.adjustment(self.cnt.sad_adj.read());
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const dad_adj = if (is_fifo) .Fixed else Self.adjustment(self.cnt.dad_adj.read());
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const transfer_type = is_fifo or self.cnt.transfer_type.read();
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// // if (is_fifo) {
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// // const offset = @sizeOf(u32);
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// // bus.write(u32, self._dad, bus.read(u32, self._sad));
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// // // TODO: Deduplicate
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// // switch (sad_adj) {
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// // .Increment => self._sad +%= offset,
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// // .Decrement => self._sad -%= offset,
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// // .Fixed => {},
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// // // TODO: Figure out correct behaviour on Illegal Source Addr Control Type
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// // .IncrementReload => std.debug.panic("panic(DmaTransfer): {} is an illegal src addr adjustment type", .{sad_adj}),
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// // }
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// // self._fifo_word_count -= 1;
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// // if (self._fifo_word_count == 0) {
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// // self._fifo_word_count = 4;
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// // self.active = false;
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// // }
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// // return true;
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// // }
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const transfer_type = self.cnt.transfer_type.read() or is_fifo;
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const offset: u32 = if (transfer_type) @sizeOf(u32) else @sizeOf(u16);
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if (transfer_type) {
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cpu.bus.write(u32, self._dad, cpu.bus.read(u32, self._sad));
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bus.write(u32, self._dad, bus.read(u32, self._sad));
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} else {
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cpu.bus.write(u16, self._dad, cpu.bus.read(u16, self._sad));
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bus.write(u16, self._dad, bus.read(u16, self._sad));
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}
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switch (sad_adj) {
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.Increment => self._sad +%= offset,
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.Decrement => self._sad -%= offset,
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// TODO: Is just ignoring this ok?
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.IncrementReload => log.err("{} is a prohibited adjustment on SAD", .{sad_adj}),
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.Fixed => {},
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// TODO: Figure out correct behaviour on Illegal Source Addr Control Type
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.IncrementReload => std.debug.panic("panic(DmaTransfer): {} is an illegal src addr adjustment type", .{sad_adj}),
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}
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if (!is_fifo) {
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switch (dad_adj) {
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.Increment, .IncrementReload => self._dad +%= offset,
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.Decrement => self._dad -%= offset,
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.Fixed => {},
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}
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}
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self._word_count -= 1;
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@ -136,15 +162,12 @@ fn DmaController(comptime id: u2) type {
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// If we're not repeating, Fire the IRQs and disable the DMA
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if (self.cnt.irq.read()) {
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switch (id) {
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0 => cpu.bus.io.irq.dma0.set(),
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1 => cpu.bus.io.irq.dma0.set(),
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2 => cpu.bus.io.irq.dma0.set(),
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3 => cpu.bus.io.irq.dma0.set(),
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0 => bus.io.irq.dma0.set(),
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1 => bus.io.irq.dma0.set(),
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2 => bus.io.irq.dma0.set(),
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3 => bus.io.irq.dma0.set(),
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}
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cpu.handleInterrupt();
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}
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self.cnt.enabled.unset();
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}
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@ -173,28 +196,21 @@ fn DmaController(comptime id: u2) type {
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if (self.cnt.repeat.read() and self.active) {
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self._word_count = if (self.word_count == 0) std.math.maxInt(@TypeOf(self._word_count)) else self.word_count;
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if (Self.adjustment(self.cnt.dad_adj.read()) == .IncrementReload) self._dad = self.dad;
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const dad_adj = std.meta.intToEnum(Adjustment, self.cnt.dad_adj.read()) catch unreachable;
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if (dad_adj == .IncrementReload) self._dad = self.dad;
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}
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}
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pub fn requestSoundDma(self: *Self, fifo_addr: u32) void {
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pub fn enableSoundDma(self: *Self, fifo_addr: u32) void {
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comptime std.debug.assert(id == 1 or id == 2);
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const is_enabled = self.cnt.enabled.read();
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const is_special = self.cnt.start_timing.read() == 0b11;
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const is_repeating = self.cnt.repeat.read();
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const is_fifo = self.dad == fifo_addr;
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if (is_enabled and is_special and is_repeating and is_fifo) {
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self._word_count = 4;
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self.cnt.transfer_type.set();
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if (self.cnt.enabled.read() and self.cnt.start_timing.read() == 0b11 and self.dad == fifo_addr) {
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self.active = true;
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self._word_count = 4;
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self.cnt.repeat.set();
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}
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}
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fn adjustment(idx: u2) Adjustment {
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return std.meta.intToEnum(Adjustment, idx) catch unreachable;
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}
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};
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}
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@ -267,15 +267,6 @@ pub const Arm7tdmi = struct {
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}
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}
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pub fn handleDMATransfers(self: *Self) void {
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while (self.bus.isDmaRunning()) {
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if (self.bus.dma[1].step(self)) continue;
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if (self.bus.dma[0].step(self)) continue;
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if (self.bus.dma[2].step(self)) continue;
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if (self.bus.dma[3].step(self)) continue;
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}
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}
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pub fn handleInterrupt(self: *Self) void {
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const should_handle = self.bus.io.ie.raw & self.bus.io.irq.raw;
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@ -48,7 +48,7 @@ pub fn runFrame(sched: *Scheduler, cpu: *Arm7tdmi) void {
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while (sched.tick < frame_end) {
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if (cpu.bus.io.haltcnt == .Halt) sched.tick += 1;
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if (cpu.bus.io.haltcnt == .Execute) cpu.step();
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cpu.handleDMATransfers();
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cpu.bus.handleDMATransfers();
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while (sched.tick >= sched.nextTimestamp()) {
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sched.handleEvent(cpu);
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