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paoda:april-fools
paoda:window
paoda:apu-things
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compare: paoda:9eb4f8f19136d27d140d63ee4c5a59b5a07da114
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paoda:apu-things

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2 changed files with 14 additions and 192 deletions
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202
src/core/Bus.zig
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@ -33,11 +33,6 @@ pub const fetch_timings: [2][0x10]u8 = [_][0x10]u8{
[_]u8{ 1, 1, 6, 1, 1, 2, 2, 1, 4, 4, 4, 4, 4, 4, 8, 8 }, // 32-bit
};
// Fastmem Related
const page_size = 1 * 0x400; // 1KiB
const address_space_size = 0x1000_0000;
const table_len = address_space_size / page_size;
const Self = @This();
pak: GamePak,
@ -53,17 +48,7 @@ io: Io,
cpu: *Arm7tdmi,
sched: *Scheduler,
read_table: *const [table_len]?*const anyopaque,
write_tables: [2]*const [table_len]?*anyopaque,
allocator: Allocator,
pub fn init(self: *Self, allocator: Allocator, sched: *Scheduler, cpu: *Arm7tdmi, paths: FilePaths) !void {
const tables = try allocator.alloc(?*anyopaque, 3 * table_len); // Allocate all tables
const read_table: *[table_len]?*const anyopaque = tables[0..table_len];
const left_write: *[table_len]?*anyopaque = tables[table_len .. 2 * table_len];
const right_write: *[table_len]?*anyopaque = tables[2 * table_len .. 3 * table_len];
self.* = .{
.pak = try GamePak.init(allocator, cpu, paths.rom, paths.save),
.bios = try Bios.init(allocator, paths.bios),
@ -76,20 +61,7 @@ pub fn init(self: *Self, allocator: Allocator, sched: *Scheduler, cpu: *Arm7tdmi
.io = Io.init(),
.cpu = cpu,
.sched = sched,
.read_table = read_table,
.write_tables = .{ left_write, right_write },
.allocator = allocator,
};
// read_table, write_tables, and *Self are not restricted to the lifetime
// of this init function so we can initialize our tables here
fillReadTable(self, read_table);
// Internal Display Memory behavious unusually on 8-bit reads
// so we have two different tables depending on whether there's an 8-bit read or not
fillWriteTable(u16, self, left_write); // T could also be u32 here
fillWriteTable(u8, self, right_write);
}
pub fn deinit(self: *Self) void {
@ -98,107 +70,9 @@ pub fn deinit(self: *Self) void {
self.pak.deinit();
self.bios.deinit();
self.ppu.deinit();
// This is so I can deallocate the original `allocator.alloc`. I have to re-make the type
// since I'm not keeping it around, This is very jank and bad though
// FIXME: please figure out another way
self.allocator.free(@ptrCast([*]const ?*anyopaque, self.write_tables[0][0..])[0 .. 3 * table_len]);
self.* = undefined;
}
fn fillReadTable(bus: *Self, table: *[table_len]?*const anyopaque) void {
const vramMirror = @import("ppu.zig").Vram.mirror;
for (table) |*ptr, i| {
const addr = page_size * i;
ptr.* = switch (addr) {
// General Internal Memory
0x0000_0000...0x0000_3FFF => null, // BIOS has it's own checks
0x0200_0000...0x02FF_FFFF => &bus.ewram.buf[addr & 0x3FFFF],
0x0300_0000...0x03FF_FFFF => &bus.iwram.buf[addr & 0x7FFF],
0x0400_0000...0x0400_03FF => null, // I/O
// Internal Display Memory
0x0500_0000...0x05FF_FFFF => &bus.ppu.palette.buf[addr & 0x3FF],
0x0600_0000...0x06FF_FFFF => &bus.ppu.vram.buf[vramMirror(addr)],
0x0700_0000...0x07FF_FFFF => &bus.ppu.oam.buf[addr & 0x3FF],
// External Memory (Game Pak)
0x0800_0000...0x0DFF_FFFF => fillTableExternalMemory(bus, addr),
0x0E00_0000...0x0FFF_FFFF => null, // SRAM
else => null,
};
}
}
fn fillWriteTable(comptime T: type, bus: *Self, table: *[table_len]?*const anyopaque) void {
comptime std.debug.assert(T == u32 or T == u16 or T == u8);
const vramMirror = @import("ppu.zig").Vram.mirror;
for (table) |*ptr, i| {
const addr = page_size * i;
ptr.* = switch (addr) {
// General Internal Memory
0x0000_0000...0x0000_3FFF => null, // BIOS has it's own checks
0x0200_0000...0x02FF_FFFF => &bus.ewram.buf[addr & 0x3FFFF],
0x0300_0000...0x03FF_FFFF => &bus.iwram.buf[addr & 0x7FFF],
0x0400_0000...0x0400_03FF => null, // I/O
// Internal Display Memory
// FIXME: Different table for different integer width writes?
0x0500_0000...0x05FF_FFFF => if (T != u8) &bus.ppu.palette.buf[addr & 0x3FF] else null,
0x0600_0000...0x06FF_FFFF => if (T != u8) &bus.ppu.vram.buf[vramMirror(addr)] else null,
0x0700_0000...0x07FF_FFFF => if (T != u8) &bus.ppu.oam.buf[addr & 0x3FF] else null,
// External Memory (Game Pak)
0x0800_0000...0x0DFF_FFFF => null, // ROM
0x0E00_0000...0x0FFF_FFFF => null, // SRAM
else => null,
};
}
}
fn fillTableExternalMemory(bus: *Self, addr: usize) ?*anyopaque {
// see `GamePak.zig` for more information about what conditions need to be true
// so that a simple pointer dereference isn't possible
const start_addr = addr;
const end_addr = addr + page_size;
const gpio_data = start_addr <= 0x0800_00C4 and 0x0800_00C4 < end_addr;
const gpio_direction = start_addr <= 0x0800_00C6 and 0x0800_00C6 < end_addr;
const gpio_control = start_addr <= 0x0800_00C8 and 0x0800_00C8 < end_addr;
if (bus.pak.gpio.device.kind != .None and (gpio_data or gpio_direction or gpio_control)) {
// We found a GPIO device, and this page a GPIO register. We want to handle this in slowmem
return null;
}
if (bus.pak.backup.kind == .Eeprom) {
if (bus.pak.buf.len > 0x100_000) {
// We are using a "large" EEPROM which means that if the below check is true
// this page has an address that's reserved for the EEPROM and therefore must
// be handled in slowmem
if (addr & 0x1FF_FFFF > 0x1FF_FEFF) return null;
} else {
// We are using a "small" EEPROM which means that if the below check is true
// (that is, we're in the 0xD address page) then we must handle at least one
// address in this page in slowmem
if (@truncate(u4, addr >> 24) == 0xD) return null;
}
}
// Finally, the GamePak has some unique behaviour for reads past the end of the ROM,
// so those will be handled by slowmem as well
const masked_addr = addr & 0x1FF_FFFF;
if (masked_addr >= bus.pak.buf.len) return null;
return &bus.pak.buf[masked_addr];
}
// TODO: Take advantage of fastmem here too?
pub fn dbgRead(self: *const Self, comptime T: type, unaligned_address: u32) T {
const page = @truncate(u8, unaligned_address >> 24);
const address = forceAlign(T, unaligned_address);
@ -303,36 +177,11 @@ fn openBus(self: *const Self, comptime T: type, address: u32) T {
}
pub fn read(self: *Self, comptime T: type, unaligned_address: u32) T {
const bits = @typeInfo(std.math.IntFittingRange(0, page_size - 1)).Int.bits;
const page = unaligned_address >> bits;
const offset = unaligned_address & (page_size - 1);
// whether or not we do this in slowmem or fastmem, we should advance the scheduler
self.sched.tick += timings[@boolToInt(T == u32)][@truncate(u4, page)];
// We're doing some serious out-of-bounds open-bus reads
if (page > table_len) return self.slowRead(T, unaligned_address);
if (self.read_table[page]) |some_ptr| {
// We have a pointer to a page, cast the pointer to it's underlying type
const Ptr = [*]const T;
const alignment = @alignOf(std.meta.Child(Ptr));
const ptr = @ptrCast(Ptr, @alignCast(alignment, some_ptr));
// Note: We don't check array length, since we force align the
// lower bits of the address as the GBA would
return ptr[forceAlign(T, offset) / @sizeOf(T)];
}
return self.slowRead(T, unaligned_address);
}
fn slowRead(self: *Self, comptime T: type, unaligned_address: u32) T {
@setCold(true);
const page = @truncate(u8, unaligned_address >> 24);
const address = forceAlign(T, unaligned_address);
self.sched.tick += timings[@boolToInt(T == u32)][@truncate(u4, page)];
return switch (page) {
// General Internal Memory
0x00 => blk: {
@ -341,14 +190,14 @@ fn slowRead(self: *Self, comptime T: type, unaligned_address: u32) T {
break :blk self.openBus(T, address);
},
0x02 => unreachable, // completely handled by fastmeme
0x03 => unreachable, // completely handled by fastmeme
0x02 => self.ewram.read(T, address),
0x03 => self.iwram.read(T, address),
0x04 => self.readIo(T, address),
// Internal Display Memory
0x05 => unreachable, // completely handled by fastmeme
0x06 => unreachable, // completely handled by fastmeme
0x07 => unreachable, // completely handled by fastmeme
0x05 => self.ppu.palette.read(T, address),
0x06 => self.ppu.vram.read(T, address),
0x07 => self.ppu.oam.read(T, address),
// External Memory (Game Pak)
0x08...0x0D => self.pak.read(T, address),
@ -369,49 +218,22 @@ fn slowRead(self: *Self, comptime T: type, unaligned_address: u32) T {
}
pub fn write(self: *Self, comptime T: type, unaligned_address: u32, value: T) void {
const bits = @typeInfo(std.math.IntFittingRange(0, page_size - 1)).Int.bits;
const page = unaligned_address >> bits;
const offset = unaligned_address & (page_size - 1);
// whether or not we do this in slowmem or fastmem, we should advance the scheduler
self.sched.tick += timings[@boolToInt(T == u32)][@truncate(u4, page)];
// We're doing some serious out-of-bounds open-bus writes, they do nothing though
if (page > table_len) return;
if (self.write_tables[if (T == u8) 1 else 0][page]) |some_ptr| {
// We have a pointer to a page, cast the pointer to it's underlying type
const Ptr = [*]T;
const alignment = @alignOf(std.meta.Child(Ptr));
const ptr = @ptrCast(Ptr, @alignCast(alignment, some_ptr));
// Note: We don't check array length, since we force align the
// lower bits of the address as the GBA would
ptr[forceAlign(T, offset) / @sizeOf(T)] = value;
} else {
// we can return early if this is an 8-bit OAM write
if (T == u8 and @truncate(u8, unaligned_address) == 0x07) return;
self.slowWrite(T, unaligned_address, value);
}
}
pub fn slowWrite(self: *Self, comptime T: type, unaligned_address: u32, value: T) void {
// @setCold(true);
const page = @truncate(u8, unaligned_address >> 24);
const address = forceAlign(T, unaligned_address);
self.sched.tick += timings[@boolToInt(T == u32)][@truncate(u4, page)];
switch (page) {
// General Internal Memory
0x00 => self.bios.write(T, address, value),
0x02 => unreachable, // completely handled by fastmem
0x03 => unreachable, // completely handled by fastmem
0x02 => self.ewram.write(T, address, value),
0x03 => self.iwram.write(T, address, value),
0x04 => io.write(self, T, address, value),
// Internal Display Memory
0x05 => self.ppu.palette.write(T, address, value),
0x06 => self.ppu.vram.write(T, self.ppu.dispcnt, address, value),
0x07 => unreachable, // completely handled by fastmem
0x07 => self.ppu.oam.write(T, address, value),
// External Memory (Game Pak)
0x08...0x0D => self.pak.write(T, self.dma[3].word_count, address, value),

4
src/core/ppu.zig
View File

@ -882,7 +882,7 @@ const Palette = struct {
}
};
pub const Vram = struct {
const Vram = struct {
const vram_size = 0x18000;
const Self = @This();
@ -933,7 +933,7 @@ pub const Vram = struct {
}
}
pub fn mirror(address: usize) usize {
fn mirror(address: usize) usize {
// Mirrored in steps of 128K (64K + 32K + 32K) (abcc)
const addr = address & 0x1FFFF;