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base: paoda:540fbf739aa1f70667fc596a18b3c24d66f8530b
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paoda:main
paoda:april-fools
paoda:window
paoda:apu-things
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compare: paoda:997dc1314c9923a45059c54a9e23b649195b7d66
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paoda:main
paoda:april-fools
paoda:window
paoda:apu-things

No commits in common. "540fbf739aa1f70667fc596a18b3c24d66f8530b" and "997dc1314c9923a45059c54a9e23b649195b7d66" have entirely different histories.
540fbf739a ... 997dc1314c

2 changed files with 11 additions and 13 deletions
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22
src/cpu.zig
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@ -65,8 +65,8 @@ pub const Arm7tdmi = struct {
.Supervisor => 1, .Supervisor => 1,
.Abort => 2, .Abort => 2,
.Undefined => 3, .Undefined => 3,
.Irq => 4, .IRQ => 4,
.Fiq => 5, .FIQ => 5,
}; };
} }
@ -75,8 +75,8 @@ pub const Arm7tdmi = struct {
.Supervisor => 0, .Supervisor => 0,
.Abort => 1, .Abort => 1,
.Undefined => 2, .Undefined => 2,
.Irq => 3, .IRQ => 3,
.Fiq => 4, .FIQ => 4,
else => std.debug.panic("{} does not have a SPSR Register", .{mode}), else => std.debug.panic("{} does not have a SPSR Register", .{mode}),
}; };
} }
@ -110,7 +110,7 @@ pub const Arm7tdmi = struct {
// Bank R8 -> r12 // Bank R8 -> r12
var r: usize = 8; var r: usize = 8;
while (r <= 12) : (r += 1) { while (r <= 12) : (r += 1) {
self.banked_fiq[(r - 8) * 2 + if (now == .Fiq) @as(usize, 1) else 0] = self.r[r]; self.banked_fiq[(r - 8) * 2 + if (now == .FIQ) @as(usize, 1) else 0] = self.r[r];
} }
// Bank r13, r14, SPSR // Bank r13, r14, SPSR
@ -129,7 +129,7 @@ pub const Arm7tdmi = struct {
// Grab R8 -> R12 // Grab R8 -> R12
r = 8; r = 8;
while (r <= 12) : (r += 1) { while (r <= 12) : (r += 1) {
self.r[r] = self.banked_fiq[(r - 8) * 2 + if (next == .Fiq) @as(usize, 1) else 0]; self.r[r] = self.banked_fiq[(r - 8) * 2 + if (next == .FIQ) @as(usize, 1) else 0];
} }
// Grab r13, r14, SPSR // Grab r13, r14, SPSR
@ -149,7 +149,7 @@ pub const Arm7tdmi = struct {
self.cpsr.mode.write(@enumToInt(next)); self.cpsr.mode.write(@enumToInt(next));
} }
pub fn fastBoot(self: *Self) void { pub fn skipBios(self: *Self) void {
self.r[0] = 0x08000000; self.r[0] = 0x08000000;
self.r[1] = 0x000000EA; self.r[1] = 0x000000EA;
// GPRs 2 -> 12 *should* already be 0 initialized // GPRs 2 -> 12 *should* already be 0 initialized
@ -157,9 +157,7 @@ pub const Arm7tdmi = struct {
self.r[14] = 0x0000_0000; self.r[14] = 0x0000_0000;
self.r[15] = 0x0800_0000; self.r[15] = 0x0800_0000;
// Set r13_irq and r14_svc to their respective values // TODO: Set sp_irq = 0x0300_7FA0, sp_svc = 0x0300_7FE0
self.banked_r[bankedIdx(.Irq) * 2 + 0] = 0x0300_7FA0;
self.banked_r[bankedIdx(.Supervisor) * 2 + 0] = 0x0300_7FE0;
self.cpsr.raw = 0x6000001F; self.cpsr.raw = 0x6000001F;
} }
@ -376,8 +374,8 @@ pub const PSR = extern union {
const Mode = enum(u5) { const Mode = enum(u5) {
User = 0b10000, User = 0b10000,
Fiq = 0b10001, FIQ = 0b10001,
Irq = 0b10010, IRQ = 0b10010,
Supervisor = 0b10011, Supervisor = 0b10011,
Abort = 0b10111, Abort = 0b10111,
Undefined = 0b11011, Undefined = 0b11011,

2
src/main.zig
View File

@ -41,7 +41,7 @@ pub fn main() anyerror!void {
defer bus.deinit(); defer bus.deinit();
var cpu = Arm7tdmi.init(&scheduler, &bus); var cpu = Arm7tdmi.init(&scheduler, &bus);
cpu.fastBoot(); cpu.skipBios();
// Initialize SDL // Initialize SDL
const status = SDL.SDL_Init(SDL.SDL_INIT_VIDEO | SDL.SDL_INIT_EVENTS | SDL.SDL_INIT_AUDIO); const status = SDL.SDL_Init(SDL.SDL_INIT_VIDEO | SDL.SDL_INIT_EVENTS | SDL.SDL_INIT_AUDIO);