fix: 8-bit writes to WIN PPU registers

Advance Wars depends on these registers similar to Mario Kart's 8-bit
writes to Affine Background registers:

lib/SDL.zig

@@ -1 +1 @@
-Subproject commit f3d7620f85929bca8b7ce2be2fa8a938e164f720
+Subproject commit 401c50ff3d0b83ad4bd89caf580ce1bd90fb5618

lib/known-folders

@@ -1 +1 @@
-Subproject commit 9db1b99219c767d5e24994b1525273fe4031e464
+Subproject commit 24845b0103e611c108d6bc334231c464e699742c

lib/zig-clap

@@ -1 +1 @@
-Subproject commit 996821a3e1f186c9e5cdfd971d742c9815ea590e
+Subproject commit 1c09e0dc31918dd716b1032ad3e1d1c080cbbff1

src/Gui.zig

@@ -8,12 +8,12 @@ const Scheduler = @import("core/scheduler.zig").Scheduler;
 const FpsTracker = @import("core/util.zig").FpsTracker;
 
 const pitch = @import("core/ppu.zig").framebuf_pitch;
+const scale = @import("core/emu.zig").win_scale;
 
 const emu = @import("core/emu.zig");
 const asString = @import("core/util.zig").asString;
 const log = std.log.scoped(.GUI);
 
-const scale = 4;
 const default_title: []const u8 = "ZBA";
 
 window: *SDL.SDL_Window,

src/core/Bus.zig

@@ -77,70 +77,29 @@ pub fn attach(self: *Self, cpu: *Arm7tdmi) void {
     self.cpu = cpu;
 }
 
-pub fn debugRead(self: *const Self, comptime T: type, address: u32) T {
+pub fn dbgRead(self: *const Self, comptime T: type, address: u32) T {
-    const cached = self.sched.tick;
-    defer self.sched.tick = cached;
-
-    // FIXME: This is bad but it's a debug read so I don't care that much?
-    const this = @intToPtr(*Self, @ptrToInt(self));
-
-    return this.read(T, address);
-}
-
-fn readOpenBus(self: *const Self, comptime T: type, address: u32) T {
-    const r15 = self.cpu.?.r[15];
-
-    const word = if (self.cpu.?.cpsr.t.read()) blk: {
-        const page = @truncate(u8, r15 >> 24);
-
-        switch (page) {
-            // EWRAM, PALRAM, VRAM, and Game ROM (16-bit)
-            0x02, 0x05, 0x06, 0x08...0x0D => {
-                const halfword = self.debugRead(u16, r15 + 2);
-                break :blk @as(u32, halfword) << 16 | halfword;
-            },
-            // BIOS or OAM (32-bit)
-            0x00, 0x07 => {
-                const offset: u32 = if (address & 3 == 0b00) 2 else 0;
-                break :blk @as(u32, self.debugRead(u16, (r15 + 2) + offset)) << 16 | self.debugRead(u16, r15 + offset);
-            },
-            // IWRAM (16-bit but special)
-            0x03 => {
-                const offset: u32 = if (address & 3 == 0b00) 2 else 0;
-                break :blk @as(u32, self.debugRead(u16, (r15 + 2) - offset)) << 16 | self.debugRead(u16, r15 + offset);
-            },
-            else => unreachable,
-        }
-    } else self.debugRead(u32, r15 + 4);
-
-    return @truncate(T, rotr(u32, word, 8 * (address & 3)));
-}
-
-fn readBios(self: *Self, comptime T: type, address: u32) T {
-    if (address < Bios.size) return self.bios.checkedRead(T, self.cpu.?.r[15], alignAddress(T, address));
-
-    return self.readOpenBus(T, address);
-}
-
-pub fn read(self: *Self, comptime T: type, address: u32) T {
     const page = @truncate(u8, address >> 24);
-    const align_addr = alignAddress(T, address);
+    const aligned_addr = forceAlign(T, address);
-    defer self.sched.tick += timings[@boolToInt(T == u32)][@truncate(u4, page)];
 
     return switch (page) {
         // General Internal Memory
-        0x00 => self.readBios(T, address),
+        0x00 => blk: {
-        0x02 => self.ewram.read(T, align_addr),
+            if (address < Bios.size)
-        0x03 => self.iwram.read(T, align_addr),
+                break :blk self.bios.dbgRead(T, self.cpu.?.r[15], aligned_addr);
-        0x04 => io.read(self, T, align_addr),
+
+            break :blk self.readOpenBus(T, address);
+        },
+        0x02 => self.ewram.read(T, aligned_addr),
+        0x03 => self.iwram.read(T, aligned_addr),
+        0x04 => io.read(self, T, aligned_addr),
 
         // Internal Display Memory
-        0x05 => self.ppu.palette.read(T, align_addr),
+        0x05 => self.ppu.palette.read(T, aligned_addr),
-        0x06 => self.ppu.vram.read(T, align_addr),
+        0x06 => self.ppu.vram.read(T, aligned_addr),
-        0x07 => self.ppu.oam.read(T, align_addr),
+        0x07 => self.ppu.oam.read(T, aligned_addr),
 
         // External Memory (Game Pak)
-        0x08...0x0D => self.pak.read(T, align_addr),
+        0x08...0x0D => self.pak.dbgRead(T, aligned_addr),
         0x0E...0x0F => blk: {
             const value = self.pak.backup.read(address);
 
@@ -153,29 +112,100 @@ pub fn read(self: *Self, comptime T: type, address: u32) T {
 
             break :blk @as(T, value) * multiplier;
         },
-        else => readOpenBus(self, T, address),
+        else => self.readOpenBus(T, address),
+    };
+}
+
+fn readOpenBus(self: *const Self, comptime T: type, address: u32) T {
+    const r15 = self.cpu.?.r[15];
+
+    const word = if (self.cpu.?.cpsr.t.read()) blk: {
+        const page = @truncate(u8, r15 >> 24);
+
+        switch (page) {
+            // EWRAM, PALRAM, VRAM, and Game ROM (16-bit)
+            0x02, 0x05, 0x06, 0x08...0x0D => {
+                const halfword = self.dbgRead(u16, r15 + 2);
+                break :blk @as(u32, halfword) << 16 | halfword;
+            },
+            // BIOS or OAM (32-bit)
+            0x00, 0x07 => {
+                const offset: u32 = if (address & 3 == 0b00) 2 else 0;
+                break :blk @as(u32, self.dbgRead(u16, (r15 + 2) + offset)) << 16 | self.dbgRead(u16, r15 + offset);
+            },
+            // IWRAM (16-bit but special)
+            0x03 => {
+                const offset: u32 = if (address & 3 == 0b00) 2 else 0;
+                break :blk @as(u32, self.dbgRead(u16, (r15 + 2) - offset)) << 16 | self.dbgRead(u16, r15 + offset);
+            },
+            else => unreachable,
+        }
+    } else self.dbgRead(u32, r15 + 4);
+
+    return @truncate(T, rotr(u32, word, 8 * (address & 3)));
+}
+
+pub fn read(self: *Self, comptime T: type, address: u32) T {
+    const page = @truncate(u8, address >> 24);
+    const aligned_addr = forceAlign(T, address);
+
+    self.sched.tick += timings[@boolToInt(T == u32)][@truncate(u4, page)];
+
+    return switch (page) {
+        // General Internal Memory
+        0x00 => blk: {
+            if (address < Bios.size)
+                break :blk self.bios.read(T, self.cpu.?.r[15], aligned_addr);
+
+            break :blk self.readOpenBus(T, address);
+        },
+        0x02 => self.ewram.read(T, aligned_addr),
+        0x03 => self.iwram.read(T, aligned_addr),
+        0x04 => io.read(self, T, aligned_addr),
+
+        // Internal Display Memory
+        0x05 => self.ppu.palette.read(T, aligned_addr),
+        0x06 => self.ppu.vram.read(T, aligned_addr),
+        0x07 => self.ppu.oam.read(T, aligned_addr),
+
+        // External Memory (Game Pak)
+        0x08...0x0D => self.pak.read(T, aligned_addr),
+        0x0E...0x0F => blk: {
+            const value = self.pak.backup.read(address);
+
+            const multiplier = switch (T) {
+                u32 => 0x01010101,
+                u16 => 0x0101,
+                u8 => 1,
+                else => @compileError("Backup: Unsupported read width"),
+            };
+
+            break :blk @as(T, value) * multiplier;
+        },
+        else => self.readOpenBus(T, address),
     };
 }
 
 pub fn write(self: *Self, comptime T: type, address: u32, value: T) void {
     const page = @truncate(u8, address >> 24);
-    const align_addr = alignAddress(T, address);
+    const aligned_addr = forceAlign(T, address);
-    defer self.sched.tick += timings[@boolToInt(T == u32)][@truncate(u4, page)];
+
+    self.sched.tick += timings[@boolToInt(T == u32)][@truncate(u4, page)];
 
     switch (page) {
         // General Internal Memory
-        0x00 => self.bios.write(T, align_addr, value),
+        0x00 => self.bios.write(T, aligned_addr, value),
-        0x02 => self.ewram.write(T, align_addr, value),
+        0x02 => self.ewram.write(T, aligned_addr, value),
-        0x03 => self.iwram.write(T, align_addr, value),
+        0x03 => self.iwram.write(T, aligned_addr, value),
-        0x04 => io.write(self, T, align_addr, value),
+        0x04 => io.write(self, T, aligned_addr, value),
 
         // Internal Display Memory
-        0x05 => self.ppu.palette.write(T, align_addr, value),
+        0x05 => self.ppu.palette.write(T, aligned_addr, value),
-        0x06 => self.ppu.vram.write(T, self.ppu.dispcnt, align_addr, value),
+        0x06 => self.ppu.vram.write(T, self.ppu.dispcnt, aligned_addr, value),
-        0x07 => self.ppu.oam.write(T, align_addr, value),
+        0x07 => self.ppu.oam.write(T, aligned_addr, value),
 
         // External Memory (Game Pak)
-        0x08...0x0D => self.pak.write(T, self.dma[3].word_count, align_addr, value),
+        0x08...0x0D => self.pak.write(T, self.dma[3].word_count, aligned_addr, value),
         0x0E...0x0F => {
             const rotate_by = switch (T) {
                 u32 => address & 3,
@@ -190,7 +220,7 @@ pub fn write(self: *Self, comptime T: type, address: u32, value: T) void {
     }
 }
 
-fn alignAddress(comptime T: type, address: u32) u32 {
+fn forceAlign(comptime T: type, address: u32) u32 {
     return switch (T) {
         u32 => address & 0xFFFF_FFFC,
         u16 => address & 0xFFFF_FFFE,

src/core/bus/Bios.zig

@@ -31,17 +31,22 @@ pub fn deinit(self: Self) void {
     if (self.buf) |buf| self.alloc.free(buf);
 }
 
-pub fn checkedRead(self: *Self, comptime T: type, r15: u32, addr: u32) T {
+pub fn read(self: *Self, comptime T: type, r15: u32, addr: u32) T {
     if (r15 < Self.size) {
         self.addr_latch = addr;
-        return self.read(T, addr);
+        return self.uncheckedRead(T, addr);
     }
 
     log.debug("Rejected read since r15=0x{X:0>8}", .{r15});
-    return @truncate(T, self.read(T, self.addr_latch + 8));
+    return @truncate(T, self.uncheckedRead(T, self.addr_latch + 8));
 }
 
-fn read(self: *const Self, comptime T: type, addr: u32) T {
+pub fn dbgRead(self: *const Self, comptime T: type, r15: u32, addr: u32) T {
+    if (r15 < Self.size) return self.uncheckedRead(T, addr);
+    return @truncate(T, self.uncheckedRead(T, self.addr_latch + 8));
+}
+
+fn uncheckedRead(self: *const Self, comptime T: type, addr: u32) T {
     if (self.buf) |buf| {
         return switch (T) {
             u32, u16, u8 => std.mem.readIntSliceLittle(T, buf[addr..][0..@sizeOf(T)]),

src/core/bus/GamePak.zig

@@ -90,6 +90,33 @@ pub fn read(self: *Self, comptime T: type, address: u32) T {
     };
 }
 
+pub fn dbgRead(self: *const Self, comptime T: type, address: u32) T {
+    const addr = address & 0x1FF_FFFF;
+
+    if (self.backup.kind == .Eeprom) {
+        if (self.isLarge()) {
+            // Addresses 0x1FF_FF00 to 0x1FF_FFFF are reserved from EEPROM accesses if
+            // * Backup type is EEPROM
+            // * Large ROM (Size is greater than 16MB)
+            if (addr > 0x1FF_FEFF)
+                return self.backup.eeprom.dbgRead();
+        } else {
+            // Addresses 0x0D00_0000 to 0x0DFF_FFFF are reserved for EEPROM accesses if
+            // * Backup type is EEPROM
+            // * Small ROM (less than 16MB)
+            if (@truncate(u8, address >> 24) == 0x0D)
+                return self.backup.eeprom.dbgRead();
+        }
+    }
+
+    return switch (T) {
+        u32 => (@as(T, self.get(addr + 3)) << 24) | (@as(T, self.get(addr + 2)) << 16) | (@as(T, self.get(addr + 1)) << 8) | (@as(T, self.get(addr))),
+        u16 => (@as(T, self.get(addr + 1)) << 8) | @as(T, self.get(addr)),
+        u8 => self.get(addr),
+        else => @compileError("GamePak: Unsupported read width"),
+    };
+}
+
 pub fn write(self: *Self, comptime T: type, word_count: u16, address: u32, value: T) void {
     const addr = address & 0x1FF_FFFF;
 

src/core/bus/backup.zig

@@ -340,6 +340,10 @@ const Eeprom = struct {
         return self.reader.read();
     }
 
+    pub fn dbgRead(self: *const Self) u1 {
+        return self.reader.dbgRead();
+    }
+
     pub fn write(self: *Self, word_count: u16, buf: *[]u8, bit: u1) void {
         if (self.guessKind(word_count)) |found| {
             log.info("EEPROM Kind: {}", .{found});
@@ -492,6 +496,19 @@ const Eeprom = struct {
 
             return bit;
         }
+
+        fn dbgRead(self: *const This) u1 {
+            if (!self.enabled) return 1;
+
+            const bit = if (self.i < 4) blk: {
+                break :blk 0;
+            } else blk: {
+                const idx = @intCast(u6, 63 - (self.i - 4));
+                break :blk @truncate(u1, self.data >> idx);
+            };
+
+            return bit;
+        }
     };
 
     const Writer = struct {

src/core/bus/io.zig

@@ -302,6 +302,14 @@ pub fn write(bus: *Bus, comptime T: type, address: u32, value: T) void {
             0x0400_0009 => bus.ppu.bg[0].cnt.raw = (@as(u16, value) << 8) | (bus.ppu.bg[0].cnt.raw & 0xFF),
             0x0400_000A => bus.ppu.bg[1].cnt.raw = (bus.ppu.bg[1].cnt.raw & 0xFF00) | value,
             0x0400_000B => bus.ppu.bg[1].cnt.raw = (@as(u16, value) << 8) | (bus.ppu.bg[1].cnt.raw & 0xFF),
+            0x0400_0040 => bus.ppu.win.h[0].set(.Lo, value),
+            0x0400_0041 => bus.ppu.win.h[0].set(.Hi, value),
+            0x0400_0042 => bus.ppu.win.h[1].set(.Lo, value),
+            0x0400_0043 => bus.ppu.win.h[1].set(.Hi, value),
+            0x0400_0044 => bus.ppu.win.v[0].set(.Lo, value),
+            0x0400_0045 => bus.ppu.win.v[0].set(.Hi, value),
+            0x0400_0046 => bus.ppu.win.v[1].set(.Lo, value),
+            0x0400_0047 => bus.ppu.win.v[1].set(.Hi, value),
             0x0400_0048 => bus.ppu.win.setInL(value),
             0x0400_0049 => bus.ppu.win.setInH(value),
             0x0400_004A => bus.ppu.win.setOutL(value),
@@ -464,18 +472,38 @@ pub const BldY = extern union {
     raw: u16,
 };
 
+const u8WriteKind = enum { Hi, Lo };
+
 /// Write-only
 pub const WinH = extern union {
+    const Self = @This();
+
     x2: Bitfield(u16, 0, 8),
     x1: Bitfield(u16, 8, 8),
     raw: u16,
+
+    pub fn set(self: *Self, comptime K: u8WriteKind, value: u8) void {
+        self.raw = switch (K) {
+            .Hi => (@as(u16, value) << 8) | self.raw & 0xFF,
+            .Lo => (self.raw & 0xFF00) | value,
+        };
+    }
 };
 
 /// Write-only
 pub const WinV = extern union {
+    const Self = @This();
+
     y2: Bitfield(u16, 0, 8),
     y1: Bitfield(u16, 8, 8),
     raw: u16,
+
+    pub fn set(self: *Self, comptime K: u8WriteKind, value: u8) void {
+        self.raw = switch (K) {
+            .Hi => (@as(u16, value) << 8) | self.raw & 0xFF,
+            .Lo => (self.raw & 0xFF00) | value,
+        };
+    }
 };
 
 pub const WinIn = extern union {

src/core/cpu.zig

@@ -520,11 +520,11 @@ pub const Arm7tdmi = struct {
         prettyPrintPsr(&self.spsr);
 
         if (self.cpsr.t.read()) {
-            const opcode = self.bus.debugRead(u16, self.r[15] - 4);
+            const opcode = self.bus.dbgRead(u16, self.r[15] - 4);
             const id = thumbIdx(opcode);
             std.debug.print("opcode: ID: 0x{b:0>10} 0x{X:0>4}\n", .{ id, opcode });
         } else {
-            const opcode = self.bus.debugRead(u32, self.r[15] - 4);
+            const opcode = self.bus.dbgRead(u32, self.r[15] - 4);
             const id = armIdx(opcode);
             std.debug.print("opcode: ID: 0x{X:0>3} 0x{X:0>8}\n", .{ id, opcode });
         }
@@ -590,7 +590,7 @@ pub const Arm7tdmi = struct {
         if (self.cpsr.t.read()) {
             if (opcode >> 11 == 0x1E) {
                 // Instruction 1 of a BL Opcode, print in ARM mode
-                const other_half = self.bus.debugRead(u16, self.r[15]);
+                const other_half = self.bus.dbgRead(u16, self.r[15]);
                 const bl_opcode = @as(u32, opcode) << 16 | other_half;
 
                 log_str = try std.fmt.bufPrint(&buf, arm_fmt, .{ r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r13, r14, r15, c_psr, bl_opcode });

src/core/emu.zig

@@ -12,9 +12,11 @@ const Thread = std.Thread;
 const Atomic = std.atomic.Atomic;
 const Allocator = std.mem.Allocator;
 
-const sync_audio = false;
+// TODO: Move these to a TOML File
-const sync_video: RunKind = .UnlimitedFPS;
+const sync_audio = true; // Enable Audio Sync
-pub const cpu_logging = false;
+const sync_video: RunKind = .LimitedFPS; // Configure Video Sync
+pub const win_scale = 3; // 1x, 2x, 3x, etc. Window Scaling
+pub const cpu_logging = false; // Enable detailed CPU logging
 
 // 228 Lines which consist of 308 dots (which are 4 cycles long)
 const cycles_per_frame: u64 = 228 * (308 * 4); //280896

src/core/util.zig

@@ -137,7 +137,7 @@ pub const Logger = struct {
         if (arm7tdmi.cpsr.t.read()) {
             if (opcode >> 11 == 0x1E) {
                 // Instruction 1 of a BL Opcode, print in ARM mode
-                const low = arm7tdmi.bus.debugRead(u16, arm7tdmi.r[15]);
+                const low = arm7tdmi.bus.dbgRead(u16, arm7tdmi.r[15]);
                 const bl_opcode = @as(u32, opcode) << 16 | low;
 
                 self.print(arm_fmt, Self.fmtArgs(arm7tdmi, bl_opcode)) catch @panic("failed to write to log file");