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No commits in common. "4ed4f8e1435e20f88865aaa01d0724ad48be8f5f" and "ee1c0bb3132b33b2b2e5b5f3cc85069ccf6de3bb" have entirely different histories.

4 changed files with 75 additions and 78 deletions

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@ -40,18 +40,61 @@ pub const Backup = struct {
None, None,
}; };
pub fn read(self: *const Self, address: u32) u8 { pub fn read(self: *const Self, address: usize) u8 {
const addr = address & 0xFFFF;
switch (self.kind) { switch (self.kind) {
.Flash, .Flash1M => return self.flash.read(self.buf, address), .Flash => {
.Sram => return self.buf[address & 0x7FFF], // 32K SRAM chip is mirrored switch (addr) {
0x0000 => if (self.flash.id_mode) return 0x32, // Panasonic manufacturer ID
0x0001 => if (self.flash.id_mode) return 0x1B, // Panasonic device ID
else => {},
}
return self.flash.read(self.buf, addr);
},
.Flash1M => {
switch (addr) {
0x0000 => if (self.flash.id_mode) return 0x62, // Sanyo manufacturer ID
0x0001 => if (self.flash.id_mode) return 0x13, // Sanyo device ID
else => {},
}
return self.flash.read(self.buf, addr);
},
.Sram => return self.buf[addr & 0x7FFF], // 32K SRAM chip is mirrored
.None, .Eeprom => return 0xFF, .None, .Eeprom => return 0xFF,
} }
} }
pub fn write(self: *Self, address: u32, value: u8) void { pub fn write(self: *Self, address: usize, byte: u8) void {
const addr = address & 0xFFFF;
switch (self.kind) { switch (self.kind) {
.Flash, .Flash1M => self.flash.write(self.buf, address, value), .Flash, .Flash1M => {
.Sram => self.buf[address & 0x7FFF] = value, if (self.flash.prep_write) return self.flash.write(self.buf, addr, byte);
if (self.flash.shouldEraseSector(addr, byte)) return self.flash.erase(self.buf, addr);
switch (addr) {
0x0000 => if (self.kind == .Flash1M and self.flash.set_bank) {
self.flash.bank = @truncate(u1, byte);
},
0x5555 => {
if (self.flash.state == .Command) {
self.flash.handleCommand(self.buf, byte);
} else if (byte == 0xAA and self.flash.state == .Ready) {
self.flash.state = .Set;
} else if (byte == 0xF0) {
self.flash.state = .Ready;
}
},
0x2AAA => if (byte == 0x55 and self.flash.state == .Set) {
self.flash.state = .Command;
},
else => {},
}
},
.Sram => self.buf[addr & 0x7FFF] = byte,
.None, .Eeprom => {}, .None, .Eeprom => {},
} }
} }
@ -75,7 +118,7 @@ pub const Backup = struct {
.kind = kind, .kind = kind,
.title = title, .title = title,
.save_path = path, .save_path = path,
.flash = try Flash.create(if (kind == .Flash1M) .Flash1M else .Flash), .flash = Flash.create(),
.eeprom = Eeprom.create(allocator), .eeprom = Eeprom.create(allocator),
}; };

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@ -3,83 +3,42 @@ const std = @import("std");
const Self = @This(); const Self = @This();
state: State, state: State,
kind: Kind,
bank: u1,
id_mode: bool, id_mode: bool,
set_bank: bool, set_bank: bool,
prep_erase: bool, prep_erase: bool,
prep_write: bool, prep_write: bool,
const Kind = enum { Flash, Flash1M }; bank: u1,
const State = enum { Ready, Set, Command };
pub fn read(self: *const Self, buf: []u8, address: u32) u8 { const State = enum {
const addr = address & 0xFFFF; Ready,
Set,
Command,
};
if (self.kind == .Flash1M) { pub fn read(self: *const Self, buf: []u8, idx: usize) u8 {
switch (addr) { return buf[self.address() + idx];
0x0000 => if (self.id_mode) return 0x32, // Panasonic manufacturer ID
0x0001 => if (self.id_mode) return 0x1B, // Panasonic device ID
else => {},
}
} else {
switch (addr) {
0x0000 => if (self.id_mode) return 0x62, // Sanyo manufacturer ID
0x0001 => if (self.id_mode) return 0x13, // Sanyo device ID
else => {},
}
}
return buf[self.baseAddress() + addr];
} }
pub fn write(self: *Self, buf: []u8, address: u32, value: u8) void { pub fn write(self: *Self, buf: []u8, idx: usize, byte: u8) void {
const addr = address & 0xFFFF; buf[self.address() + idx] = byte;
if (self.prep_write) return self._write(buf, addr, value);
if (self.shouldEraseSector(addr, value)) return self.erase(buf, addr);
switch (addr) {
0x0000 => if (self.kind == .Flash1M and self.set_bank) {
self.bank = @truncate(u1, value);
},
0x5555 => {
if (self.state == .Command) {
self.handleCommand(buf, value);
} else if (value == 0xAA and self.state == .Ready) {
self.state = .Set;
} else if (value == 0xF0) {
self.state = .Ready;
}
},
0x2AAA => if (value == 0x55 and self.state == .Set) {
self.state = .Command;
},
else => {},
}
}
fn _write(self: *Self, buf: []u8, idx: usize, byte: u8) void {
buf[self.baseAddress() + idx] = byte;
self.prep_write = false; self.prep_write = false;
} }
pub fn create(kind: Kind) !Self { pub fn create() Self {
return .{ return .{
.state = .Ready, .state = .Ready,
.kind = kind,
.bank = 0,
.id_mode = false, .id_mode = false,
.set_bank = false, .set_bank = false,
.prep_erase = false, .prep_erase = false,
.prep_write = false, .prep_write = false,
.bank = 0,
}; };
} }
fn handleCommand(self: *Self, buf: []u8, value: u8) void { pub fn handleCommand(self: *Self, buf: []u8, byte: u8) void {
switch (value) { switch (byte) {
0x90 => self.id_mode = true, 0x90 => self.id_mode = true,
0xF0 => self.id_mode = false, 0xF0 => self.id_mode = false,
0xB0 => self.set_bank = true, 0xB0 => self.set_bank = true,
@ -89,18 +48,18 @@ fn handleCommand(self: *Self, buf: []u8, value: u8) void {
self.prep_erase = false; self.prep_erase = false;
}, },
0xA0 => self.prep_write = true, 0xA0 => self.prep_write = true,
else => std.debug.panic("Unhandled Flash Command: 0x{X:0>2}", .{value}), else => std.debug.panic("Unhandled Flash Command: 0x{X:0>2}", .{byte}),
} }
self.state = .Ready; self.state = .Ready;
} }
fn shouldEraseSector(self: *const Self, addr: usize, byte: u8) bool { pub fn shouldEraseSector(self: *const Self, addr: usize, byte: u8) bool {
return self.state == .Command and self.prep_erase and byte == 0x30 and addr & 0xFFF == 0x000; return self.state == .Command and self.prep_erase and byte == 0x30 and addr & 0xFFF == 0x000;
} }
fn erase(self: *Self, buf: []u8, sector: usize) void { pub fn erase(self: *Self, buf: []u8, sector: usize) void {
const start = self.baseAddress() + (sector & 0xF000); const start = self.address() + (sector & 0xF000);
std.mem.set(u8, buf[start..][0..0x1000], 0xFF); std.mem.set(u8, buf[start..][0..0x1000], 0xFF);
self.prep_erase = false; self.prep_erase = false;
@ -108,6 +67,6 @@ fn erase(self: *Self, buf: []u8, sector: usize) void {
} }
/// Base Address /// Base Address
inline fn baseAddress(self: *const Self) usize { inline fn address(self: *const Self) usize {
return if (self.bank == 1) 0x10000 else @as(usize, 0); return if (self.bank == 1) 0x10000 else @as(usize, 0);
} }

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@ -256,16 +256,11 @@ fn DmaController(comptime id: u2) type {
cpu.bus.write(u16, dad_addr, @truncate(u16, rotr(u32, self.data_latch, 8 * (dad_addr & 3)))); cpu.bus.write(u16, dad_addr, @truncate(u16, rotr(u32, self.data_latch, 8 * (dad_addr & 3))));
} }
switch (@truncate(u8, sad_addr >> 24)) { switch (sad_adj) {
// according to fleroviux, DMAs with a source address in ROM misbehave .Increment => self.sad_latch +%= offset,
// the resultant behaviour is that the source address will increment despite what DMAXCNT says .Decrement => self.sad_latch -%= offset,
0x08...0x0D => self.sad_latch +%= offset, // obscure behaviour .IncrementReload => log.err("{} is a prohibited adjustment on SAD", .{sad_adj}),
else => switch (sad_adj) { .Fixed => {},
.Increment => self.sad_latch +%= offset,
.Decrement => self.sad_latch -%= offset,
.IncrementReload => log.err("{} is a prohibited adjustment on SAD", .{sad_adj}),
.Fixed => {},
},
} }
switch (dad_adj) { switch (dad_adj) {

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@ -145,7 +145,7 @@ pub const Logger = struct {
if (cpu.cpsr.t.read()) { if (cpu.cpsr.t.read()) {
if (opcode >> 11 == 0x1E) { if (opcode >> 11 == 0x1E) {
// Instruction 1 of a BL Opcode, print in ARM mode // Instruction 1 of a BL Opcode, print in ARM mode
const low = cpu.bus.dbgRead(u16, cpu.r[15] - 2); const low = cpu.bus.dbgRead(u16, cpu.r[15]);
const bl_opcode = @as(u32, opcode) << 16 | low; const bl_opcode = @as(u32, opcode) << 16 | low;
self.print(arm_fmt, Self.fmtArgs(cpu, bl_opcode)) catch @panic("failed to write to log file"); self.print(arm_fmt, Self.fmtArgs(cpu, bl_opcode)) catch @panic("failed to write to log file");