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No commits in common. "3e25a7f5958e9dfd8026071e813821a6f9798432" and "750fdb65ae3019e7bf9b6dfb9892155cb1e5b35a" have entirely different histories.
3e25a7f595
...
750fdb65ae
@ -243,7 +243,7 @@ pub const Arm7tdmi = struct {
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const Self = @This();
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r: [16]u32,
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pipe: Pipeline,
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pipe: Pipline,
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sched: *Scheduler,
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bus: *Bus,
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cpsr: PSR,
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@ -264,7 +264,7 @@ pub const Arm7tdmi = struct {
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pub fn init(sched: *Scheduler, bus: *Bus, log_file: ?std.fs.File) Self {
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return Self{
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.r = [_]u32{0x00} ** 16,
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.pipe = Pipeline.init(),
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.pipe = Pipline.init(),
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.sched = sched,
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.bus = bus,
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.cpsr = .{ .raw = 0x0000_001F },
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@ -324,8 +324,21 @@ pub const Arm7tdmi = struct {
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return self.bus.io.haltcnt == .Halt;
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}
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pub fn setCpsrNoFlush(self: *Self, value: u32) void {
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if (value & 0x1F != self.cpsr.raw & 0x1F) self.changeModeFromIdx(@truncate(u5, value & 0x1F));
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self.cpsr.raw = value;
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}
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pub fn setCpsr(self: *Self, value: u32) void {
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if (value & 0x1F != self.cpsr.raw & 0x1F) self.changeModeFromIdx(@truncate(u5, value & 0x1F));
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const new: PSR = .{ .raw = value };
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if (self.cpsr.t.read() != new.t.read()) {
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// If THUMB to ARM or ARM to THUMB, flush pipeline
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self.r[15] &= if (new.t.read()) ~@as(u32, 1) else ~@as(u32, 3);
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if (new.t.read()) self.pipe.reload(u16, self) else self.pipe.reload(u32, self);
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}
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self.cpsr.raw = value;
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}
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@ -429,24 +442,22 @@ pub const Arm7tdmi = struct {
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}
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pub fn step(self: *Self) void {
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defer {
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if (!self.pipe.flushed) self.r[15] += if (self.cpsr.t.read()) 2 else @as(u32, 4);
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self.pipe.flushed = false;
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}
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if (self.cpsr.t.read()) {
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const opcode = @truncate(u16, self.pipe.step(self, u16) orelse return);
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if (self.cpsr.t.read()) blk: {
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const opcode = @truncate(u16, self.pipe.step(self, u16) orelse break :blk);
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if (cpu_logging) self.logger.?.mgbaLog(self, opcode);
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thumb.lut[thumb.idx(opcode)](self, self.bus, opcode);
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} else {
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const opcode = self.pipe.step(self, u32) orelse return;
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} else blk: {
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const opcode = self.pipe.step(self, u32) orelse break :blk;
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if (cpu_logging) self.logger.?.mgbaLog(self, opcode);
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if (checkCond(self.cpsr, @truncate(u4, opcode >> 28))) {
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arm.lut[arm.idx(opcode)](self, self.bus, opcode);
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}
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}
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if (!self.pipe.flushed) self.r[15] += if (self.cpsr.t.read()) 2 else @as(u32, 4);
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self.pipe.flushed = false;
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}
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pub fn stepDmaTransfer(self: *Self) bool {
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@ -484,14 +495,13 @@ pub const Arm7tdmi = struct {
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// Return if IME is disabled, CPSR I is set or there is nothing to handle
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if (!self.bus.io.ime or self.cpsr.i.read() or should_handle == 0) return;
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// If Pipeline isn't full, we have a bug
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std.debug.assert(self.pipe.isFull());
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// If pipeline isn't full, return but reschedule the handling of the event
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if (!self.pipe.isFull()) return;
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// log.debug("Handling Interrupt!", .{});
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self.bus.io.haltcnt = .Execute;
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// FIXME: This seems weird, but retAddr.gba suggests I need to make these changes
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const ret_addr = self.r[15] - if (self.cpsr.t.read()) 0 else @as(u32, 4);
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const ret_addr = self.r[15] - if (self.cpsr.t.read()) 2 else @as(u32, 4);
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const new_spsr = self.cpsr.raw;
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self.changeMode(.Irq);
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@ -501,21 +511,26 @@ pub const Arm7tdmi = struct {
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self.r[14] = ret_addr;
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self.spsr.raw = new_spsr;
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self.r[15] = 0x0000_0018;
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self.pipe.reload(self);
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self.pipe.reload(u32, self);
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}
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inline fn fetch(self: *Self, comptime T: type, address: u32) T {
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inline fn fetch(self: *Self, comptime T: type) T {
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comptime std.debug.assert(T == u32 or T == u16); // Opcode may be 32-bit (ARM) or 16-bit (THUMB)
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defer self.r[15] += if (T == u32) 4 else 2;
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// Bus.read will advance the scheduler. There are different timings for CPU fetches,
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// so we want to undo what Bus.read will apply. We can do this by caching the current tick
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// This is very dumb.
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//
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// FIXME: Please rework this
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// FIXME: You better hope this is optimized out
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const tick_cache = self.sched.tick;
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defer self.sched.tick = tick_cache + Bus.fetch_timings[@boolToInt(T == u32)][@truncate(u4, address >> 24)];
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defer self.sched.tick = tick_cache + Bus.fetch_timings[@boolToInt(T == u32)][@truncate(u4, self.r[15] >> 24)];
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return self.bus.read(T, address);
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return self.bus.read(T, self.r[15]);
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}
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fn debug_log(self: *const Self, file: *const File, opcode: u32) void {
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if (self.binary_log) {
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self.skyLog(file) catch unreachable;
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} else {
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self.mgbaLog(file, opcode) catch unreachable;
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}
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}
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pub fn panic(self: *const Self, comptime format: []const u8, args: anytype) noreturn {
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@ -641,7 +656,7 @@ pub fn checkCond(cpsr: PSR, cond: u4) bool {
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};
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}
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const Pipeline = struct {
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const Pipline = struct {
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const Self = @This();
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stage: [2]?u32,
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flushed: bool,
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@ -653,6 +668,15 @@ const Pipeline = struct {
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};
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}
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pub fn flush(self: *Self) void {
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for (self.stage) |*opcode| opcode.* = null;
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self.flushed = true;
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// Note: If using this, add
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// if (!self.pipe.flushed) self.r[15] += if (self.cpsr.t.read()) 2 else @as(u32, 4);
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// to the end of Arm7tdmi.step
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}
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pub fn isFull(self: *const Self) bool {
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return self.stage[0] != null and self.stage[1] != null;
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}
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@ -661,25 +685,26 @@ const Pipeline = struct {
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comptime std.debug.assert(T == u32 or T == u16);
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// FIXME: https://github.com/ziglang/zig/issues/12642
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var opcode = self.stage[0];
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const opcode = self.stage[0..1][0];
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self.stage[0] = self.stage[1];
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self.stage[1] = cpu.fetch(T, cpu.r[15]);
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self.stage[1] = cpu.bus.read(T, cpu.r[15]);
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return opcode;
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}
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pub fn reload(self: *Self, cpu: *Arm7tdmi) void {
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if (cpu.cpsr.t.read()) {
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self.stage[0] = cpu.fetch(u16, cpu.r[15]);
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self.stage[1] = cpu.fetch(u16, cpu.r[15] + 2);
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cpu.r[15] += 4;
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} else {
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self.stage[0] = cpu.fetch(u32, cpu.r[15]);
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self.stage[1] = cpu.fetch(u32, cpu.r[15] + 4);
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cpu.r[15] += 8;
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}
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pub fn reload(self: *Self, comptime T: type, cpu: *Arm7tdmi) void {
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comptime std.debug.assert(T == u32 or T == u16);
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// Sometimes, the pipeline can be reloaded twice in the same instruction
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// This can happen if:
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// 1. R15 is written to
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// 2. The CPSR is written to (and T changes), so R15 is written to again
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self.stage[0] = cpu.bus.read(T, cpu.r[15]);
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self.stage[1] = cpu.bus.read(T, cpu.r[15] + if (T == u32) 4 else @as(u32, 2));
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cpu.r[15] += if (T == u32) 8 else @as(u32, 4);
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self.flushed = true;
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}
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};
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@ -55,7 +55,7 @@ pub fn blockDataTransfer(comptime P: bool, comptime U: bool, comptime S: bool, c
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if (L) {
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cpu.r[15] = bus.read(u32, und_addr);
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cpu.pipe.reload(cpu);
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cpu.pipe.reload(u32, cpu);
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} else {
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// FIXME: Should r15 on write be +12 ahead?
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bus.write(u32, und_addr, cpu.r[15] + 4);
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@ -92,7 +92,7 @@ pub fn blockDataTransfer(comptime P: bool, comptime U: bool, comptime S: bool, c
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cpu.r[i] = value;
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if (i == 0xF) {
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cpu.r[i] &= ~@as(u32, 3); // Align r15
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cpu.pipe.reload(cpu);
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cpu.pipe.reload(u32, cpu);
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if (S) cpu.setCpsr(cpu.spsr.raw);
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}
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@ -12,7 +12,7 @@ pub fn branch(comptime L: bool) InstrFn {
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if (L) cpu.r[14] = cpu.r[15] - 4;
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cpu.r[15] +%= sext(u32, u24, opcode) << 2;
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cpu.pipe.reload(cpu);
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cpu.pipe.reload(u32, cpu);
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}
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}.inner;
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}
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@ -24,5 +24,5 @@ pub fn branchAndExchange(cpu: *Arm7tdmi, _: *Bus, opcode: u32) void {
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cpu.r[15] = cpu.r[rn] & if (thumb) ~@as(u32, 1) else ~@as(u32, 3);
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cpu.cpsr.t.write(thumb);
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cpu.pipe.reload(cpu);
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if (thumb) cpu.pipe.reload(u16, cpu) else cpu.pipe.reload(u32, cpu);
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}
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@ -24,7 +24,7 @@ pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime kind: u4) Ins
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if (!I and opcode >> 4 & 1 == 1) cpu.r[15] -= 4;
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var result: u32 = undefined;
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var overflow: bool = undefined;
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var didOverflow: bool = undefined;
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// Perform Data Processing Logic
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switch (kind) {
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@ -32,10 +32,10 @@ pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime kind: u4) Ins
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0x1 => result = op1 ^ op2, // EOR
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0x2 => result = op1 -% op2, // SUB
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0x3 => result = op2 -% op1, // RSB
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0x4 => result = add(&overflow, op1, op2), // ADD
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0x5 => result = adc(&overflow, op1, op2, old_carry), // ADC
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0x6 => result = sbc(op1, op2, old_carry), // SBC
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0x7 => result = sbc(op2, op1, old_carry), // RSC
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0x4 => result = newAdd(&didOverflow, op1, op2), // ADD
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0x5 => result = newAdc(&didOverflow, op1, op2, old_carry), // ADC
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0x6 => result = newSbc(op1, op2, old_carry), // SBC
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0x7 => result = newSbc(op2, op1, old_carry), // RSC
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0x8 => {
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// TST
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if (rd == 0xF)
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@ -62,7 +62,7 @@ pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime kind: u4) Ins
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if (rd == 0xF)
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return undefinedTestBehaviour(cpu);
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overflow = @addWithOverflow(u32, op1, op2, &result);
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didOverflow = @addWithOverflow(u32, op1, op2, &result);
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},
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0xC => result = op1 | op2, // ORR
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0xD => result = op2, // MOV
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@ -75,59 +75,73 @@ pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime kind: u4) Ins
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0x8, 0x9, 0xA, 0xB => {}, // Test Operations
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else => {
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cpu.r[rd] = result;
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if (rd == 0xF) {
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if (S) cpu.setCpsr(cpu.spsr.raw);
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cpu.pipe.reload(cpu);
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}
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if (rd == 0xF) cpu.pipe.reload(u32, cpu);
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},
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}
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// Write Flags
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switch (kind) {
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0x0, 0x1, 0xC, 0xD, 0xE, 0xF => if (S and rd != 0xF) {
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0x0, 0x1, 0xC, 0xD, 0xE, 0xF => {
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// Logic Operation Flags
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cpu.cpsr.n.write(result >> 31 & 1 == 1);
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cpu.cpsr.z.write(result == 0);
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// C set by Barrel Shifter, V is unaffected
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},
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0x2, 0x3 => if (S and rd != 0xF) {
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// SUB, RSB Flags
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cpu.cpsr.n.write(result >> 31 & 1 == 1);
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cpu.cpsr.z.write(result == 0);
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if (kind == 0x2) {
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// SUB specific
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cpu.cpsr.c.write(op2 <= op1);
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cpu.cpsr.v.write(((op1 ^ result) & (~op2 ^ result)) >> 31 & 1 == 1);
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} else {
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// RSB Specific
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cpu.cpsr.c.write(op1 <= op2);
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cpu.cpsr.v.write(((op2 ^ result) & (~op1 ^ result)) >> 31 & 1 == 1);
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if (S) {
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if (rd == 0xF) {
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cpu.setCpsr(cpu.spsr.raw);
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} else {
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cpu.cpsr.n.write(result >> 31 & 1 == 1);
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cpu.cpsr.z.write(result == 0);
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// C set by Barrel Shifter, V is unaffected
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}
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}
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},
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0x4, 0x5 => if (S and rd != 0xF) {
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// ADD, ADC Flags
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cpu.cpsr.n.write(result >> 31 & 1 == 1);
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cpu.cpsr.z.write(result == 0);
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cpu.cpsr.c.write(overflow);
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cpu.cpsr.v.write(((op1 ^ result) & (op2 ^ result)) >> 31 & 1 == 1);
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},
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0x6, 0x7 => if (S and rd != 0xF) {
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// SBC, RSC Flags
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cpu.cpsr.n.write(result >> 31 & 1 == 1);
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cpu.cpsr.z.write(result == 0);
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0x2, 0x3 => {
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// SUB, RSB Flags
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if (S) {
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cpu.cpsr.n.write(result >> 31 & 1 == 1);
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cpu.cpsr.z.write(result == 0);
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if (kind == 0x6) {
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// SBC specific
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const subtrahend = @as(u64, op2) -% old_carry +% 1;
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cpu.cpsr.c.write(subtrahend <= op1);
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cpu.cpsr.v.write(((op1 ^ result) & (~op2 ^ result)) >> 31 & 1 == 1);
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} else {
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// RSC Specific
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const subtrahend = @as(u64, op1) -% old_carry +% 1;
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cpu.cpsr.c.write(subtrahend <= op2);
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cpu.cpsr.v.write(((op2 ^ result) & (~op1 ^ result)) >> 31 & 1 == 1);
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if (kind == 0x2) {
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// SUB specific
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cpu.cpsr.c.write(op2 <= op1);
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cpu.cpsr.v.write(((op1 ^ result) & (~op2 ^ result)) >> 31 & 1 == 1);
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} else {
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// RSB Specific
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cpu.cpsr.c.write(op1 <= op2);
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cpu.cpsr.v.write(((op2 ^ result) & (~op1 ^ result)) >> 31 & 1 == 1);
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}
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if (rd == 0xF) cpu.setCpsr(cpu.spsr.raw);
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}
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},
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0x4, 0x5 => {
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// ADD, ADC Flags
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if (S) {
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cpu.cpsr.n.write(result >> 31 & 1 == 1);
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cpu.cpsr.z.write(result == 0);
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cpu.cpsr.c.write(didOverflow);
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cpu.cpsr.v.write(((op1 ^ result) & (op2 ^ result)) >> 31 & 1 == 1);
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if (rd == 0xF) cpu.setCpsr(cpu.spsr.raw);
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}
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},
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0x6, 0x7 => {
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// SBC, RSC Flags
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if (S) {
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cpu.cpsr.n.write(result >> 31 & 1 == 1);
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cpu.cpsr.z.write(result == 0);
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if (kind == 0x6) {
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// SBC specific
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const subtrahend = @as(u64, op2) -% old_carry +% 1;
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cpu.cpsr.c.write(subtrahend <= op1);
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cpu.cpsr.v.write(((op1 ^ result) & (~op2 ^ result)) >> 31 & 1 == 1);
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} else {
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// RSC Specific
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const subtrahend = @as(u64, op1) -% old_carry +% 1;
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cpu.cpsr.c.write(subtrahend <= op2);
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cpu.cpsr.v.write(((op2 ^ result) & (~op1 ^ result)) >> 31 & 1 == 1);
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}
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if (rd == 0xF) cpu.setCpsr(cpu.spsr.raw);
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}
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},
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0x8, 0x9, 0xA, 0xB => {
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@ -141,10 +155,10 @@ pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime kind: u4) Ins
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cpu.cpsr.v.write(((op1 ^ result) & (~op2 ^ result)) >> 31 & 1 == 1);
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} else if (kind == 0xB) {
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// CMN specific
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cpu.cpsr.c.write(overflow);
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cpu.cpsr.c.write(didOverflow);
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cpu.cpsr.v.write(((op1 ^ result) & (op2 ^ result)) >> 31 & 1 == 1);
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} else {
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// TST, TEQ specific
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// TEST, TEQ specific
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||||
// Barrel Shifter should always calc CPSR C in TST
|
||||
if (!S) _ = execute(true, cpu, opcode);
|
||||
}
|
||||
@ -154,7 +168,134 @@ pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime kind: u4) Ins
|
||||
}.inner;
|
||||
}
|
||||
|
||||
pub fn sbc(left: u32, right: u32, old_carry: u1) u32 {
|
||||
// pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime instrKind: u4) InstrFn {
|
||||
// return struct {
|
||||
// fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u32) void {
|
||||
// const rd = @truncate(u4, opcode >> 12 & 0xF);
|
||||
// const rn = opcode >> 16 & 0xF;
|
||||
// const old_carry = @boolToInt(cpu.cpsr.c.read());
|
||||
|
||||
// // If certain conditions are met, PC is 12 ahead instead of 8
|
||||
// // TODO: What are these conditions? I can't remember
|
||||
// if (!I and opcode >> 4 & 1 == 1) cpu.r[15] += 4;
|
||||
// const op1 = cpu.r[rn];
|
||||
|
||||
// const amount = @truncate(u8, (opcode >> 8 & 0xF) << 1);
|
||||
// const op2 = if (I) rotateRight(S, &cpu.cpsr, opcode & 0xFF, amount) else execute(S, cpu, opcode);
|
||||
|
||||
// // Undo special condition from above
|
||||
// if (!I and opcode >> 4 & 1 == 1) cpu.r[15] -= 4;
|
||||
|
||||
// switch (instrKind) {
|
||||
// 0x0 => {
|
||||
// // AND
|
||||
// const result = op1 & op2;
|
||||
// cpu.r[rd] = result;
|
||||
// setArmLogicOpFlags(S, cpu, rd, result);
|
||||
// },
|
||||
// 0x1 => {
|
||||
// // EOR
|
||||
// const result = op1 ^ op2;
|
||||
// cpu.r[rd] = result;
|
||||
// setArmLogicOpFlags(S, cpu, rd, result);
|
||||
// },
|
||||
// 0x2 => {
|
||||
// // SUB
|
||||
// cpu.r[rd] = armSub(S, cpu, rd, op1, op2);
|
||||
// },
|
||||
// 0x3 => {
|
||||
// // RSB
|
||||
// cpu.r[rd] = armSub(S, cpu, rd, op2, op1);
|
||||
// },
|
||||
// 0x4 => {
|
||||
// // ADD
|
||||
// cpu.r[rd] = armAdd(S, cpu, rd, op1, op2);
|
||||
// },
|
||||
// 0x5 => {
|
||||
// // ADC
|
||||
// cpu.r[rd] = armAdc(S, cpu, rd, op1, op2, old_carry);
|
||||
// },
|
||||
// 0x6 => {
|
||||
// // SBC
|
||||
// cpu.r[rd] = armSbc(S, cpu, rd, op1, op2, old_carry);
|
||||
// },
|
||||
// 0x7 => {
|
||||
// // RSC
|
||||
// cpu.r[rd] = armSbc(S, cpu, rd, op2, op1, old_carry);
|
||||
// },
|
||||
// 0x8 => {
|
||||
// // TST
|
||||
// if (rd == 0xF)
|
||||
// return undefinedTestBehaviour(cpu);
|
||||
|
||||
// const result = op1 & op2;
|
||||
// setTestOpFlags(S, cpu, opcode, result);
|
||||
// },
|
||||
// 0x9 => {
|
||||
// // TEQ
|
||||
// if (rd == 0xF)
|
||||
// return undefinedTestBehaviour(cpu);
|
||||
|
||||
// const result = op1 ^ op2;
|
||||
// setTestOpFlags(S, cpu, opcode, result);
|
||||
// },
|
||||
// 0xA => {
|
||||
// // CMP
|
||||
// if (rd == 0xF)
|
||||
// return undefinedTestBehaviour(cpu);
|
||||
|
||||
// cmp(cpu, op1, op2);
|
||||
// },
|
||||
// 0xB => {
|
||||
// // CMN
|
||||
// if (rd == 0xF)
|
||||
// return undefinedTestBehaviour(cpu);
|
||||
|
||||
// cmn(cpu, op1, op2);
|
||||
// },
|
||||
// 0xC => {
|
||||
// // ORR
|
||||
// const result = op1 | op2;
|
||||
// cpu.r[rd] = result;
|
||||
// setArmLogicOpFlags(S, cpu, rd, result);
|
||||
// },
|
||||
// 0xD => {
|
||||
// // MOV
|
||||
// cpu.r[rd] = op2;
|
||||
// setArmLogicOpFlags(S, cpu, rd, op2);
|
||||
// },
|
||||
// 0xE => {
|
||||
// // BIC
|
||||
// const result = op1 & ~op2;
|
||||
// cpu.r[rd] = result;
|
||||
// setArmLogicOpFlags(S, cpu, rd, result);
|
||||
// },
|
||||
// 0xF => {
|
||||
// // MVN
|
||||
// const result = ~op2;
|
||||
// cpu.r[rd] = result;
|
||||
// setArmLogicOpFlags(S, cpu, rd, result);
|
||||
// },
|
||||
// }
|
||||
|
||||
// if (rd == 0xF) cpu.pipe.reload(u32, cpu);
|
||||
// }
|
||||
// }.inner;
|
||||
// }
|
||||
|
||||
fn armSbc(comptime S: bool, cpu: *Arm7tdmi, rd: u4, left: u32, right: u32, old_carry: u1) u32 {
|
||||
var result: u32 = undefined;
|
||||
if (S and rd == 0xF) {
|
||||
result = sbc(false, cpu, left, right, old_carry);
|
||||
cpu.setCpsr(cpu.spsr.raw);
|
||||
} else {
|
||||
result = sbc(S, cpu, left, right, old_carry);
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
fn newSbc(left: u32, right: u32, old_carry: u1) u32 {
|
||||
// TODO: Make your own version (thanks peach.bot)
|
||||
const subtrahend = @as(u64, right) -% old_carry +% 1;
|
||||
const ret = @truncate(u32, left -% subtrahend);
|
||||
@ -162,22 +303,157 @@ pub fn sbc(left: u32, right: u32, old_carry: u1) u32 {
|
||||
return ret;
|
||||
}
|
||||
|
||||
pub fn add(overflow: *bool, left: u32, right: u32) u32 {
|
||||
pub fn sbc(comptime S: bool, cpu: *Arm7tdmi, left: u32, right: u32, old_carry: u1) u32 {
|
||||
// TODO: Make your own version (thanks peach.bot)
|
||||
const subtrahend = @as(u64, right) -% old_carry +% 1;
|
||||
const result = @truncate(u32, left -% subtrahend);
|
||||
|
||||
if (S) {
|
||||
cpu.cpsr.n.write(result >> 31 & 1 == 1);
|
||||
cpu.cpsr.z.write(result == 0);
|
||||
cpu.cpsr.c.write(subtrahend <= left);
|
||||
cpu.cpsr.v.write(((left ^ result) & (~right ^ result)) >> 31 & 1 == 1);
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
fn armSub(comptime S: bool, cpu: *Arm7tdmi, rd: u4, left: u32, right: u32) u32 {
|
||||
var result: u32 = undefined;
|
||||
if (S and rd == 0xF) {
|
||||
result = sub(false, cpu, left, right);
|
||||
cpu.setCpsr(cpu.spsr.raw);
|
||||
} else {
|
||||
result = sub(S, cpu, left, right);
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
pub fn sub(comptime S: bool, cpu: *Arm7tdmi, left: u32, right: u32) u32 {
|
||||
const result = left -% right;
|
||||
|
||||
if (S) {
|
||||
cpu.cpsr.n.write(result >> 31 & 1 == 1);
|
||||
cpu.cpsr.z.write(result == 0);
|
||||
cpu.cpsr.c.write(right <= left);
|
||||
cpu.cpsr.v.write(((left ^ result) & (~right ^ result)) >> 31 & 1 == 1);
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
fn armAdd(comptime S: bool, cpu: *Arm7tdmi, rd: u4, left: u32, right: u32) u32 {
|
||||
var result: u32 = undefined;
|
||||
if (S and rd == 0xF) {
|
||||
result = add(false, cpu, left, right);
|
||||
cpu.setCpsr(cpu.spsr.raw);
|
||||
} else {
|
||||
result = add(S, cpu, left, right);
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
fn newAdd(didOverflow: *bool, left: u32, right: u32) u32 {
|
||||
var ret: u32 = undefined;
|
||||
overflow.* = @addWithOverflow(u32, left, right, &ret);
|
||||
didOverflow.* = @addWithOverflow(u32, left, right, &ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
pub fn adc(overflow: *bool, left: u32, right: u32, old_carry: u1) u32 {
|
||||
var ret: u32 = undefined;
|
||||
const first = @addWithOverflow(u32, left, right, &ret);
|
||||
const second = @addWithOverflow(u32, ret, old_carry, &ret);
|
||||
pub fn add(comptime S: bool, cpu: *Arm7tdmi, left: u32, right: u32) u32 {
|
||||
var result: u32 = undefined;
|
||||
const didOverflow = @addWithOverflow(u32, left, right, &result);
|
||||
|
||||
overflow.* = first or second;
|
||||
if (S) {
|
||||
cpu.cpsr.n.write(result >> 31 & 1 == 1);
|
||||
cpu.cpsr.z.write(result == 0);
|
||||
cpu.cpsr.c.write(didOverflow);
|
||||
cpu.cpsr.v.write(((left ^ result) & (right ^ result)) >> 31 & 1 == 1);
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
fn armAdc(comptime S: bool, cpu: *Arm7tdmi, rd: u4, left: u32, right: u32, old_carry: u1) u32 {
|
||||
var result: u32 = undefined;
|
||||
if (S and rd == 0xF) {
|
||||
result = adc(false, cpu, left, right, old_carry);
|
||||
cpu.setCpsr(cpu.spsr.raw);
|
||||
} else {
|
||||
result = adc(S, cpu, left, right, old_carry);
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
fn newAdc(didOverflow: *bool, left: u32, right: u32, old_carry: u1) u32 {
|
||||
var ret: u32 = undefined;
|
||||
const did = @addWithOverflow(u32, left, right, &ret);
|
||||
const overflow = @addWithOverflow(u32, ret, old_carry, &ret);
|
||||
|
||||
didOverflow.* = did or overflow;
|
||||
return ret;
|
||||
}
|
||||
|
||||
pub fn adc(comptime S: bool, cpu: *Arm7tdmi, left: u32, right: u32, old_carry: u1) u32 {
|
||||
var result: u32 = undefined;
|
||||
const did = @addWithOverflow(u32, left, right, &result);
|
||||
const overflow = @addWithOverflow(u32, result, old_carry, &result);
|
||||
|
||||
if (S) {
|
||||
cpu.cpsr.n.write(result >> 31 & 1 == 1);
|
||||
cpu.cpsr.z.write(result == 0);
|
||||
cpu.cpsr.c.write(did or overflow);
|
||||
cpu.cpsr.v.write(((left ^ result) & (right ^ result)) >> 31 & 1 == 1);
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
pub fn cmp(cpu: *Arm7tdmi, left: u32, right: u32) void {
|
||||
const result = left -% right;
|
||||
|
||||
cpu.cpsr.n.write(result >> 31 & 1 == 1);
|
||||
cpu.cpsr.z.write(result == 0);
|
||||
cpu.cpsr.c.write(right <= left);
|
||||
cpu.cpsr.v.write(((left ^ result) & (~right ^ result)) >> 31 & 1 == 1);
|
||||
}
|
||||
|
||||
pub fn cmn(cpu: *Arm7tdmi, left: u32, right: u32) void {
|
||||
var result: u32 = undefined;
|
||||
const didOverflow = @addWithOverflow(u32, left, right, &result);
|
||||
|
||||
cpu.cpsr.n.write(result >> 31 & 1 == 1);
|
||||
cpu.cpsr.z.write(result == 0);
|
||||
cpu.cpsr.c.write(didOverflow);
|
||||
cpu.cpsr.v.write(((left ^ result) & (right ^ result)) >> 31 & 1 == 1);
|
||||
}
|
||||
|
||||
fn setArmLogicOpFlags(comptime S: bool, cpu: *Arm7tdmi, rd: u4, result: u32) void {
|
||||
if (S and rd == 0xF) {
|
||||
cpu.setCpsr(cpu.spsr.raw);
|
||||
} else {
|
||||
setLogicOpFlags(S, cpu, result);
|
||||
}
|
||||
}
|
||||
|
||||
pub fn setLogicOpFlags(comptime S: bool, cpu: *Arm7tdmi, result: u32) void {
|
||||
if (S) {
|
||||
cpu.cpsr.n.write(result >> 31 & 1 == 1);
|
||||
cpu.cpsr.z.write(result == 0);
|
||||
// C set by Barrel Shifter, V is unaffected
|
||||
}
|
||||
}
|
||||
|
||||
fn setTestOpFlags(comptime S: bool, cpu: *Arm7tdmi, opcode: u32, result: u32) void {
|
||||
cpu.cpsr.n.write(result >> 31 & 1 == 1);
|
||||
cpu.cpsr.z.write(result == 0);
|
||||
// Barrel Shifter should always calc CPSR C in TST
|
||||
if (!S) _ = execute(true, cpu, opcode);
|
||||
}
|
||||
|
||||
fn undefinedTestBehaviour(cpu: *Arm7tdmi) void {
|
||||
@setCold(true);
|
||||
cpu.setCpsr(cpu.spsr.raw);
|
||||
cpu.setCpsrNoFlush(cpu.spsr.raw);
|
||||
}
|
||||
|
||||
@ -47,13 +47,13 @@ pub fn singleDataTransfer(comptime I: bool, comptime P: bool, comptime U: bool,
|
||||
address = modified_base;
|
||||
if (W and P or !P) {
|
||||
cpu.r[rn] = address;
|
||||
if (rn == 0xF) cpu.pipe.reload(cpu);
|
||||
if (rn == 0xF) cpu.pipe.reload(u32, cpu);
|
||||
}
|
||||
|
||||
if (L) {
|
||||
// This emulates the LDR rd == rn behaviour
|
||||
cpu.r[rd] = result;
|
||||
if (rd == 0xF) cpu.pipe.reload(cpu);
|
||||
if (rd == 0xF) cpu.pipe.reload(u32, cpu);
|
||||
}
|
||||
}
|
||||
}.inner;
|
||||
|
||||
@ -17,7 +17,7 @@ pub fn armSoftwareInterrupt() InstrFn {
|
||||
cpu.r[14] = ret_addr; // Resume Execution
|
||||
cpu.spsr.raw = cpsr; // Previous mode CPSR
|
||||
cpu.r[15] = 0x0000_0008;
|
||||
cpu.pipe.reload(cpu);
|
||||
cpu.pipe.reload(u32, cpu);
|
||||
}
|
||||
}.inner;
|
||||
}
|
||||
|
||||
@ -4,11 +4,16 @@ const InstrFn = @import("../../cpu.zig").thumb.InstrFn;
|
||||
|
||||
const adc = @import("../arm/data_processing.zig").adc;
|
||||
const sbc = @import("../arm/data_processing.zig").sbc;
|
||||
const sub = @import("../arm/data_processing.zig").sub;
|
||||
const cmp = @import("../arm/data_processing.zig").cmp;
|
||||
const cmn = @import("../arm/data_processing.zig").cmn;
|
||||
const setTestOpFlags = @import("../arm/data_processing.zig").setTestOpFlags;
|
||||
const setLogicOpFlags = @import("../arm/data_processing.zig").setLogicOpFlags;
|
||||
|
||||
const lsl = @import("../barrel_shifter.zig").logicalLeft;
|
||||
const lsr = @import("../barrel_shifter.zig").logicalRight;
|
||||
const asr = @import("../barrel_shifter.zig").arithmeticRight;
|
||||
const ror = @import("../barrel_shifter.zig").rotateRight;
|
||||
const logicalLeft = @import("../barrel_shifter.zig").logicalLeft;
|
||||
const logicalRight = @import("../barrel_shifter.zig").logicalRight;
|
||||
const arithmeticRight = @import("../barrel_shifter.zig").arithmeticRight;
|
||||
const rotateRight = @import("../barrel_shifter.zig").rotateRight;
|
||||
|
||||
pub fn fmt4(comptime op: u4) InstrFn {
|
||||
return struct {
|
||||
@ -17,85 +22,96 @@ pub fn fmt4(comptime op: u4) InstrFn {
|
||||
const rd = opcode & 0x7;
|
||||
const carry = @boolToInt(cpu.cpsr.c.read());
|
||||
|
||||
const op1 = cpu.r[rd];
|
||||
const op2 = cpu.r[rs];
|
||||
|
||||
var result: u32 = undefined;
|
||||
var overflow: bool = undefined;
|
||||
switch (op) {
|
||||
0x0 => result = op1 & op2, // AND
|
||||
0x1 => result = op1 ^ op2, // EOR
|
||||
0x2 => result = lsl(true, &cpu.cpsr, op1, @truncate(u8, op2)), // LSL
|
||||
0x3 => result = lsr(true, &cpu.cpsr, op1, @truncate(u8, op2)), // LSR
|
||||
0x4 => result = asr(true, &cpu.cpsr, op1, @truncate(u8, op2)), // ASR
|
||||
0x5 => result = adc(&overflow, op1, op2, carry), // ADC
|
||||
0x6 => result = sbc(op1, op2, carry), // SBC
|
||||
0x7 => result = ror(true, &cpu.cpsr, op1, @truncate(u8, op2)), // ROR
|
||||
0x8 => result = op1 & op2, // TST
|
||||
0x9 => result = 0 -% op2, // NEG
|
||||
0xA => result = op1 -% op2, // CMP
|
||||
0xB => overflow = @addWithOverflow(u32, op1, op2, &result), // CMN
|
||||
0xC => result = op1 | op2, // ORR
|
||||
0xD => result = @truncate(u32, @as(u64, op2) * @as(u64, op1)),
|
||||
0xE => result = op1 & ~op2,
|
||||
0xF => result = ~op2,
|
||||
}
|
||||
|
||||
// Write to Destination Register
|
||||
switch (op) {
|
||||
0x8, 0xA, 0xB => {},
|
||||
else => cpu.r[rd] = result,
|
||||
}
|
||||
|
||||
// Write Flags
|
||||
switch (op) {
|
||||
0x0, 0x1, 0x2, 0x3, 0x4, 0x7, 0xC, 0xE, 0xF => {
|
||||
// Logic Operations
|
||||
cpu.cpsr.n.write(result >> 31 & 1 == 1);
|
||||
cpu.cpsr.z.write(result == 0);
|
||||
// C set by Barrel Shifter, V is unaffected
|
||||
0x0 => {
|
||||
// AND
|
||||
const result = cpu.r[rd] & cpu.r[rs];
|
||||
cpu.r[rd] = result;
|
||||
setLogicOpFlags(true, cpu, result);
|
||||
},
|
||||
0x8, 0xA => {
|
||||
// Test Flags
|
||||
// CMN (0xB) is handled with ADC
|
||||
cpu.cpsr.n.write(result >> 31 & 1 == 1);
|
||||
cpu.cpsr.z.write(result == 0);
|
||||
|
||||
if (op == 0xA) {
|
||||
// CMP specific
|
||||
cpu.cpsr.c.write(op2 <= op1);
|
||||
cpu.cpsr.v.write(((op1 ^ result) & (~op2 ^ result)) >> 31 & 1 == 1);
|
||||
}
|
||||
0x1 => {
|
||||
// EOR
|
||||
const result = cpu.r[rd] ^ cpu.r[rs];
|
||||
cpu.r[rd] = result;
|
||||
setLogicOpFlags(true, cpu, result);
|
||||
},
|
||||
0x5, 0xB => {
|
||||
// ADC, CMN
|
||||
cpu.cpsr.n.write(result >> 31 & 1 == 1);
|
||||
cpu.cpsr.z.write(result == 0);
|
||||
cpu.cpsr.c.write(overflow);
|
||||
cpu.cpsr.v.write(((op1 ^ result) & (op2 ^ result)) >> 31 & 1 == 1);
|
||||
0x2 => {
|
||||
// LSL
|
||||
const result = logicalLeft(true, &cpu.cpsr, cpu.r[rd], @truncate(u8, cpu.r[rs]));
|
||||
cpu.r[rd] = result;
|
||||
setLogicOpFlags(true, cpu, result);
|
||||
},
|
||||
0x3 => {
|
||||
// LSR
|
||||
const result = logicalRight(true, &cpu.cpsr, cpu.r[rd], @truncate(u8, cpu.r[rs]));
|
||||
cpu.r[rd] = result;
|
||||
setLogicOpFlags(true, cpu, result);
|
||||
},
|
||||
0x4 => {
|
||||
// ASR
|
||||
const result = arithmeticRight(true, &cpu.cpsr, cpu.r[rd], @truncate(u8, cpu.r[rs]));
|
||||
cpu.r[rd] = result;
|
||||
setLogicOpFlags(true, cpu, result);
|
||||
},
|
||||
0x5 => {
|
||||
// ADC
|
||||
cpu.r[rd] = adc(true, cpu, cpu.r[rd], cpu.r[rs], carry);
|
||||
},
|
||||
0x6 => {
|
||||
// SBC
|
||||
cpu.cpsr.n.write(result >> 31 & 1 == 1);
|
||||
cpu.cpsr.z.write(result == 0);
|
||||
|
||||
const subtrahend = @as(u64, op2) -% carry +% 1;
|
||||
cpu.cpsr.c.write(subtrahend <= op1);
|
||||
cpu.cpsr.v.write(((op1 ^ result) & (~op2 ^ result)) >> 31 & 1 == 1);
|
||||
cpu.r[rd] = sbc(true, cpu, cpu.r[rd], cpu.r[rs], carry);
|
||||
},
|
||||
0x7 => {
|
||||
// ROR
|
||||
const result = rotateRight(true, &cpu.cpsr, cpu.r[rd], @truncate(u8, cpu.r[rs]));
|
||||
cpu.r[rd] = result;
|
||||
setLogicOpFlags(true, cpu, result);
|
||||
},
|
||||
0x8 => {
|
||||
// TST
|
||||
const result = cpu.r[rd] & cpu.r[rs];
|
||||
setLogicOpFlags(true, cpu, result);
|
||||
},
|
||||
0x9 => {
|
||||
// NEG
|
||||
cpu.cpsr.n.write(result >> 31 & 1 == 1);
|
||||
cpu.cpsr.z.write(result == 0);
|
||||
cpu.cpsr.c.write(op2 <= 0);
|
||||
cpu.cpsr.v.write(((0 ^ result) & (~op2 ^ result)) >> 31 & 1 == 1);
|
||||
cpu.r[rd] = sub(true, cpu, 0, cpu.r[rs]);
|
||||
},
|
||||
0xA => {
|
||||
// CMP
|
||||
cmp(cpu, cpu.r[rd], cpu.r[rs]);
|
||||
},
|
||||
0xB => {
|
||||
// CMN
|
||||
cmn(cpu, cpu.r[rd], cpu.r[rs]);
|
||||
},
|
||||
0xC => {
|
||||
// ORR
|
||||
const result = cpu.r[rd] | cpu.r[rs];
|
||||
cpu.r[rd] = result;
|
||||
setLogicOpFlags(true, cpu, result);
|
||||
},
|
||||
0xD => {
|
||||
// Multiplication
|
||||
// MUL
|
||||
const temp = @as(u64, cpu.r[rs]) * @as(u64, cpu.r[rd]);
|
||||
const result = @truncate(u32, temp);
|
||||
cpu.r[rd] = result;
|
||||
|
||||
cpu.cpsr.n.write(result >> 31 & 1 == 1);
|
||||
cpu.cpsr.z.write(result == 0);
|
||||
// V is unaffected, assuming similar behaviour to ARMv4 MUL C is undefined
|
||||
},
|
||||
0xE => {
|
||||
// BIC
|
||||
const result = cpu.r[rd] & ~cpu.r[rs];
|
||||
cpu.r[rd] = result;
|
||||
setLogicOpFlags(true, cpu, result);
|
||||
},
|
||||
0xF => {
|
||||
// MVN
|
||||
const result = ~cpu.r[rs];
|
||||
cpu.r[rd] = result;
|
||||
setLogicOpFlags(true, cpu, result);
|
||||
},
|
||||
}
|
||||
}
|
||||
}.inner;
|
||||
|
||||
@ -34,7 +34,7 @@ pub fn fmt14(comptime L: bool, comptime R: bool) InstrFn {
|
||||
if (L) {
|
||||
const value = bus.read(u32, address);
|
||||
cpu.r[15] = value & ~@as(u32, 1);
|
||||
cpu.pipe.reload(cpu);
|
||||
cpu.pipe.reload(u16, cpu);
|
||||
} else {
|
||||
bus.write(u32, address, cpu.r[14]);
|
||||
}
|
||||
@ -55,7 +55,7 @@ pub fn fmt15(comptime L: bool, comptime rb: u3) InstrFn {
|
||||
if (opcode & 0xFF == 0) {
|
||||
if (L) {
|
||||
cpu.r[15] = bus.read(u32, address);
|
||||
cpu.pipe.reload(cpu);
|
||||
cpu.pipe.reload(u16, cpu);
|
||||
} else {
|
||||
bus.write(u32, address, cpu.r[15] + 2);
|
||||
}
|
||||
|
||||
@ -15,7 +15,7 @@ pub fn fmt16(comptime cond: u4) InstrFn {
|
||||
if (!checkCond(cpu.cpsr, cond)) return;
|
||||
|
||||
cpu.r[15] +%= sext(u32, u8, opcode & 0xFF) << 1;
|
||||
cpu.pipe.reload(cpu);
|
||||
cpu.pipe.reload(u16, cpu);
|
||||
}
|
||||
}.inner;
|
||||
}
|
||||
@ -25,7 +25,7 @@ pub fn fmt18() InstrFn {
|
||||
// B but conditional
|
||||
fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void {
|
||||
cpu.r[15] +%= sext(u32, u11, opcode & 0x7FF) << 1;
|
||||
cpu.pipe.reload(cpu);
|
||||
cpu.pipe.reload(u16, cpu);
|
||||
}
|
||||
}.inner;
|
||||
}
|
||||
@ -43,7 +43,7 @@ pub fn fmt19(comptime is_low: bool) InstrFn {
|
||||
cpu.r[15] = cpu.r[14] +% (offset << 1);
|
||||
cpu.r[14] = next_opcode | 1;
|
||||
|
||||
cpu.pipe.reload(cpu);
|
||||
cpu.pipe.reload(u16, cpu);
|
||||
} else {
|
||||
// Instruction 1
|
||||
const lr_offset = sext(u32, u11, offset) << 12;
|
||||
|
||||
@ -3,12 +3,12 @@ const std = @import("std");
|
||||
const Bus = @import("../../Bus.zig");
|
||||
const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
|
||||
const InstrFn = @import("../../cpu.zig").thumb.InstrFn;
|
||||
const shifter = @import("../barrel_shifter.zig");
|
||||
|
||||
const add = @import("../arm/data_processing.zig").add;
|
||||
|
||||
const lsl = @import("../barrel_shifter.zig").logicalLeft;
|
||||
const lsr = @import("../barrel_shifter.zig").logicalRight;
|
||||
const asr = @import("../barrel_shifter.zig").arithmeticRight;
|
||||
const sub = @import("../arm/data_processing.zig").sub;
|
||||
const cmp = @import("../arm/data_processing.zig").cmp;
|
||||
const setLogicOpFlags = @import("../arm/data_processing.zig").setLogicOpFlags;
|
||||
|
||||
pub fn fmt1(comptime op: u2, comptime offset: u5) InstrFn {
|
||||
return struct {
|
||||
@ -22,7 +22,7 @@ pub fn fmt1(comptime op: u2, comptime offset: u5) InstrFn {
|
||||
if (offset == 0) {
|
||||
break :blk cpu.r[rs];
|
||||
} else {
|
||||
break :blk lsl(true, &cpu.cpsr, cpu.r[rs], offset);
|
||||
break :blk shifter.logicalLeft(true, &cpu.cpsr, cpu.r[rs], offset);
|
||||
}
|
||||
},
|
||||
0b01 => blk: {
|
||||
@ -31,7 +31,7 @@ pub fn fmt1(comptime op: u2, comptime offset: u5) InstrFn {
|
||||
cpu.cpsr.c.write(cpu.r[rs] >> 31 & 1 == 1);
|
||||
break :blk @as(u32, 0);
|
||||
} else {
|
||||
break :blk lsr(true, &cpu.cpsr, cpu.r[rs], offset);
|
||||
break :blk shifter.logicalRight(true, &cpu.cpsr, cpu.r[rs], offset);
|
||||
}
|
||||
},
|
||||
0b10 => blk: {
|
||||
@ -40,7 +40,7 @@ pub fn fmt1(comptime op: u2, comptime offset: u5) InstrFn {
|
||||
cpu.cpsr.c.write(cpu.r[rs] >> 31 & 1 == 1);
|
||||
break :blk @bitCast(u32, @bitCast(i32, cpu.r[rs]) >> 31);
|
||||
} else {
|
||||
break :blk asr(true, &cpu.cpsr, cpu.r[rs], offset);
|
||||
break :blk shifter.arithmeticRight(true, &cpu.cpsr, cpu.r[rs], offset);
|
||||
}
|
||||
},
|
||||
else => cpu.panic("[CPU/THUMB.1] 0b{b:0>2} is not a valid op", .{op}),
|
||||
@ -48,10 +48,7 @@ pub fn fmt1(comptime op: u2, comptime offset: u5) InstrFn {
|
||||
|
||||
// Equivalent to an ARM MOVS
|
||||
cpu.r[rd] = result;
|
||||
|
||||
// Write Flags
|
||||
cpu.cpsr.n.write(result >> 31 & 1 == 1);
|
||||
cpu.cpsr.z.write(result == 0);
|
||||
setLogicOpFlags(true, cpu, result);
|
||||
}
|
||||
}.inner;
|
||||
}
|
||||
@ -62,49 +59,35 @@ pub fn fmt5(comptime op: u2, comptime h1: u1, comptime h2: u1) InstrFn {
|
||||
const rs = @as(u4, h2) << 3 | (opcode >> 3 & 0x7);
|
||||
const rd = @as(u4, h1) << 3 | (opcode & 0x7);
|
||||
|
||||
const op1 = cpu.r[rd];
|
||||
const op2 = cpu.r[rs];
|
||||
const rs_value = if (rs == 0xF) cpu.r[rs] & ~@as(u32, 1) else cpu.r[rs];
|
||||
const rd_value = if (rd == 0xF) cpu.r[rd] & ~@as(u32, 1) else cpu.r[rd];
|
||||
|
||||
var result: u32 = undefined;
|
||||
var overflow: bool = undefined;
|
||||
switch (op) {
|
||||
0b00 => result = add(&overflow, op1, op2), // ADD
|
||||
0b01 => result = op1 -% op2, // CMP
|
||||
0b10 => result = op2, // MOV
|
||||
0b11 => {},
|
||||
}
|
||||
|
||||
// Write to Destination Register
|
||||
switch (op) {
|
||||
0b01 => {}, // Test Instruction
|
||||
0b00 => {
|
||||
// ADD
|
||||
const sum = add(false, cpu, rd_value, rs_value);
|
||||
cpu.r[rd] = if (rd == 0xF) sum & ~@as(u32, 1) else sum;
|
||||
},
|
||||
0b01 => cmp(cpu, rd_value, rs_value), // CMP
|
||||
0b10 => {
|
||||
// MOV
|
||||
cpu.r[rd] = if (rd == 0xF) rs_value & ~@as(u32, 1) else rs_value;
|
||||
},
|
||||
0b11 => {
|
||||
// BX
|
||||
const is_thumb = op2 & 1 == 1;
|
||||
cpu.r[15] = op2 & ~@as(u32, 1);
|
||||
const thumb = rs_value & 1 == 1;
|
||||
cpu.r[15] = rs_value & ~@as(u32, 1);
|
||||
|
||||
cpu.cpsr.t.write(is_thumb);
|
||||
cpu.pipe.reload(cpu);
|
||||
},
|
||||
else => {
|
||||
cpu.r[rd] = result;
|
||||
if (rd == 0xF) {
|
||||
cpu.r[15] &= ~@as(u32, 1);
|
||||
cpu.pipe.reload(cpu);
|
||||
}
|
||||
cpu.cpsr.t.write(thumb);
|
||||
if (thumb) cpu.pipe.reload(u16, cpu) else cpu.pipe.reload(u32, cpu);
|
||||
|
||||
// TODO: We shouldn't need to worry about the if statement
|
||||
// below, because in BX, rd SBZ (and H1 is guaranteed to be 0)
|
||||
return;
|
||||
},
|
||||
}
|
||||
|
||||
// Write Flags
|
||||
switch (op) {
|
||||
0b01 => {
|
||||
// CMP
|
||||
cpu.cpsr.n.write(result >> 31 & 1 == 1);
|
||||
cpu.cpsr.z.write(result == 0);
|
||||
cpu.cpsr.c.write(op2 <= op1);
|
||||
cpu.cpsr.v.write(((op1 ^ result) & (~op2 ^ result)) >> 31 & 1 == 1);
|
||||
},
|
||||
0b00, 0b10, 0b11 => {}, // MOV and Branch Instruction
|
||||
}
|
||||
if (rd == 0xF) cpu.pipe.reload(u16, cpu);
|
||||
}
|
||||
}.inner;
|
||||
}
|
||||
@ -114,28 +97,21 @@ pub fn fmt2(comptime I: bool, is_sub: bool, rn: u3) InstrFn {
|
||||
fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void {
|
||||
const rs = opcode >> 3 & 0x7;
|
||||
const rd = @truncate(u3, opcode);
|
||||
const op1 = cpu.r[rs];
|
||||
const op2: u32 = if (I) rn else cpu.r[rn];
|
||||
|
||||
if (is_sub) {
|
||||
// SUB
|
||||
const result = op1 -% op2;
|
||||
cpu.r[rd] = result;
|
||||
|
||||
cpu.cpsr.n.write(result >> 31 & 1 == 1);
|
||||
cpu.cpsr.z.write(result == 0);
|
||||
cpu.cpsr.c.write(op2 <= op1);
|
||||
cpu.cpsr.v.write(((op1 ^ result) & (~op2 ^ result)) >> 31 & 1 == 1);
|
||||
cpu.r[rd] = if (I) blk: {
|
||||
break :blk sub(true, cpu, cpu.r[rs], rn);
|
||||
} else blk: {
|
||||
break :blk sub(true, cpu, cpu.r[rs], cpu.r[rn]);
|
||||
};
|
||||
} else {
|
||||
// ADD
|
||||
var overflow: bool = undefined;
|
||||
const result = add(&overflow, op1, op2);
|
||||
cpu.r[rd] = result;
|
||||
|
||||
cpu.cpsr.n.write(result >> 31 & 1 == 1);
|
||||
cpu.cpsr.z.write(result == 0);
|
||||
cpu.cpsr.c.write(overflow);
|
||||
cpu.cpsr.v.write(((op1 ^ result) & (op2 ^ result)) >> 31 & 1 == 1);
|
||||
cpu.r[rd] = if (I) blk: {
|
||||
break :blk add(true, cpu, cpu.r[rs], rn);
|
||||
} else blk: {
|
||||
break :blk add(true, cpu, cpu.r[rs], cpu.r[rn]);
|
||||
};
|
||||
}
|
||||
}
|
||||
}.inner;
|
||||
@ -144,36 +120,17 @@ pub fn fmt2(comptime I: bool, is_sub: bool, rn: u3) InstrFn {
|
||||
pub fn fmt3(comptime op: u2, comptime rd: u3) InstrFn {
|
||||
return struct {
|
||||
fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void {
|
||||
const op1 = cpu.r[rd];
|
||||
const op2: u32 = opcode & 0xFF; // Offset
|
||||
|
||||
var overflow: bool = undefined;
|
||||
const result: u32 = switch (op) {
|
||||
0b00 => op2, // MOV
|
||||
0b01 => op1 -% op2, // CMP
|
||||
0b10 => add(&overflow, op1, op2), // ADD
|
||||
0b11 => op1 -% op2, // SUB
|
||||
};
|
||||
|
||||
// Write to Register
|
||||
if (op != 0b01) cpu.r[rd] = result;
|
||||
|
||||
// Write Flags
|
||||
cpu.cpsr.n.write(result >> 31 & 1 == 1);
|
||||
cpu.cpsr.z.write(result == 0);
|
||||
const offset = @truncate(u8, opcode);
|
||||
|
||||
switch (op) {
|
||||
0b00 => {}, // MOV | C set by Barrel Shifter, V is unaffected
|
||||
0b01, 0b11 => {
|
||||
// SUB, CMP
|
||||
cpu.cpsr.c.write(op2 <= op1);
|
||||
cpu.cpsr.v.write(((op1 ^ result) & (~op2 ^ result)) >> 31 & 1 == 1);
|
||||
},
|
||||
0b10 => {
|
||||
// ADD
|
||||
cpu.cpsr.c.write(overflow);
|
||||
cpu.cpsr.v.write(((op1 ^ result) & (op2 ^ result)) >> 31 & 1 == 1);
|
||||
0b00 => {
|
||||
// MOV
|
||||
cpu.r[rd] = offset;
|
||||
setLogicOpFlags(true, cpu, offset);
|
||||
},
|
||||
0b01 => cmp(cpu, cpu.r[rd], offset), // CMP
|
||||
0b10 => cpu.r[rd] = add(true, cpu, cpu.r[rd], offset), // ADD
|
||||
0b11 => cpu.r[rd] = sub(true, cpu, cpu.r[rd], offset), // SUB
|
||||
}
|
||||
}
|
||||
}.inner;
|
||||
|
||||
@ -17,7 +17,7 @@ pub fn fmt17() InstrFn {
|
||||
cpu.r[14] = ret_addr; // Resume Execution
|
||||
cpu.spsr.raw = cpsr; // Previous mode CPSR
|
||||
cpu.r[15] = 0x0000_0008;
|
||||
cpu.pipe.reload(cpu);
|
||||
cpu.pipe.reload(u32, cpu);
|
||||
}
|
||||
}.inner;
|
||||
}
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user