feat(cpu): implement format 13

While bugs do exist, at this point all THUMB and ARMv4 instructions
have been implemented! Yay!

src/cpu.zig

@@ -31,11 +31,13 @@ const format6 = @import("cpu/thumb/format6.zig").format6;
 const format78 = @import("cpu/thumb/format78.zig").format78;
 const format9 = @import("cpu/thumb/format9.zig").format9;
 const format10 = @import("cpu/thumb/format10.zig").format10;
+const format11 = @import("cpu/thumb/format11.zig").format11;
 const format12 = @import("cpu/thumb/format12.zig").format12;
 const format13 = @import("cpu/thumb/format13.zig").format13;
 const format14 = @import("cpu/thumb/format14.zig").format14;
 const format15 = @import("cpu/thumb/format15.zig").format15;
 const format16 = @import("cpu/thumb/format16.zig").format16;
+const format17 = @import("cpu/thumb/format17.zig").format17;
 const format18 = @import("cpu/thumb/format18.zig").format18;
 const format19 = @import("cpu/thumb/format19.zig").format19;
 
@@ -478,16 +480,17 @@ fn thumbPopulate() [0x400]ThumbInstrFn {
 
                 lut[i] = format13(S);
             } else if (i >> 2 & 0xFF == 0xDF) {
-                // Format 17 | Software Interrupt
+                lut[i] = format17();
-                lut[i] = thumbUndefined;
             } else if (i >> 6 & 0xF == 0b1000) {
                 const L = i >> 5 & 1 == 1;
                 const offset = i & 0x1F;
 
                 lut[i] = format10(L, offset);
             } else if (i >> 6 & 0xF == 0b1001) {
-                // Format 11 | SP-relative load / store
+                const L = i >> 5 & 1 == 1;
-                lut[i] = thumbUndefined;
+                const rd = i >> 2 & 0x3;
+
+                lut[i] = format11(L, rd);
             } else if (i >> 6 & 0xF == 0b1010) {
                 const isSP = i >> 5 & 1 == 1;
                 const rd = i >> 2 & 0x7;

src/cpu/thumb/format11.zig

@@ -0,0 +1,21 @@
+const std = @import("std");
+
+const Bus = @import("../../Bus.zig");
+const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
+const InstrFn = @import("../../cpu.zig").ThumbInstrFn;
+
+pub fn format11(comptime L: bool, comptime rd: u3) InstrFn {
+    return struct {
+        fn inner(cpu: *Arm7tdmi, bus: *Bus, opcode: u16) void {
+            const offset = (opcode & 0xFF) << 2;
+            const address = cpu.r[13] + offset;
+
+            if (L) {
+                const value = bus.read32(address & 0xFFFF_FFFC);
+                cpu.r[rd] = std.math.rotr(u32, value, 8 * (address & 0x3));
+            } else {
+                bus.write32(address & 0xFFFF_FFFC, cpu.r[rd]);
+            }
+        }
+    }.inner;
+}

src/cpu/thumb/format13.zig

@@ -4,10 +4,11 @@ const Bus = @import("../../Bus.zig");
 const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
 const InstrFn = @import("../../cpu.zig").ThumbInstrFn;
 
-pub fn format13(comptime _: bool) InstrFn {
+pub fn format13(comptime S: bool) InstrFn {
     return struct {
-        fn inner(cpu: *Arm7tdmi, _: *Bus, _: u16) void {
+        fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void {
-            cpu.panic("[CPU|THUMB|Fmt13] Implement Format 13 THUMB Instructions", .{});
+            const offset = (opcode & 0x7F) << 2;
+            cpu.r[13] = if (S) cpu.r[13] - offset else cpu.r[13] + offset;
         }
     }.inner;
 }

src/cpu/thumb/format17.zig

@@ -0,0 +1,24 @@
+const std = @import("std");
+
+const Bus = @import("../../Bus.zig");
+const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
+const InstrFn = @import("../../cpu.zig").ThumbInstrFn;
+
+pub fn format17() InstrFn {
+    return struct {
+        fn inner(cpu: *Arm7tdmi, _: *Bus, _: u16) void {
+            // Copy Values from Current Mode
+            const r15 = cpu.r[15];
+            const cpsr = cpu.cpsr.raw;
+
+            // Switch Mode
+            cpu.changeMode(.Supervisor);
+            cpu.cpsr.t.write(false); // Force ARM Mode
+            cpu.cpsr.i.write(true); // Disable normal interrupts
+
+            cpu.r[14] = r15; // Resume Execution
+            cpu.spsr.raw = cpsr; // Previous mode CPSR
+            cpu.r[15] = 0x0000_0008;
+        }
+    }.inner;
+}