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compare: paoda:7bfb87a8598ef43a5c43ff9bd55483c644abc95a
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225c0f7d55 ... 7bfb87a859

5 changed files with 35 additions and 77 deletions
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89
src/cpu/arm/block_data_transfer.zig
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@ -7,78 +7,43 @@ const InstrFn = @import("../../cpu.zig").ArmInstrFn;
pub fn blockDataTransfer(comptime P: bool, comptime U: bool, comptime S: bool, comptime W: bool, comptime L: bool) InstrFn { pub fn blockDataTransfer(comptime P: bool, comptime U: bool, comptime S: bool, comptime W: bool, comptime L: bool) InstrFn {
return struct { return struct {
fn inner(cpu: *Arm7tdmi, bus: *Bus, opcode: u32) void { fn inner(cpu: *Arm7tdmi, bus: *Bus, opcode: u32) void {
const rn = @truncate(u4, opcode >> 16 & 0xF); const r15_present = opcode >> 15 & 1 == 1;
const rlist = opcode & 0xFFFF; const rn = opcode >> 16 & 0xF;
const r15 = rlist >> 15 & 1 == 1; const base = cpu.r[rn];
var count: u32 = 0; const in_list = opcode >> @truncate(u4, rn) & 1 == 1;
var i: u5 = 0;
var first: u4 = 0;
var write_to_base = true;
while (i < 16) : (i += 1) { var address: u32 = base;
const r = @truncate(u4, 15 - i);
if (rlist >> r & 1 == 1) {
first = r;
count += 1;
}
}
var start = cpu.r[rn];
if (U) { if (U) {
start += if (P) 4 else 0; // Increment
} else { var i: u5 = 0;
start = start - (4 * count) + if (!P) 4 else 0; while (i < 0x10) : (i += 1) {
} if (opcode >> i & 1 == 1) {
if (P) address += 4;
var end = cpu.r[rn]; transfer(cpu, bus, r15_present, i, address);
if (U) { if (!P) address += 4;
end = end + (4 * count) - if (!P) 4 else 0; }
} else {
end -= if (P) 4 else 0;
}
var new_base = cpu.r[rn];
if (U) {
new_base += 4 * count;
} else {
new_base -= 4 * count;
}
var address = start;
if (rlist == 0) {
var pc_addr = cpu.r[rn];
if (U) {
pc_addr += if (P) 4 else 0;
} else {
pc_addr -= 0x40 - if (!P) 4 else 0;
} }
} else {
// Decrement
if (L) { var i: u5 = 0x10;
cpu.r[15] = bus.read32(pc_addr); while (i > 0) : (i -= 1) {
} else { const j = i - 1;
bus.write32(pc_addr, cpu.r[15] + 8);
}
cpu.r[rn] = if (U) cpu.r[rn] + 0x40 else cpu.r[rn] - 0x40; if (opcode >> j & 1 == 1) {
return; if (P) address -= 4;
} transfer(cpu, bus, r15_present, j, address);
if (!P) address -= 4;
i = first;
while (i < 16) : (i += 1) {
if (rlist >> i & 1 == 1) {
transfer(cpu, bus, r15, i, address);
address += 4;
if (W and !L and write_to_base) {
cpu.r[rn] = new_base;
write_to_base = false;
} }
} }
} }
if (W and L and rlist >> rn & 1 == 0) cpu.r[rn] = new_base; if (W) {
if (!L or (L and !in_list)) {
cpu.r[rn] = address;
}
}
} }
fn transfer(cpu: *Arm7tdmi, bus: *Bus, r15_present: bool, i: u5, address: u32) void { fn transfer(cpu: *Arm7tdmi, bus: *Bus, r15_present: bool, i: u5, address: u32) void {

10
src/cpu/arm/half_signed_data_transfer.zig
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@ -45,20 +45,14 @@ pub fn halfAndSignedDataTransfer(comptime P: bool, comptime U: bool, comptime I:
}, },
0b11 => { 0b11 => {
// LDRSH // LDRSH
const value = if (address & 1 == 1) blk: { result = util.u32SignExtend(16, bus.read16(address & 0xFFFF_FFFE));
break :blk util.u32SignExtend(8, bus.read8(address));
} else blk: {
break :blk util.u32SignExtend(16, bus.read16(address));
};
result = std.math.rotr(u32, value, 8 * (address & 1));
}, },
0b00 => unreachable, // SWP 0b00 => unreachable, // SWP
} }
} else { } else {
if (opcode >> 5 & 0x01 == 0x01) { if (opcode >> 5 & 0x01 == 0x01) {
// STRH // STRH
bus.write16(address & 0xFFFF_FFFE, @truncate(u16, cpu.r[rd])); bus.write16(address, @truncate(u16, cpu.r[rd]));
} else unreachable; // SWP } else unreachable; // SWP
} }

4
src/cpu/arm/single_data_swap.zig
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@ -20,8 +20,8 @@ pub fn singleDataSwap(comptime B: bool) InstrFn {
cpu.r[rd] = value; cpu.r[rd] = value;
} else { } else {
// SWP // SWP
const value = std.math.rotr(u32, bus.read32(address & 0xFFFF_FFFC), 8 * (address & 0x3)); const value = std.math.rotr(u32, bus.read32(address), 8 * (address & 0x3));
bus.write32(address & 0xFFFF_FFFC, cpu.r[rm]); bus.write32(address, cpu.r[rm]);
cpu.r[rd] = value; cpu.r[rd] = value;
} }
} }

7
src/cpu/arm/single_data_transfer.zig
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@ -38,12 +38,11 @@ pub fn singleDataTransfer(comptime I: bool, comptime P: bool, comptime U: bool,
} else { } else {
if (B) { if (B) {
// STRB // STRB
const value = if (rd == 0xF) cpu.r[rd] + 8 else cpu.r[rd]; bus.write8(address, @truncate(u8, cpu.r[rd]));
bus.write8(address, @truncate(u8, value));
} else { } else {
// STR // STR
const value = if (rd == 0xF) cpu.r[rd] + 8 else cpu.r[rd]; const force_aligned = address & 0xFFFF_FFFC;
bus.write32(address & 0xFFFF_FFFC, value); bus.write32(force_aligned, cpu.r[rd]);
} }
} }

2
src/cpu/thumb/block_data_transfer.zig
View File

@ -54,7 +54,7 @@ pub fn format15(comptime L: bool, comptime rb: u3) InstrFn {
const end_address = cpu.r[rb] + 4 * countRlist(opcode); const end_address = cpu.r[rb] + 4 * countRlist(opcode);
if (opcode & 0xFF == 0) { if (opcode & 0xFF == 0) {
if (L) cpu.r[15] = bus.read32(address) else bus.write32(address, cpu.r[15] + 4); if (L) cpu.r[15] = bus.read32(address) else bus.write32(address, cpu.r[15] + 4); // TODO: Why is this r[15] + 4?
cpu.r[rb] += 0x40; cpu.r[rb] += 0x40;
return; return;
} }