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2a561aeba3
Author | SHA1 | Date |
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Rekai Nyangadzayi Musuka | 2a561aeba3 |
55
src/ppu.zig
55
src/ppu.zig
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@ -3,12 +3,14 @@ const io = @import("bus/io.zig");
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const EventKind = @import("scheduler.zig").EventKind;
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const EventKind = @import("scheduler.zig").EventKind;
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const Scheduler = @import("scheduler.zig").Scheduler;
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const Scheduler = @import("scheduler.zig").Scheduler;
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const Arm7tdmi = @import("cpu.zig").Arm7tdmi;
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const Bit = @import("bitfield").Bit;
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const Bit = @import("bitfield").Bit;
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const Bitfield = @import("bitfield").Bitfield;
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const Bitfield = @import("bitfield").Bitfield;
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const Allocator = std.mem.Allocator;
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const Allocator = std.mem.Allocator;
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const log = std.log.scoped(.PPU);
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const log = std.log.scoped(.PPU);
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const pollBlankingDma = @import("bus/dma.zig").pollBlankingDma;
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pub const width = 240;
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pub const width = 240;
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pub const height = 160;
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pub const height = 160;
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@ -351,6 +353,59 @@ pub const Ppu = struct {
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},
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},
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};
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};
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}
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}
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pub fn handleHDrawEnd(self: *Self, cpu: *Arm7tdmi) void {
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// Transitioning to a Hblank
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if (self.dispstat.hblank_irq.read()) {
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cpu.bus.io.irq.hblank.set();
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cpu.handleInterrupt();
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}
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// See if HBlank DMA is present and not enabled
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pollBlankingDma(cpu.bus, .HBlank);
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self.dispstat.hblank.set();
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self.sched.push(.HBlank, self.sched.now() + (68 * 4));
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}
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pub fn handleHBlankEnd(self: *Self, cpu: *Arm7tdmi) void {
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// The End of a Hblank (During Draw or Vblank)
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const old_scanline = self.vcount.scanline.read();
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const scanline = (old_scanline + 1) % 228;
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self.vcount.scanline.write(scanline);
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self.dispstat.hblank.unset();
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// Perform Vc == VcT check
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const coincidence = scanline == self.dispstat.vcount_trigger.read();
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self.dispstat.coincidence.write(coincidence);
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if (coincidence and self.dispstat.vcount_irq.read()) {
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cpu.bus.io.irq.coincidence.set();
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cpu.handleInterrupt();
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}
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if (scanline < 160) {
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// Transitioning to another Draw
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self.sched.push(.Draw, self.sched.now() + (240 * 4));
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} else {
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// Transitioning to a Vblank
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if (scanline == 160) {
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self.dispstat.vblank.set();
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if (self.dispstat.vblank_irq.read()) {
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cpu.bus.io.irq.vblank.set();
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cpu.handleInterrupt();
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}
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// See if Vblank DMA is present and not enabled
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pollBlankingDma(cpu.bus, .VBlank);
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}
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if (scanline == 227) self.dispstat.vblank.unset();
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self.sched.push(.VBlank, self.sched.now() + (240 * 4));
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}
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}
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};
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};
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const Palette = struct {
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const Palette = struct {
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@ -1,7 +1,5 @@
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const std = @import("std");
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const std = @import("std");
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const pollBlankingDma = @import("bus/dma.zig").pollBlankingDma;
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const Bus = @import("Bus.zig");
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const Bus = @import("Bus.zig");
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const Arm7tdmi = @import("cpu.zig").Arm7tdmi;
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const Arm7tdmi = @import("cpu.zig").Arm7tdmi;
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@ -32,92 +30,18 @@ pub const Scheduler = struct {
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}
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}
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pub fn handleEvent(self: *Self, cpu: *Arm7tdmi, bus: *Bus) void {
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pub fn handleEvent(self: *Self, cpu: *Arm7tdmi, bus: *Bus) void {
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const should_handle = if (self.queue.peek()) |e| self.tick >= e.tick else false;
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if (self.queue.removeOrNull()) |event| {
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const stat = &bus.ppu.dispstat;
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const vcount = &bus.ppu.vcount;
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const irq = &bus.io.irq;
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if (should_handle) {
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const event = self.queue.remove();
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// log.debug("Handle {} @ tick = {}", .{ event.kind, self.tick });
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switch (event.kind) {
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switch (event.kind) {
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.HeatDeath => {
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.HeatDeath => {
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log.err("A u64 overflowered. This *actually* should never happen.", .{});
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log.err("A u64 overflowered. This *actually* should never happen.", .{});
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unreachable;
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unreachable;
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},
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},
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.HBlank => {
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// The End of a Hblank (During Draw or Vblank)
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const old_scanline = vcount.scanline.read();
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const scanline = (old_scanline + 1) % 228;
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vcount.scanline.write(scanline);
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stat.hblank.unset();
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// Perform Vc == VcT check
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const coincidence = scanline == stat.vcount_trigger.read();
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stat.coincidence.write(coincidence);
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if (coincidence and stat.vcount_irq.read()) {
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irq.coincidence.set();
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cpu.handleInterrupt();
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}
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if (scanline < 160) {
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// Transitioning to another Draw
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self.push(.Draw, self.tick + (240 * 4));
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} else {
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// Transitioning to a Vblank
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if (scanline == 160) {
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stat.vblank.set();
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if (stat.vblank_irq.read()) {
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irq.vblank.set();
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cpu.handleInterrupt();
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}
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// See if Vblank DMA is present and not enabled
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pollBlankingDma(bus, .VBlank);
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}
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if (scanline == 227) stat.vblank.unset();
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self.push(.VBlank, self.tick + (240 * 4));
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}
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},
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.Draw => {
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.Draw => {
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// The end of a Draw
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// The end of a VDraw
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bus.ppu.drawScanline();
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bus.ppu.drawScanline();
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bus.ppu.handleHDrawEnd(cpu);
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// Transitioning to a Hblank
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if (bus.ppu.dispstat.hblank_irq.read()) {
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bus.io.irq.hblank.set();
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cpu.handleInterrupt();
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}
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// See if Hblank DMA is present and not enabled
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pollBlankingDma(bus, .HBlank);
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bus.ppu.dispstat.hblank.set();
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self.push(.HBlank, self.tick + (68 * 4));
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},
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.VBlank => {
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// The end of a Vblank
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// Transitioning to a Hblank
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if (bus.ppu.dispstat.hblank_irq.read()) {
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bus.io.irq.hblank.set();
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cpu.handleInterrupt();
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}
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// See if Hblank DMA is present and not enabled
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pollBlankingDma(bus, .HBlank);
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bus.ppu.dispstat.hblank.set();
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self.push(.HBlank, self.tick + (68 * 4));
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},
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},
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.TimerOverflow => |id| {
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.TimerOverflow => |id| {
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// log.warn("TIM{} Overflowed", .{id});
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switch (id) {
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switch (id) {
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0 => bus.io.tim0.handleOverflow(cpu, &bus.io),
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0 => bus.io.tim0.handleOverflow(cpu, &bus.io),
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1 => bus.io.tim1.handleOverflow(cpu, &bus.io),
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1 => bus.io.tim1.handleOverflow(cpu, &bus.io),
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@ -125,6 +49,8 @@ pub const Scheduler = struct {
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3 => bus.io.tim3.handleOverflow(cpu, &bus.io),
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3 => bus.io.tim3.handleOverflow(cpu, &bus.io),
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}
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}
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},
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},
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.HBlank => bus.ppu.handleHBlankEnd(cpu), // The end of a HBlank
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.VBlank => bus.ppu.handleHDrawEnd(cpu), // The end of a VBlank
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}
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}
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}
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}
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}
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}
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@ -153,9 +79,9 @@ pub const Scheduler = struct {
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}
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}
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pub fn nextTimestamp(self: *Self) u64 {
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pub fn nextTimestamp(self: *Self) u64 {
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if (self.queue.peek()) |e| {
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if (self.queue.peek()) |e| return e;
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return e.tick;
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} else unreachable;
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unreachable; // There's always the HeatDeath event scheduled
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}
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}
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};
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};
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