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7233be1ca1
Author | SHA1 | Date |
---|---|---|
Rekai Nyangadzayi Musuka | 7233be1ca1 | |
Rekai Nyangadzayi Musuka | b4fcaddf80 | |
Rekai Nyangadzayi Musuka | e496f830f6 | |
Rekai Nyangadzayi Musuka | 5211f0ca70 | |
Rekai Nyangadzayi Musuka | b6e91cbca1 | |
Rekai Nyangadzayi Musuka | 323753e77a | |
Rekai Nyangadzayi Musuka | 4aa63e318b | |
Rekai Nyangadzayi Musuka | 5b75844d88 | |
Rekai Nyangadzayi Musuka | c97abea94a | |
Rekai Nyangadzayi Musuka | 65cfc97f28 | |
Rekai Nyangadzayi Musuka | fa862f095a |
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@ -180,11 +180,11 @@ const Audio = struct {
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export fn callback(userdata: ?*anyopaque, stream: [*c]u8, len: c_int) void {
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const apu = @ptrCast(*Apu, @alignCast(@alignOf(*Apu), userdata));
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const written = SDL.SDL_AudioStreamGet(apu.stream, stream, len);
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_ = SDL.SDL_AudioStreamGet(apu.stream, stream, len);
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// If we don't write anything, play silence otherwise garbage will be played
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// FIXME: I don't think this hack to remove DC Offset is acceptable :thinking:
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if (written == 0) std.mem.set(u8, stream[0..@intCast(usize, len)], 0x40);
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// if (written == 0) std.mem.set(u8, stream[0..@intCast(usize, len)], 0x40);
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}
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};
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@ -163,6 +163,8 @@ pub const Apu = struct {
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fs: FrameSequencer,
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capacitor: f32,
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is_buffer_full: bool,
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pub fn init(sched: *Scheduler) Self {
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const apu: Self = .{
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.ch1 = ToneSweep.init(sched),
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@ -178,11 +180,12 @@ pub const Apu = struct {
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.bias = .{ .raw = 0x0200 },
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.sampling_cycle = 0b00,
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.stream = SDL.SDL_NewAudioStream(SDL.AUDIO_U16, 2, 1 << 15, SDL.AUDIO_U16, 2, host_sample_rate) orelse unreachable,
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.stream = SDL.SDL_NewAudioStream(SDL.AUDIO_U16, 2, 1 << 15, SDL.AUDIO_U16, 2, host_sample_rate).?,
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.sched = sched,
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.capacitor = 0,
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.fs = FrameSequencer.init(),
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.is_buffer_full = false,
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};
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sched.push(.SampleAudio, apu.sampleTicks());
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@ -277,6 +280,13 @@ pub const Apu = struct {
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}
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pub fn sampleAudio(self: *Self, late: u64) void {
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self.sched.push(.SampleAudio, self.sampleTicks() -| late);
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// Whether the APU is busy or not is determined by the main loop in emu.zig
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// This should only ever be true (because this side of the emu is single threaded)
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// When audio sync is disaabled
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if (self.is_buffer_full) return;
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var left: i16 = 0;
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var right: i16 = 0;
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@ -325,28 +335,30 @@ pub const Apu = struct {
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left += bias;
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right += bias;
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const tmp_left = std.math.clamp(@bitCast(u16, left), std.math.minInt(u11), std.math.maxInt(u11));
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const tmp_right = std.math.clamp(@bitCast(u16, right), std.math.minInt(u11), std.math.maxInt(u11));
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const clamped_left = std.math.clamp(@bitCast(u16, left), std.math.minInt(u11), std.math.maxInt(u11));
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const clamped_right = std.math.clamp(@bitCast(u16, right), std.math.minInt(u11), std.math.maxInt(u11));
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// Extend to 16-bit signed audio samples
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const final_left = (tmp_left << 5) | (tmp_left >> 6);
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const final_right = (tmp_right << 5) | (tmp_right >> 6);
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const ext_left = (clamped_left << 5) | (clamped_left >> 6);
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const ext_right = (clamped_right << 5) | (clamped_right >> 6);
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if (self.sampling_cycle != self.bias.sampling_cycle.read()) {
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const new_sample_rate = Self.sampleRate(self.bias.sampling_cycle.read());
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log.info("Sample Rate changed from {}Hz to {}Hz", .{ Self.sampleRate(self.sampling_cycle), new_sample_rate });
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// FIXME: This rarely happens
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if (self.sampling_cycle != self.bias.sampling_cycle.read()) self.replaceSDLResampler();
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// Sample Rate Changed, Create a new Resampler since i can't figure out how to change
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// the parameters of the old one
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const old = self.stream;
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defer SDL.SDL_FreeAudioStream(old);
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self.sampling_cycle = self.bias.sampling_cycle.read();
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self.stream = SDL.SDL_NewAudioStream(SDL.AUDIO_U16, 2, @intCast(c_int, new_sample_rate), SDL.AUDIO_U16, 2, host_sample_rate) orelse unreachable;
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_ = SDL.SDL_AudioStreamPut(self.stream, &[2]u16{ ext_left, ext_right }, 2 * @sizeOf(u16));
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}
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_ = SDL.SDL_AudioStreamPut(self.stream, &[2]u16{ final_left, final_right }, 2 * @sizeOf(u16));
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self.sched.push(.SampleAudio, self.sampleTicks() -| late);
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fn replaceSDLResampler(self: *Self) void {
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const sample_rate = Self.sampleRate(self.bias.sampling_cycle.read());
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log.info("Sample Rate changed from {}Hz to {}Hz", .{ Self.sampleRate(self.sampling_cycle), sample_rate });
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// Sampling Cycle (Sample Rate) changed, Craete a new SDL Audio Resampler
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// FIXME: Replace SDL's Audio Resampler with either a custom or more reliable one
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const old_stream = self.stream;
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defer SDL.SDL_FreeAudioStream(old_stream);
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self.sampling_cycle = self.bias.sampling_cycle.read();
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self.stream = SDL.SDL_NewAudioStream(SDL.AUDIO_U16, 2, @intCast(c_int, sample_rate), SDL.AUDIO_U16, 2, host_sample_rate).?;
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}
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fn sampleTicks(self: *const Self) u64 {
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157
src/core/cpu.zig
157
src/core/cpu.zig
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@ -28,9 +28,14 @@ pub const arm = struct {
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const multiply = @import("cpu/arm/multiply.zig").multiply;
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const multiplyLong = @import("cpu/arm/multiply.zig").multiplyLong;
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/// Determine index into ARM InstrFn LUT
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fn idx(opcode: u32) u12 {
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return @truncate(u12, opcode >> 20 & 0xFF) << 4 | @truncate(u12, opcode >> 4 & 0xF);
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}
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// Undefined ARM Instruction handler
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fn und(cpu: *Arm7tdmi, _: *Bus, opcode: u32) void {
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const id = armIdx(opcode);
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const id = idx(opcode);
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cpu.panic("[CPU/Decode] ID: 0x{X:0>3} 0x{X:0>8} is an illegal opcode", .{ id, opcode });
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}
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@ -120,9 +125,14 @@ pub const thumb = struct {
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const swi = @import("cpu/thumb/software_interrupt.zig").fmt17;
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const branch = @import("cpu/thumb/branch.zig");
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/// Determine index into THUMB InstrFn LUT
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fn idx(opcode: u16) u10 {
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return @truncate(u10, opcode >> 6);
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}
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/// Undefined THUMB Instruction Handler
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fn und(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void {
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const id = thumbIdx(opcode);
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const id = idx(opcode);
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cpu.panic("[CPU/Decode] ID: 0b{b:0>10} 0x{X:0>2} is an illegal opcode", .{ id, opcode });
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}
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@ -233,6 +243,7 @@ pub const Arm7tdmi = struct {
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const Self = @This();
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r: [16]u32,
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pipe: Pipline,
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sched: *Scheduler,
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bus: *Bus,
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cpsr: PSR,
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@ -253,6 +264,7 @@ pub const Arm7tdmi = struct {
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pub fn init(sched: *Scheduler, bus: *Bus, log_file: ?std.fs.File) Self {
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return Self{
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.r = [_]u32{0x00} ** 16,
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.pipe = Pipline.init(),
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.sched = sched,
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.bus = bus,
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.cpsr = .{ .raw = 0x0000_001F },
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@ -312,8 +324,21 @@ pub const Arm7tdmi = struct {
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return self.bus.io.haltcnt == .Halt;
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}
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pub fn setCpsrNoFlush(self: *Self, value: u32) void {
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if (value & 0x1F != self.cpsr.raw & 0x1F) self.changeModeFromIdx(@truncate(u5, value & 0x1F));
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self.cpsr.raw = value;
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}
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pub fn setCpsr(self: *Self, value: u32) void {
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if (value & 0x1F != self.cpsr.raw & 0x1F) self.changeModeFromIdx(@truncate(u5, value & 0x1F));
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const new: PSR = .{ .raw = value };
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if (self.cpsr.t.read() != new.t.read()) {
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// If THUMB to ARM or ARM to THUMB, flush pipeline
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self.r[15] &= if (new.t.read()) ~@as(u32, 1) else ~@as(u32, 3);
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if (new.t.read()) self.pipe.reload(u16, self) else self.pipe.reload(u32, self);
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}
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self.cpsr.raw = value;
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}
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@ -404,31 +429,35 @@ pub const Arm7tdmi = struct {
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pub fn fastBoot(self: *Self) void {
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self.r = std.mem.zeroes([16]u32);
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self.r[0] = 0x08000000;
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self.r[1] = 0x000000EA;
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// self.r[0] = 0x08000000;
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// self.r[1] = 0x000000EA;
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self.r[13] = 0x0300_7F00;
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self.r[15] = 0x0800_0000;
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self.banked_r[bankedIdx(.Irq, .R13)] = 0x0300_7FA0;
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self.banked_r[bankedIdx(.Supervisor, .R13)] = 0x0300_7FE0;
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self.cpsr.raw = 0x6000001F;
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// self.cpsr.raw = 0x6000001F;
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self.cpsr.raw = 0x0000_001F;
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}
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pub fn step(self: *Self) void {
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if (self.cpsr.t.read()) {
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const opcode = self.fetch(u16);
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if (self.cpsr.t.read()) blk: {
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const opcode = @truncate(u16, self.pipe.step(self, u16) orelse break :blk);
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if (cpu_logging) self.logger.?.mgbaLog(self, opcode);
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thumb.lut[thumbIdx(opcode)](self, self.bus, opcode);
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} else {
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const opcode = self.fetch(u32);
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thumb.lut[thumb.idx(opcode)](self, self.bus, opcode);
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} else blk: {
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const opcode = self.pipe.step(self, u32) orelse break :blk;
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if (cpu_logging) self.logger.?.mgbaLog(self, opcode);
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if (checkCond(self.cpsr, @truncate(u4, opcode >> 28))) {
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arm.lut[armIdx(opcode)](self, self.bus, opcode);
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arm.lut[arm.idx(opcode)](self, self.bus, opcode);
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}
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}
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if (!self.pipe.flushed) self.r[15] += if (self.cpsr.t.read()) 2 else @as(u32, 4);
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self.pipe.flushed = false;
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}
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pub fn stepDmaTransfer(self: *Self) bool {
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@ -463,27 +492,26 @@ pub const Arm7tdmi = struct {
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pub fn handleInterrupt(self: *Self) void {
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const should_handle = self.bus.io.ie.raw & self.bus.io.irq.raw;
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if (should_handle != 0) {
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// Return if IME is disabled, CPSR I is set or there is nothing to handle
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if (!self.bus.io.ime or self.cpsr.i.read() or should_handle == 0) return;
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// If pipeline isn't full, return but reschedule the handling of the event
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if (!self.pipe.isFull()) return;
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// log.debug("Handling Interrupt!", .{});
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self.bus.io.haltcnt = .Execute;
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// log.debug("An Interrupt was Fired!", .{});
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// Either IME is not true or I in CPSR is true
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// Don't handle interrupts
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if (!self.bus.io.ime or self.cpsr.i.read()) return;
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// log.debug("An interrupt was Handled!", .{});
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// retAddr.gba says r15 on it's own is off by -04h in both ARM and THUMB mode
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const r15 = self.r[15] + 4;
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const cpsr = self.cpsr.raw;
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const ret_addr = self.r[15] - if (self.cpsr.t.read()) 2 else @as(u32, 4);
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const new_spsr = self.cpsr.raw;
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self.changeMode(.Irq);
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self.cpsr.t.write(false);
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self.cpsr.i.write(true);
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self.r[14] = r15;
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self.spsr.raw = cpsr;
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self.r[15] = 0x000_0018;
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}
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self.r[14] = ret_addr;
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self.spsr.raw = new_spsr;
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self.r[15] = 0x0000_0018;
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self.pipe.reload(u32, self);
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}
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inline fn fetch(self: *Self, comptime T: type) T {
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@ -497,8 +525,12 @@ pub const Arm7tdmi = struct {
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return self.bus.read(T, self.r[15]);
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}
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pub fn fakePC(self: *const Self) u32 {
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return self.r[15] + 4;
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fn debug_log(self: *const Self, file: *const File, opcode: u32) void {
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if (self.binary_log) {
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self.skyLog(file) catch unreachable;
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} else {
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self.mgbaLog(file, opcode) catch unreachable;
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}
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}
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pub fn panic(self: *const Self, comptime format: []const u8, args: anytype) noreturn {
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@ -515,13 +547,15 @@ pub const Arm7tdmi = struct {
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std.debug.print("spsr: 0x{X:0>8} ", .{self.spsr.raw});
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prettyPrintPsr(&self.spsr);
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std.debug.print("pipeline: {??X:0>8}\n", .{self.pipe.stage});
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if (self.cpsr.t.read()) {
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const opcode = self.bus.dbgRead(u16, self.r[15] - 4);
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const id = thumbIdx(opcode);
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const id = thumb.idx(opcode);
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std.debug.print("opcode: ID: 0x{b:0>10} 0x{X:0>4}\n", .{ id, opcode });
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} else {
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const opcode = self.bus.dbgRead(u32, self.r[15] - 4);
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const id = armIdx(opcode);
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const id = arm.idx(opcode);
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std.debug.print("opcode: ID: 0x{X:0>3} 0x{X:0>8}\n", .{ id, opcode });
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}
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@ -578,7 +612,7 @@ pub const Arm7tdmi = struct {
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const r12 = self.r[12];
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const r13 = self.r[13];
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const r14 = self.r[14];
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const r15 = self.r[15];
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const r15 = self.r[15] -| if (self.cpsr.t.read()) 2 else @as(u32, 4);
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const c_psr = self.cpsr.raw;
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@ -586,7 +620,7 @@ pub const Arm7tdmi = struct {
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if (self.cpsr.t.read()) {
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if (opcode >> 11 == 0x1E) {
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// Instruction 1 of a BL Opcode, print in ARM mode
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const other_half = self.bus.dbgRead(u16, self.r[15]);
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const other_half = self.bus.debugRead(u16, self.r[15] - 2);
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const bl_opcode = @as(u32, opcode) << 16 | other_half;
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log_str = try std.fmt.bufPrint(&buf, arm_fmt, .{ r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r13, r14, r15, c_psr, bl_opcode });
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@ -601,14 +635,6 @@ pub const Arm7tdmi = struct {
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}
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};
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inline fn armIdx(opcode: u32) u12 {
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return @truncate(u12, opcode >> 20 & 0xFF) << 4 | @truncate(u12, opcode >> 4 & 0xF);
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}
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inline fn thumbIdx(opcode: u16) u10 {
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return @truncate(u10, opcode >> 6);
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}
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pub fn checkCond(cpsr: PSR, cond: u4) bool {
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return switch (cond) {
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0x0 => cpsr.z.read(), // EQ - Equal
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@ -630,6 +656,59 @@ pub fn checkCond(cpsr: PSR, cond: u4) bool {
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};
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}
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const Pipline = struct {
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const Self = @This();
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stage: [2]?u32,
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flushed: bool,
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fn init() Self {
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return .{
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.stage = [_]?u32{null} ** 2,
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.flushed = false,
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};
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}
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pub fn flush(self: *Self) void {
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for (self.stage) |*opcode| opcode.* = null;
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self.flushed = true;
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// Note: If using this, add
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// if (!self.pipe.flushed) self.r[15] += if (self.cpsr.t.read()) 2 else @as(u32, 4);
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// to the end of Arm7tdmi.step
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}
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pub fn isFull(self: *const Self) bool {
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return self.stage[0] != null and self.stage[1] != null;
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}
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pub fn step(self: *Self, cpu: *Arm7tdmi, comptime T: type) ?u32 {
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comptime std.debug.assert(T == u32 or T == u16);
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// FIXME: https://github.com/ziglang/zig/issues/12642
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const opcode = self.stage[0..1][0];
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self.stage[0] = self.stage[1];
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self.stage[1] = cpu.bus.read(T, cpu.r[15]);
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return opcode;
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}
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pub fn reload(self: *Self, comptime T: type, cpu: *Arm7tdmi) void {
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comptime std.debug.assert(T == u32 or T == u16);
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// Sometimes, the pipeline can be reloaded twice in the same instruction
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// This can happen if:
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// 1. R15 is written to
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// 2. The CPSR is written to (and T changes), so R15 is written to again
|
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|
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self.stage[0] = cpu.bus.read(T, cpu.r[15]);
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self.stage[1] = cpu.bus.read(T, cpu.r[15] + if (T == u32) 4 else @as(u32, 2));
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||||
|
||||
cpu.r[15] += if (T == u32) 8 else @as(u32, 4);
|
||||
self.flushed = true;
|
||||
}
|
||||
};
|
||||
|
||||
pub const PSR = extern union {
|
||||
mode: Bitfield(u32, 0, 5),
|
||||
t: Bit(u32, 5),
|
||||
|
|
|
@ -55,8 +55,10 @@ pub fn blockDataTransfer(comptime P: bool, comptime U: bool, comptime S: bool, c
|
|||
|
||||
if (L) {
|
||||
cpu.r[15] = bus.read(u32, und_addr);
|
||||
cpu.pipe.reload(u32, cpu);
|
||||
} else {
|
||||
bus.write(u32, und_addr, cpu.r[15] + 8);
|
||||
// FIXME: Should r15 on write be +12 ahead?
|
||||
bus.write(u32, und_addr, cpu.r[15] + 4);
|
||||
}
|
||||
|
||||
cpu.r[rn] = if (U) cpu.r[rn] + 0x40 else cpu.r[rn] - 0x40;
|
||||
|
@ -86,17 +88,23 @@ pub fn blockDataTransfer(comptime P: bool, comptime U: bool, comptime S: bool, c
|
|||
cpu.setUserModeRegister(i, bus.read(u32, address));
|
||||
} else {
|
||||
const value = bus.read(u32, address);
|
||||
cpu.r[i] = if (i == 0xF) value & 0xFFFF_FFFC else value;
|
||||
if (S and i == 0xF) cpu.setCpsr(cpu.spsr.raw);
|
||||
|
||||
cpu.r[i] = value;
|
||||
if (i == 0xF) {
|
||||
cpu.r[i] &= ~@as(u32, 3); // Align r15
|
||||
cpu.pipe.reload(u32, cpu);
|
||||
|
||||
if (S) cpu.setCpsr(cpu.spsr.raw);
|
||||
}
|
||||
}
|
||||
} else {
|
||||
if (S) {
|
||||
// Always Transfer User mode Registers
|
||||
// This happens regardless if r15 is in the list
|
||||
const value = cpu.getUserModeRegister(i);
|
||||
bus.write(u32, address, value + if (i == 0xF) 8 else @as(u32, 0)); // PC is already 4 ahead to make 12
|
||||
bus.write(u32, address, value + if (i == 0xF) 4 else @as(u32, 0)); // PC is already 8 ahead to make 12
|
||||
} else {
|
||||
bus.write(u32, address, cpu.r[i] + if (i == 0xF) 8 else @as(u32, 0));
|
||||
bus.write(u32, address, cpu.r[i] + if (i == 0xF) 4 else @as(u32, 0));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
@ -9,14 +9,20 @@ const sext = @import("../../util.zig").sext;
|
|||
pub fn branch(comptime L: bool) InstrFn {
|
||||
return struct {
|
||||
fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u32) void {
|
||||
if (L) cpu.r[14] = cpu.r[15];
|
||||
cpu.r[15] = cpu.fakePC() +% (sext(u32, u24, opcode) << 2);
|
||||
if (L) cpu.r[14] = cpu.r[15] - 4;
|
||||
|
||||
cpu.r[15] +%= sext(u32, u24, opcode) << 2;
|
||||
cpu.pipe.reload(u32, cpu);
|
||||
}
|
||||
}.inner;
|
||||
}
|
||||
|
||||
pub fn branchAndExchange(cpu: *Arm7tdmi, _: *Bus, opcode: u32) void {
|
||||
const rn = opcode & 0xF;
|
||||
cpu.cpsr.t.write(cpu.r[rn] & 1 == 1);
|
||||
cpu.r[15] = cpu.r[rn] & 0xFFFF_FFFE;
|
||||
|
||||
const thumb = cpu.r[rn] & 1 == 1;
|
||||
cpu.r[15] = cpu.r[rn] & if (thumb) ~@as(u32, 1) else ~@as(u32, 3);
|
||||
|
||||
cpu.cpsr.t.write(thumb);
|
||||
if (thumb) cpu.pipe.reload(u16, cpu) else cpu.pipe.reload(u32, cpu);
|
||||
}
|
||||
|
|
|
@ -5,7 +5,7 @@ const InstrFn = @import("../../cpu.zig").arm.InstrFn;
|
|||
const rotateRight = @import("../barrel_shifter.zig").rotateRight;
|
||||
const execute = @import("../barrel_shifter.zig").execute;
|
||||
|
||||
pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime instrKind: u4) InstrFn {
|
||||
pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime kind: u4) InstrFn {
|
||||
return struct {
|
||||
fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u32) void {
|
||||
const rd = @truncate(u4, opcode >> 12 & 0xF);
|
||||
|
@ -13,124 +13,276 @@ pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime instrKind: u4
|
|||
const old_carry = @boolToInt(cpu.cpsr.c.read());
|
||||
|
||||
// If certain conditions are met, PC is 12 ahead instead of 8
|
||||
// TODO: Why these conditions?
|
||||
if (!I and opcode >> 4 & 1 == 1) cpu.r[15] += 4;
|
||||
const op1 = cpu.r[rn];
|
||||
|
||||
const op1 = if (rn == 0xF) cpu.fakePC() else cpu.r[rn];
|
||||
|
||||
var op2: u32 = undefined;
|
||||
if (I) {
|
||||
const amount = @truncate(u8, (opcode >> 8 & 0xF) << 1);
|
||||
op2 = rotateRight(S, &cpu.cpsr, opcode & 0xFF, amount);
|
||||
} else {
|
||||
op2 = execute(S, cpu, opcode);
|
||||
}
|
||||
const op2 = if (I) rotateRight(S, &cpu.cpsr, opcode & 0xFF, amount) else execute(S, cpu, opcode);
|
||||
|
||||
// Undo special condition from above
|
||||
if (!I and opcode >> 4 & 1 == 1) cpu.r[15] -= 4;
|
||||
|
||||
switch (instrKind) {
|
||||
0x0 => {
|
||||
// AND
|
||||
const result = op1 & op2;
|
||||
cpu.r[rd] = result;
|
||||
setArmLogicOpFlags(S, cpu, rd, result);
|
||||
},
|
||||
0x1 => {
|
||||
// EOR
|
||||
const result = op1 ^ op2;
|
||||
cpu.r[rd] = result;
|
||||
setArmLogicOpFlags(S, cpu, rd, result);
|
||||
},
|
||||
0x2 => {
|
||||
// SUB
|
||||
cpu.r[rd] = armSub(S, cpu, rd, op1, op2);
|
||||
},
|
||||
0x3 => {
|
||||
// RSB
|
||||
cpu.r[rd] = armSub(S, cpu, rd, op2, op1);
|
||||
},
|
||||
0x4 => {
|
||||
// ADD
|
||||
cpu.r[rd] = armAdd(S, cpu, rd, op1, op2);
|
||||
},
|
||||
0x5 => {
|
||||
// ADC
|
||||
cpu.r[rd] = armAdc(S, cpu, rd, op1, op2, old_carry);
|
||||
},
|
||||
0x6 => {
|
||||
// SBC
|
||||
cpu.r[rd] = armSbc(S, cpu, rd, op1, op2, old_carry);
|
||||
},
|
||||
0x7 => {
|
||||
// RSC
|
||||
cpu.r[rd] = armSbc(S, cpu, rd, op2, op1, old_carry);
|
||||
},
|
||||
var result: u32 = undefined;
|
||||
var didOverflow: bool = undefined;
|
||||
|
||||
// Perform Data Processing Logic
|
||||
switch (kind) {
|
||||
0x0 => result = op1 & op2, // AND
|
||||
0x1 => result = op1 ^ op2, // EOR
|
||||
0x2 => result = op1 -% op2, // SUB
|
||||
0x3 => result = op2 -% op1, // RSB
|
||||
0x4 => result = newAdd(&didOverflow, op1, op2), // ADD
|
||||
0x5 => result = newAdc(&didOverflow, op1, op2, old_carry), // ADC
|
||||
0x6 => result = newSbc(op1, op2, old_carry), // SBC
|
||||
0x7 => result = newSbc(op2, op1, old_carry), // RSC
|
||||
0x8 => {
|
||||
// TST
|
||||
if (rd == 0xF) {
|
||||
undefinedTestBehaviour(cpu);
|
||||
return;
|
||||
}
|
||||
if (rd == 0xF)
|
||||
return undefinedTestBehaviour(cpu);
|
||||
|
||||
const result = op1 & op2;
|
||||
setTestOpFlags(S, cpu, opcode, result);
|
||||
result = op1 & op2;
|
||||
},
|
||||
0x9 => {
|
||||
// TEQ
|
||||
if (rd == 0xF) {
|
||||
undefinedTestBehaviour(cpu);
|
||||
return;
|
||||
}
|
||||
if (rd == 0xF)
|
||||
return undefinedTestBehaviour(cpu);
|
||||
|
||||
const result = op1 ^ op2;
|
||||
setTestOpFlags(S, cpu, opcode, result);
|
||||
result = op1 ^ op2;
|
||||
},
|
||||
0xA => {
|
||||
// CMP
|
||||
if (rd == 0xF) {
|
||||
undefinedTestBehaviour(cpu);
|
||||
return;
|
||||
}
|
||||
if (rd == 0xF)
|
||||
return undefinedTestBehaviour(cpu);
|
||||
|
||||
cmp(cpu, op1, op2);
|
||||
result = op1 -% op2;
|
||||
},
|
||||
0xB => {
|
||||
// CMN
|
||||
if (rd == 0xF) {
|
||||
undefinedTestBehaviour(cpu);
|
||||
return;
|
||||
if (rd == 0xF)
|
||||
return undefinedTestBehaviour(cpu);
|
||||
|
||||
didOverflow = @addWithOverflow(u32, op1, op2, &result);
|
||||
},
|
||||
0xC => result = op1 | op2, // ORR
|
||||
0xD => result = op2, // MOV
|
||||
0xE => result = op1 & ~op2, // BIC
|
||||
0xF => result = ~op2, // MVN
|
||||
}
|
||||
|
||||
cmn(cpu, op1, op2);
|
||||
},
|
||||
0xC => {
|
||||
// ORR
|
||||
const result = op1 | op2;
|
||||
// Write to Destination Register
|
||||
switch (kind) {
|
||||
0x8, 0x9, 0xA, 0xB => {}, // Test Operations
|
||||
else => {
|
||||
cpu.r[rd] = result;
|
||||
setArmLogicOpFlags(S, cpu, rd, result);
|
||||
if (rd == 0xF) cpu.pipe.reload(u32, cpu);
|
||||
},
|
||||
0xD => {
|
||||
// MOV
|
||||
cpu.r[rd] = op2;
|
||||
setArmLogicOpFlags(S, cpu, rd, op2);
|
||||
}
|
||||
|
||||
// Write Flags
|
||||
switch (kind) {
|
||||
0x0, 0x1, 0xC, 0xD, 0xE, 0xF => {
|
||||
// Logic Operation Flags
|
||||
if (S) {
|
||||
if (rd == 0xF) {
|
||||
cpu.setCpsr(cpu.spsr.raw);
|
||||
} else {
|
||||
cpu.cpsr.n.write(result >> 31 & 1 == 1);
|
||||
cpu.cpsr.z.write(result == 0);
|
||||
// C set by Barrel Shifter, V is unaffected
|
||||
}
|
||||
}
|
||||
},
|
||||
0xE => {
|
||||
// BIC
|
||||
const result = op1 & ~op2;
|
||||
cpu.r[rd] = result;
|
||||
setArmLogicOpFlags(S, cpu, rd, result);
|
||||
0x2, 0x3 => {
|
||||
// SUB, RSB Flags
|
||||
if (S) {
|
||||
cpu.cpsr.n.write(result >> 31 & 1 == 1);
|
||||
cpu.cpsr.z.write(result == 0);
|
||||
|
||||
if (kind == 0x2) {
|
||||
// SUB specific
|
||||
cpu.cpsr.c.write(op2 <= op1);
|
||||
cpu.cpsr.v.write(((op1 ^ result) & (~op2 ^ result)) >> 31 & 1 == 1);
|
||||
} else {
|
||||
// RSB Specific
|
||||
cpu.cpsr.c.write(op1 <= op2);
|
||||
cpu.cpsr.v.write(((op2 ^ result) & (~op1 ^ result)) >> 31 & 1 == 1);
|
||||
}
|
||||
|
||||
if (rd == 0xF) cpu.setCpsr(cpu.spsr.raw);
|
||||
}
|
||||
},
|
||||
0xF => {
|
||||
// MVN
|
||||
const result = ~op2;
|
||||
cpu.r[rd] = result;
|
||||
setArmLogicOpFlags(S, cpu, rd, result);
|
||||
0x4, 0x5 => {
|
||||
// ADD, ADC Flags
|
||||
if (S) {
|
||||
cpu.cpsr.n.write(result >> 31 & 1 == 1);
|
||||
cpu.cpsr.z.write(result == 0);
|
||||
cpu.cpsr.c.write(didOverflow);
|
||||
cpu.cpsr.v.write(((op1 ^ result) & (op2 ^ result)) >> 31 & 1 == 1);
|
||||
|
||||
if (rd == 0xF) cpu.setCpsr(cpu.spsr.raw);
|
||||
}
|
||||
},
|
||||
0x6, 0x7 => {
|
||||
// SBC, RSC Flags
|
||||
if (S) {
|
||||
cpu.cpsr.n.write(result >> 31 & 1 == 1);
|
||||
cpu.cpsr.z.write(result == 0);
|
||||
|
||||
if (kind == 0x6) {
|
||||
// SBC specific
|
||||
const subtrahend = @as(u64, op2) -% old_carry +% 1;
|
||||
cpu.cpsr.c.write(subtrahend <= op1);
|
||||
cpu.cpsr.v.write(((op1 ^ result) & (~op2 ^ result)) >> 31 & 1 == 1);
|
||||
} else {
|
||||
// RSC Specific
|
||||
const subtrahend = @as(u64, op1) -% old_carry +% 1;
|
||||
cpu.cpsr.c.write(subtrahend <= op2);
|
||||
cpu.cpsr.v.write(((op2 ^ result) & (~op1 ^ result)) >> 31 & 1 == 1);
|
||||
}
|
||||
|
||||
if (rd == 0xF) cpu.setCpsr(cpu.spsr.raw);
|
||||
}
|
||||
},
|
||||
0x8, 0x9, 0xA, 0xB => {
|
||||
// Test Operation Flags
|
||||
cpu.cpsr.n.write(result >> 31 & 1 == 1);
|
||||
cpu.cpsr.z.write(result == 0);
|
||||
|
||||
if (kind == 0xA) {
|
||||
// CMP specific
|
||||
cpu.cpsr.c.write(op2 <= op1);
|
||||
cpu.cpsr.v.write(((op1 ^ result) & (~op2 ^ result)) >> 31 & 1 == 1);
|
||||
} else if (kind == 0xB) {
|
||||
// CMN specific
|
||||
cpu.cpsr.c.write(didOverflow);
|
||||
cpu.cpsr.v.write(((op1 ^ result) & (op2 ^ result)) >> 31 & 1 == 1);
|
||||
} else {
|
||||
// TEST, TEQ specific
|
||||
// Barrel Shifter should always calc CPSR C in TST
|
||||
if (!S) _ = execute(true, cpu, opcode);
|
||||
}
|
||||
},
|
||||
}
|
||||
}
|
||||
}.inner;
|
||||
}
|
||||
|
||||
// pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime instrKind: u4) InstrFn {
|
||||
// return struct {
|
||||
// fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u32) void {
|
||||
// const rd = @truncate(u4, opcode >> 12 & 0xF);
|
||||
// const rn = opcode >> 16 & 0xF;
|
||||
// const old_carry = @boolToInt(cpu.cpsr.c.read());
|
||||
|
||||
// // If certain conditions are met, PC is 12 ahead instead of 8
|
||||
// // TODO: What are these conditions? I can't remember
|
||||
// if (!I and opcode >> 4 & 1 == 1) cpu.r[15] += 4;
|
||||
// const op1 = cpu.r[rn];
|
||||
|
||||
// const amount = @truncate(u8, (opcode >> 8 & 0xF) << 1);
|
||||
// const op2 = if (I) rotateRight(S, &cpu.cpsr, opcode & 0xFF, amount) else execute(S, cpu, opcode);
|
||||
|
||||
// // Undo special condition from above
|
||||
// if (!I and opcode >> 4 & 1 == 1) cpu.r[15] -= 4;
|
||||
|
||||
// switch (instrKind) {
|
||||
// 0x0 => {
|
||||
// // AND
|
||||
// const result = op1 & op2;
|
||||
// cpu.r[rd] = result;
|
||||
// setArmLogicOpFlags(S, cpu, rd, result);
|
||||
// },
|
||||
// 0x1 => {
|
||||
// // EOR
|
||||
// const result = op1 ^ op2;
|
||||
// cpu.r[rd] = result;
|
||||
// setArmLogicOpFlags(S, cpu, rd, result);
|
||||
// },
|
||||
// 0x2 => {
|
||||
// // SUB
|
||||
// cpu.r[rd] = armSub(S, cpu, rd, op1, op2);
|
||||
// },
|
||||
// 0x3 => {
|
||||
// // RSB
|
||||
// cpu.r[rd] = armSub(S, cpu, rd, op2, op1);
|
||||
// },
|
||||
// 0x4 => {
|
||||
// // ADD
|
||||
// cpu.r[rd] = armAdd(S, cpu, rd, op1, op2);
|
||||
// },
|
||||
// 0x5 => {
|
||||
// // ADC
|
||||
// cpu.r[rd] = armAdc(S, cpu, rd, op1, op2, old_carry);
|
||||
// },
|
||||
// 0x6 => {
|
||||
// // SBC
|
||||
// cpu.r[rd] = armSbc(S, cpu, rd, op1, op2, old_carry);
|
||||
// },
|
||||
// 0x7 => {
|
||||
// // RSC
|
||||
// cpu.r[rd] = armSbc(S, cpu, rd, op2, op1, old_carry);
|
||||
// },
|
||||
// 0x8 => {
|
||||
// // TST
|
||||
// if (rd == 0xF)
|
||||
// return undefinedTestBehaviour(cpu);
|
||||
|
||||
// const result = op1 & op2;
|
||||
// setTestOpFlags(S, cpu, opcode, result);
|
||||
// },
|
||||
// 0x9 => {
|
||||
// // TEQ
|
||||
// if (rd == 0xF)
|
||||
// return undefinedTestBehaviour(cpu);
|
||||
|
||||
// const result = op1 ^ op2;
|
||||
// setTestOpFlags(S, cpu, opcode, result);
|
||||
// },
|
||||
// 0xA => {
|
||||
// // CMP
|
||||
// if (rd == 0xF)
|
||||
// return undefinedTestBehaviour(cpu);
|
||||
|
||||
// cmp(cpu, op1, op2);
|
||||
// },
|
||||
// 0xB => {
|
||||
// // CMN
|
||||
// if (rd == 0xF)
|
||||
// return undefinedTestBehaviour(cpu);
|
||||
|
||||
// cmn(cpu, op1, op2);
|
||||
// },
|
||||
// 0xC => {
|
||||
// // ORR
|
||||
// const result = op1 | op2;
|
||||
// cpu.r[rd] = result;
|
||||
// setArmLogicOpFlags(S, cpu, rd, result);
|
||||
// },
|
||||
// 0xD => {
|
||||
// // MOV
|
||||
// cpu.r[rd] = op2;
|
||||
// setArmLogicOpFlags(S, cpu, rd, op2);
|
||||
// },
|
||||
// 0xE => {
|
||||
// // BIC
|
||||
// const result = op1 & ~op2;
|
||||
// cpu.r[rd] = result;
|
||||
// setArmLogicOpFlags(S, cpu, rd, result);
|
||||
// },
|
||||
// 0xF => {
|
||||
// // MVN
|
||||
// const result = ~op2;
|
||||
// cpu.r[rd] = result;
|
||||
// setArmLogicOpFlags(S, cpu, rd, result);
|
||||
// },
|
||||
// }
|
||||
|
||||
// if (rd == 0xF) cpu.pipe.reload(u32, cpu);
|
||||
// }
|
||||
// }.inner;
|
||||
// }
|
||||
|
||||
fn armSbc(comptime S: bool, cpu: *Arm7tdmi, rd: u4, left: u32, right: u32, old_carry: u1) u32 {
|
||||
var result: u32 = undefined;
|
||||
if (S and rd == 0xF) {
|
||||
|
@ -143,6 +295,14 @@ fn armSbc(comptime S: bool, cpu: *Arm7tdmi, rd: u4, left: u32, right: u32, old_c
|
|||
return result;
|
||||
}
|
||||
|
||||
fn newSbc(left: u32, right: u32, old_carry: u1) u32 {
|
||||
// TODO: Make your own version (thanks peach.bot)
|
||||
const subtrahend = @as(u64, right) -% old_carry +% 1;
|
||||
const ret = @truncate(u32, left -% subtrahend);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
pub fn sbc(comptime S: bool, cpu: *Arm7tdmi, left: u32, right: u32, old_carry: u1) u32 {
|
||||
// TODO: Make your own version (thanks peach.bot)
|
||||
const subtrahend = @as(u64, right) -% old_carry +% 1;
|
||||
|
@ -195,6 +355,12 @@ fn armAdd(comptime S: bool, cpu: *Arm7tdmi, rd: u4, left: u32, right: u32) u32 {
|
|||
return result;
|
||||
}
|
||||
|
||||
fn newAdd(didOverflow: *bool, left: u32, right: u32) u32 {
|
||||
var ret: u32 = undefined;
|
||||
didOverflow.* = @addWithOverflow(u32, left, right, &ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
pub fn add(comptime S: bool, cpu: *Arm7tdmi, left: u32, right: u32) u32 {
|
||||
var result: u32 = undefined;
|
||||
const didOverflow = @addWithOverflow(u32, left, right, &result);
|
||||
|
@ -221,6 +387,15 @@ fn armAdc(comptime S: bool, cpu: *Arm7tdmi, rd: u4, left: u32, right: u32, old_c
|
|||
return result;
|
||||
}
|
||||
|
||||
fn newAdc(didOverflow: *bool, left: u32, right: u32, old_carry: u1) u32 {
|
||||
var ret: u32 = undefined;
|
||||
const did = @addWithOverflow(u32, left, right, &ret);
|
||||
const overflow = @addWithOverflow(u32, ret, old_carry, &ret);
|
||||
|
||||
didOverflow.* = did or overflow;
|
||||
return ret;
|
||||
}
|
||||
|
||||
pub fn adc(comptime S: bool, cpu: *Arm7tdmi, left: u32, right: u32, old_carry: u1) u32 {
|
||||
var result: u32 = undefined;
|
||||
const did = @addWithOverflow(u32, left, right, &result);
|
||||
|
@ -280,5 +455,5 @@ fn setTestOpFlags(comptime S: bool, cpu: *Arm7tdmi, opcode: u32, result: u32) vo
|
|||
|
||||
fn undefinedTestBehaviour(cpu: *Arm7tdmi) void {
|
||||
@setCold(true);
|
||||
cpu.setCpsr(cpu.spsr.raw);
|
||||
cpu.setCpsrNoFlush(cpu.spsr.raw);
|
||||
}
|
||||
|
|
|
@ -15,20 +15,8 @@ pub fn halfAndSignedDataTransfer(comptime P: bool, comptime U: bool, comptime I:
|
|||
const rm = opcode & 0xF;
|
||||
const imm_offset_high = opcode >> 8 & 0xF;
|
||||
|
||||
var base: u32 = undefined;
|
||||
if (rn == 0xF) {
|
||||
base = cpu.fakePC();
|
||||
if (!L) base += 4;
|
||||
} else {
|
||||
base = cpu.r[rn];
|
||||
}
|
||||
|
||||
var offset: u32 = undefined;
|
||||
if (I) {
|
||||
offset = imm_offset_high << 4 | rm;
|
||||
} else {
|
||||
offset = cpu.r[rm];
|
||||
}
|
||||
const base = cpu.r[rn] + if (!L and rn == 0xF) 4 else @as(u32, 0);
|
||||
const offset = if (I) imm_offset_high << 4 | rm else cpu.r[rm];
|
||||
|
||||
const modified_base = if (U) base +% offset else base -% offset;
|
||||
var address = if (P) modified_base else base;
|
||||
|
|
|
@ -14,13 +14,8 @@ pub fn singleDataTransfer(comptime I: bool, comptime P: bool, comptime U: bool,
|
|||
const rn = opcode >> 16 & 0xF;
|
||||
const rd = opcode >> 12 & 0xF;
|
||||
|
||||
var base: u32 = undefined;
|
||||
if (rn == 0xF) {
|
||||
base = cpu.fakePC();
|
||||
if (!L) base += 4; // Offset of 12
|
||||
} else {
|
||||
base = cpu.r[rn];
|
||||
}
|
||||
// rn is r15 and L is not set, the PC is 12 ahead
|
||||
const base = cpu.r[rn] + if (!L and rn == 0xF) 4 else @as(u32, 0);
|
||||
|
||||
const offset = if (I) shifter.immShift(false, cpu, opcode) else opcode & 0xFFF;
|
||||
|
||||
|
@ -40,18 +35,26 @@ pub fn singleDataTransfer(comptime I: bool, comptime P: bool, comptime U: bool,
|
|||
} else {
|
||||
if (B) {
|
||||
// STRB
|
||||
const value = if (rd == 0xF) cpu.r[rd] + 8 else cpu.r[rd];
|
||||
const value = cpu.r[rd] + if (rd == 0xF) 4 else @as(u32, 0); // PC is 12 ahead
|
||||
bus.write(u8, address, @truncate(u8, value));
|
||||
} else {
|
||||
// STR
|
||||
const value = if (rd == 0xF) cpu.r[rd] + 8 else cpu.r[rd];
|
||||
const value = cpu.r[rd] + if (rd == 0xF) 4 else @as(u32, 0);
|
||||
bus.write(u32, address, value);
|
||||
}
|
||||
}
|
||||
|
||||
address = modified_base;
|
||||
if (W and P or !P) cpu.r[rn] = address;
|
||||
if (L) cpu.r[rd] = result; // This emulates the LDR rd == rn behaviour
|
||||
if (W and P or !P) {
|
||||
cpu.r[rn] = address;
|
||||
if (rn == 0xF) cpu.pipe.reload(u32, cpu);
|
||||
}
|
||||
|
||||
if (L) {
|
||||
// This emulates the LDR rd == rn behaviour
|
||||
cpu.r[rd] = result;
|
||||
if (rd == 0xF) cpu.pipe.reload(u32, cpu);
|
||||
}
|
||||
}
|
||||
}.inner;
|
||||
}
|
||||
|
|
|
@ -6,7 +6,7 @@ pub fn armSoftwareInterrupt() InstrFn {
|
|||
return struct {
|
||||
fn inner(cpu: *Arm7tdmi, _: *Bus, _: u32) void {
|
||||
// Copy Values from Current Mode
|
||||
const r15 = cpu.r[15];
|
||||
const ret_addr = cpu.r[15] - 4;
|
||||
const cpsr = cpu.cpsr.raw;
|
||||
|
||||
// Switch Mode
|
||||
|
@ -14,9 +14,10 @@ pub fn armSoftwareInterrupt() InstrFn {
|
|||
cpu.cpsr.t.write(false); // Force ARM Mode
|
||||
cpu.cpsr.i.write(true); // Disable normal interrupts
|
||||
|
||||
cpu.r[14] = r15; // Resume Execution
|
||||
cpu.r[14] = ret_addr; // Resume Execution
|
||||
cpu.spsr.raw = cpsr; // Previous mode CPSR
|
||||
cpu.r[15] = 0x0000_0008;
|
||||
cpu.pipe.reload(u32, cpu);
|
||||
}
|
||||
}.inner;
|
||||
}
|
||||
|
|
|
@ -18,11 +18,9 @@ pub fn execute(comptime S: bool, cpu: *Arm7tdmi, opcode: u32) u32 {
|
|||
|
||||
fn registerShift(comptime S: bool, cpu: *Arm7tdmi, opcode: u32) u32 {
|
||||
const rs_idx = opcode >> 8 & 0xF;
|
||||
const rm = cpu.r[opcode & 0xF];
|
||||
const rs = @truncate(u8, cpu.r[rs_idx]);
|
||||
|
||||
const rm_idx = opcode & 0xF;
|
||||
const rm = if (rm_idx == 0xF) cpu.fakePC() else cpu.r[rm_idx];
|
||||
|
||||
return switch (@truncate(u2, opcode >> 5)) {
|
||||
0b00 => logicalLeft(S, &cpu.cpsr, rm, rs),
|
||||
0b01 => logicalRight(S, &cpu.cpsr, rm, rs),
|
||||
|
@ -33,9 +31,7 @@ fn registerShift(comptime S: bool, cpu: *Arm7tdmi, opcode: u32) u32 {
|
|||
|
||||
pub fn immShift(comptime S: bool, cpu: *Arm7tdmi, opcode: u32) u32 {
|
||||
const amount = @truncate(u8, opcode >> 7 & 0x1F);
|
||||
|
||||
const rm_idx = opcode & 0xF;
|
||||
const rm = if (rm_idx == 0xF) cpu.fakePC() else cpu.r[rm_idx];
|
||||
const rm = cpu.r[opcode & 0xF];
|
||||
|
||||
var result: u32 = undefined;
|
||||
if (amount == 0) {
|
||||
|
|
|
@ -33,7 +33,8 @@ pub fn fmt14(comptime L: bool, comptime R: bool) InstrFn {
|
|||
if (R) {
|
||||
if (L) {
|
||||
const value = bus.read(u32, address);
|
||||
cpu.r[15] = value & 0xFFFF_FFFE;
|
||||
cpu.r[15] = value & ~@as(u32, 1);
|
||||
cpu.pipe.reload(u16, cpu);
|
||||
} else {
|
||||
bus.write(u32, address, cpu.r[14]);
|
||||
}
|
||||
|
@ -52,7 +53,13 @@ pub fn fmt15(comptime L: bool, comptime rb: u3) InstrFn {
|
|||
const end_address = cpu.r[rb] + 4 * countRlist(opcode);
|
||||
|
||||
if (opcode & 0xFF == 0) {
|
||||
if (L) cpu.r[15] = bus.read(u32, address) else bus.write(u32, address, cpu.r[15] + 4);
|
||||
if (L) {
|
||||
cpu.r[15] = bus.read(u32, address);
|
||||
cpu.pipe.reload(u16, cpu);
|
||||
} else {
|
||||
bus.write(u32, address, cpu.r[15] + 2);
|
||||
}
|
||||
|
||||
cpu.r[rb] += 0x40;
|
||||
return;
|
||||
}
|
||||
|
|
|
@ -9,16 +9,13 @@ pub fn fmt16(comptime cond: u4) InstrFn {
|
|||
return struct {
|
||||
fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void {
|
||||
// B
|
||||
const offset = sext(u32, u8, opcode & 0xFF) << 1;
|
||||
if (cond == 0xE or cond == 0xF)
|
||||
cpu.panic("[CPU/THUMB.16] Undefined conditional branch with condition {}", .{cond});
|
||||
|
||||
const should_execute = switch (cond) {
|
||||
0xE, 0xF => cpu.panic("[CPU/THUMB.16] Undefined conditional branch with condition {}", .{cond}),
|
||||
else => checkCond(cpu.cpsr, cond),
|
||||
};
|
||||
if (!checkCond(cpu.cpsr, cond)) return;
|
||||
|
||||
if (should_execute) {
|
||||
cpu.r[15] = (cpu.r[15] + 2) +% offset;
|
||||
}
|
||||
cpu.r[15] +%= sext(u32, u8, opcode & 0xFF) << 1;
|
||||
cpu.pipe.reload(u16, cpu);
|
||||
}
|
||||
}.inner;
|
||||
}
|
||||
|
@ -27,8 +24,8 @@ pub fn fmt18() InstrFn {
|
|||
return struct {
|
||||
// B but conditional
|
||||
fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void {
|
||||
const offset = sext(u32, u11, opcode & 0x7FF) << 1;
|
||||
cpu.r[15] = (cpu.r[15] + 2) +% offset;
|
||||
cpu.r[15] +%= sext(u32, u11, opcode & 0x7FF) << 1;
|
||||
cpu.pipe.reload(u16, cpu);
|
||||
}
|
||||
}.inner;
|
||||
}
|
||||
|
@ -41,13 +38,16 @@ pub fn fmt19(comptime is_low: bool) InstrFn {
|
|||
|
||||
if (is_low) {
|
||||
// Instruction 2
|
||||
const old_pc = cpu.r[15];
|
||||
const next_opcode = cpu.r[15] - 2;
|
||||
|
||||
cpu.r[15] = cpu.r[14] +% (offset << 1);
|
||||
cpu.r[14] = old_pc | 1;
|
||||
cpu.r[14] = next_opcode | 1;
|
||||
|
||||
cpu.pipe.reload(u16, cpu);
|
||||
} else {
|
||||
// Instruction 1
|
||||
cpu.r[14] = (cpu.r[15] + 2) +% (sext(u32, u11, offset) << 12);
|
||||
const lr_offset = sext(u32, u11, offset) << 12;
|
||||
cpu.r[14] = (cpu.r[15] +% lr_offset) & ~@as(u32, 1);
|
||||
}
|
||||
}
|
||||
}.inner;
|
||||
|
|
|
@ -10,8 +10,6 @@ const sub = @import("../arm/data_processing.zig").sub;
|
|||
const cmp = @import("../arm/data_processing.zig").cmp;
|
||||
const setLogicOpFlags = @import("../arm/data_processing.zig").setLogicOpFlags;
|
||||
|
||||
const log = std.log.scoped(.Thumb1);
|
||||
|
||||
pub fn fmt1(comptime op: u2, comptime offset: u5) InstrFn {
|
||||
return struct {
|
||||
fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void {
|
||||
|
@ -58,29 +56,38 @@ pub fn fmt1(comptime op: u2, comptime offset: u5) InstrFn {
|
|||
pub fn fmt5(comptime op: u2, comptime h1: u1, comptime h2: u1) InstrFn {
|
||||
return struct {
|
||||
fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void {
|
||||
const src_idx = @as(u4, h2) << 3 | (opcode >> 3 & 0x7);
|
||||
const dst_idx = @as(u4, h1) << 3 | (opcode & 0x7);
|
||||
const rs = @as(u4, h2) << 3 | (opcode >> 3 & 0x7);
|
||||
const rd = @as(u4, h1) << 3 | (opcode & 0x7);
|
||||
|
||||
const src = if (src_idx == 0xF) (cpu.r[src_idx] + 2) & 0xFFFF_FFFE else cpu.r[src_idx];
|
||||
const dst = if (dst_idx == 0xF) (cpu.r[dst_idx] + 2) & 0xFFFF_FFFE else cpu.r[dst_idx];
|
||||
const rs_value = if (rs == 0xF) cpu.r[rs] & ~@as(u32, 1) else cpu.r[rs];
|
||||
const rd_value = if (rd == 0xF) cpu.r[rd] & ~@as(u32, 1) else cpu.r[rd];
|
||||
|
||||
switch (op) {
|
||||
0b00 => {
|
||||
// ADD
|
||||
const sum = add(false, cpu, dst, src);
|
||||
cpu.r[dst_idx] = if (dst_idx == 0xF) sum & 0xFFFF_FFFE else sum;
|
||||
const sum = add(false, cpu, rd_value, rs_value);
|
||||
cpu.r[rd] = if (rd == 0xF) sum & ~@as(u32, 1) else sum;
|
||||
},
|
||||
0b01 => cmp(cpu, dst, src), // CMP
|
||||
0b01 => cmp(cpu, rd_value, rs_value), // CMP
|
||||
0b10 => {
|
||||
// MOV
|
||||
cpu.r[dst_idx] = if (dst_idx == 0xF) src & 0xFFFF_FFFE else src;
|
||||
cpu.r[rd] = if (rd == 0xF) rs_value & ~@as(u32, 1) else rs_value;
|
||||
},
|
||||
0b11 => {
|
||||
// BX
|
||||
cpu.cpsr.t.write(src & 1 == 1);
|
||||
cpu.r[15] = src & 0xFFFF_FFFE;
|
||||
const thumb = rs_value & 1 == 1;
|
||||
cpu.r[15] = rs_value & ~@as(u32, 1);
|
||||
|
||||
cpu.cpsr.t.write(thumb);
|
||||
if (thumb) cpu.pipe.reload(u16, cpu) else cpu.pipe.reload(u32, cpu);
|
||||
|
||||
// TODO: We shouldn't need to worry about the if statement
|
||||
// below, because in BX, rd SBZ (and H1 is guaranteed to be 0)
|
||||
return;
|
||||
},
|
||||
}
|
||||
|
||||
if (rd == 0xF) cpu.pipe.reload(u16, cpu);
|
||||
}
|
||||
}.inner;
|
||||
}
|
||||
|
@ -133,10 +140,9 @@ pub fn fmt12(comptime isSP: bool, comptime rd: u3) InstrFn {
|
|||
return struct {
|
||||
fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void {
|
||||
// ADD
|
||||
const left = if (isSP) cpu.r[13] else (cpu.r[15] + 2) & 0xFFFF_FFFD;
|
||||
const left = if (isSP) cpu.r[13] else cpu.r[15] & ~@as(u32, 2);
|
||||
const right = (opcode & 0xFF) << 2;
|
||||
const result = left + right;
|
||||
cpu.r[rd] = result;
|
||||
cpu.r[rd] = left + right;
|
||||
}
|
||||
}.inner;
|
||||
}
|
||||
|
|
|
@ -11,7 +11,9 @@ pub fn fmt6(comptime rd: u3) InstrFn {
|
|||
fn inner(cpu: *Arm7tdmi, bus: *Bus, opcode: u16) void {
|
||||
// LDR
|
||||
const offset = (opcode & 0xFF) << 2;
|
||||
cpu.r[rd] = bus.read(u32, (cpu.r[15] + 2 & 0xFFFF_FFFD) + offset);
|
||||
|
||||
// Bit 1 of the PC intentionally ignored
|
||||
cpu.r[rd] = bus.read(u32, (cpu.r[15] & ~@as(u32, 2)) + offset);
|
||||
}
|
||||
}.inner;
|
||||
}
|
||||
|
|
|
@ -6,7 +6,7 @@ pub fn fmt17() InstrFn {
|
|||
return struct {
|
||||
fn inner(cpu: *Arm7tdmi, _: *Bus, _: u16) void {
|
||||
// Copy Values from Current Mode
|
||||
const r15 = cpu.r[15];
|
||||
const ret_addr = cpu.r[15] - 2;
|
||||
const cpsr = cpu.cpsr.raw;
|
||||
|
||||
// Switch Mode
|
||||
|
@ -14,9 +14,10 @@ pub fn fmt17() InstrFn {
|
|||
cpu.cpsr.t.write(false); // Force ARM Mode
|
||||
cpu.cpsr.i.write(true); // Disable normal interrupts
|
||||
|
||||
cpu.r[14] = r15; // Resume Execution
|
||||
cpu.r[14] = ret_addr; // Resume Execution
|
||||
cpu.spsr.raw = cpsr; // Previous mode CPSR
|
||||
cpu.r[15] = 0x0000_0008;
|
||||
cpu.pipe.reload(u32, cpu);
|
||||
}
|
||||
}.inner;
|
||||
}
|
||||
|
|
|
@ -70,12 +70,21 @@ pub fn runFrame(sched: *Scheduler, cpu: *Arm7tdmi) void {
|
|||
}
|
||||
}
|
||||
|
||||
fn syncToAudio(cpu: *const Arm7tdmi) void {
|
||||
const stream = cpu.bus.apu.stream;
|
||||
const min_sample_count = 0x800;
|
||||
fn syncToAudio(stream: *SDL.SDL_AudioStream, is_buffer_full: *bool) void {
|
||||
const sample_size = 2 * @sizeOf(u16);
|
||||
const max_buf_size: c_int = 0x400;
|
||||
|
||||
// Busy Loop while we wait for the Audio system to catch up
|
||||
while (SDL.SDL_AudioStreamAvailable(stream) > (@sizeOf(u16) * 2) * min_sample_count) {}
|
||||
// Determine whether the APU is busy right at this moment
|
||||
var still_full: bool = SDL.SDL_AudioStreamAvailable(stream) > sample_size * if (is_buffer_full.*) max_buf_size >> 1 else max_buf_size;
|
||||
defer is_buffer_full.* = still_full; // Update APU Busy status right before exiting scope
|
||||
|
||||
// If Busy is false, there's no need to sync here
|
||||
if (!still_full) return;
|
||||
|
||||
while (true) {
|
||||
still_full = SDL.SDL_AudioStreamAvailable(stream) > sample_size * max_buf_size >> 1;
|
||||
if (!sync_audio or !still_full) break;
|
||||
}
|
||||
}
|
||||
|
||||
pub fn runUnsynchronized(quit: *Atomic(bool), sched: *Scheduler, cpu: *Arm7tdmi, fps: ?*FpsTracker) void {
|
||||
|
@ -86,21 +95,21 @@ pub fn runUnsynchronized(quit: *Atomic(bool), sched: *Scheduler, cpu: *Arm7tdmi,
|
|||
|
||||
while (!quit.load(.SeqCst)) {
|
||||
runFrame(sched, cpu);
|
||||
if (sync_audio) syncToAudio(cpu);
|
||||
syncToAudio(cpu.bus.apu.stream, &cpu.bus.apu.is_buffer_full);
|
||||
|
||||
tracker.tick();
|
||||
}
|
||||
} else {
|
||||
while (!quit.load(.SeqCst)) {
|
||||
runFrame(sched, cpu);
|
||||
if (sync_audio) syncToAudio(cpu);
|
||||
syncToAudio(cpu.bus.apu.stream, &cpu.bus.apu.is_buffer_full);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pub fn runSynchronized(quit: *Atomic(bool), sched: *Scheduler, cpu: *Arm7tdmi, fps: ?*FpsTracker) void {
|
||||
log.info("Emulation thread w/ video sync", .{});
|
||||
var timer = Timer.start() catch unreachable;
|
||||
var timer = Timer.start() catch std.debug.panic("Failed to initialize std.timer.Timer", .{});
|
||||
var wake_time: u64 = frame_period;
|
||||
|
||||
if (fps) |tracker| {
|
||||
|
@ -108,13 +117,14 @@ pub fn runSynchronized(quit: *Atomic(bool), sched: *Scheduler, cpu: *Arm7tdmi, f
|
|||
|
||||
while (!quit.load(.SeqCst)) {
|
||||
runFrame(sched, cpu);
|
||||
const new_wake_time = syncToVideo(&timer, wake_time);
|
||||
const new_wake_time = blockOnVideo(&timer, wake_time);
|
||||
|
||||
// Spin to make up the difference of OS scheduler innacuracies
|
||||
// If we happen to also be syncing to audio, we choose to spin on
|
||||
// the amount of time needed for audio to catch up rather than
|
||||
// our expected wake-up time
|
||||
if (sync_audio) syncToAudio(cpu) else spinLoop(&timer, wake_time);
|
||||
syncToAudio(cpu.bus.apu.stream, &cpu.bus.apu.is_buffer_full);
|
||||
if (!sync_audio) spinLoop(&timer, wake_time);
|
||||
wake_time = new_wake_time;
|
||||
|
||||
tracker.tick();
|
||||
|
@ -122,16 +132,17 @@ pub fn runSynchronized(quit: *Atomic(bool), sched: *Scheduler, cpu: *Arm7tdmi, f
|
|||
} else {
|
||||
while (!quit.load(.SeqCst)) {
|
||||
runFrame(sched, cpu);
|
||||
const new_wake_time = syncToVideo(&timer, wake_time);
|
||||
// see above comment
|
||||
if (sync_audio) syncToAudio(cpu) else spinLoop(&timer, wake_time);
|
||||
const new_wake_time = blockOnVideo(&timer, wake_time);
|
||||
|
||||
// see above comment
|
||||
syncToAudio(cpu.bus.apu.stream, &cpu.bus.apu.is_buffer_full);
|
||||
if (!sync_audio) spinLoop(&timer, wake_time);
|
||||
wake_time = new_wake_time;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
inline fn syncToVideo(timer: *Timer, wake_time: u64) u64 {
|
||||
inline fn blockOnVideo(timer: *Timer, wake_time: u64) u64 {
|
||||
// Use the OS scheduler to put the emulation thread to sleep
|
||||
const maybe_recalc_wake_time = sleep(timer, wake_time);
|
||||
|
||||
|
@ -149,6 +160,8 @@ pub fn runBusyLoop(quit: *Atomic(bool), sched: *Scheduler, cpu: *Arm7tdmi) void
|
|||
runFrame(sched, cpu);
|
||||
spinLoop(&timer, wake_time);
|
||||
|
||||
syncToAudio(cpu.bus.apu.stream, &cpu.bus.apu.is_buffer_full);
|
||||
|
||||
// Update to the new wake time
|
||||
wake_time += frame_period;
|
||||
}
|
||||
|
|
|
@ -127,6 +127,7 @@ pub const Logger = struct {
|
|||
|
||||
pub fn print(self: *Self, comptime format: []const u8, args: anytype) !void {
|
||||
try self.buf.writer().print(format, args);
|
||||
try self.buf.flush(); // FIXME: On panics, whatever is in the buffer isn't written to file
|
||||
}
|
||||
|
||||
pub fn mgbaLog(self: *Self, cpu: *const Arm7tdmi, opcode: u32) void {
|
||||
|
@ -166,7 +167,7 @@ pub const Logger = struct {
|
|||
cpu.r[12],
|
||||
cpu.r[13],
|
||||
cpu.r[14],
|
||||
cpu.r[15],
|
||||
cpu.r[15] - if (cpu.cpsr.t.read()) 2 else @as(u32, 4),
|
||||
cpu.cpsr.raw,
|
||||
opcode,
|
||||
};
|
||||
|
|
Loading…
Reference in New Issue