fix: impl workaround for stage2 miscompilation

I believe this to be necessary in order to get hardware interrupts
working.

thumb.gba test 108 fails but I'm committing anyways (despite the
regression) because this is kind of rebase/merge hell and I have
something that at least sort of works rn

lib/SDL.zig

@@ -1 +1 @@
-Subproject commit 401c50ff3d0b83ad4bd89caf580ce1bd90fb5618
+Subproject commit d66925011971fbe221fc2a7f7cb4cd8c181d9ba3

lib/util/bitfield.zig

@@ -14,7 +14,7 @@ fn PtrCastPreserveCV(comptime T: type, comptime PtrToT: type, comptime NewT: typ
 fn BitType(comptime FieldType: type, comptime ValueType: type, comptime shamt: usize) type {
     const self_bit: FieldType = (1 << shamt);
 
-    return struct {
+    return extern struct {
         bits: Bitfield(FieldType, shamt, 1),
 
         pub fn set(self: anytype) void {
@@ -63,7 +63,7 @@ pub fn Bitfield(comptime FieldType: type, comptime shamt: usize, comptime num_bi
 
     const ValueType = std.meta.Int(.unsigned, num_bits);
 
-    return struct {
+    return extern struct {
         dummy: FieldType,
 
         fn field(self: anytype) PtrCastPreserveCV(@This(), @TypeOf(self), FieldType) {

src/Gui.zig

@@ -11,7 +11,6 @@ const pitch = @import("core/ppu.zig").framebuf_pitch;
 const scale = @import("core/emu.zig").win_scale;
 
 const emu = @import("core/emu.zig");
-const asString = @import("core/util.zig").asString;
 const log = std.log.scoped(.GUI);
 
 const default_title: []const u8 = "ZBA";

src/core/bus/Bios.zig

@@ -13,12 +13,12 @@ alloc: Allocator,
 addr_latch: u32,
 
 pub fn init(alloc: Allocator, maybe_path: ?[]const u8) !Self {
-    var buf: ?[]u8 = null;
+    const buf: ?[]u8 = if (maybe_path) |path| blk: {
-    if (maybe_path) |path| {
         const file = try std.fs.cwd().openFile(path, .{});
         defer file.close();
-        buf = try file.readToEndAlloc(alloc, try file.getEndPos());
+
-    }
+        break :blk try file.readToEndAlloc(alloc, try file.getEndPos());
+    } else null;
 
     return Self{
         .buf = buf,

src/core/bus/backup.zig

@@ -3,7 +3,7 @@ const Allocator = std.mem.Allocator;
 const log = std.log.scoped(.Backup);
 
 const escape = @import("../util.zig").escape;
-const asString = @import("../util.zig").asString;
+const asStringSlice = @import("../util.zig").asStringSlice;
 
 const backup_kinds = [5]Needle{
     .{ .str = "EEPROM_V", .kind = .Eeprom },
@@ -18,7 +18,7 @@ pub const Backup = struct {
 
     buf: []u8,
     alloc: Allocator,
-    kind: BackupKind,
+    kind: Kind,
 
     title: [12]u8,
     save_path: ?[]const u8,
@@ -26,7 +26,15 @@ pub const Backup = struct {
     flash: Flash,
     eeprom: Eeprom,
 
-    pub fn init(alloc: Allocator, kind: BackupKind, title: [12]u8, path: ?[]const u8) !Self {
+    const Kind = enum {
+        Eeprom,
+        Sram,
+        Flash,
+        Flash1M,
+        None,
+    };
+
+    pub fn init(allocator: Allocator, kind: Kind, title: [12]u8, path: ?[]const u8) !Self {
         log.info("Kind: {}", .{kind});
 
         const buf_size: usize = switch (kind) {
@@ -36,24 +44,24 @@ pub const Backup = struct {
             .None, .Eeprom => 0, // EEPROM is handled upon first Read Request to it
         };
 
-        const buf = try alloc.alloc(u8, buf_size);
+        const buf = try allocator.alloc(u8, buf_size);
         std.mem.set(u8, buf, 0xFF);
 
         var backup = Self{
             .buf = buf,
-            .alloc = alloc,
+            .alloc = allocator,
             .kind = kind,
             .title = title,
             .save_path = path,
             .flash = Flash.init(),
-            .eeprom = Eeprom.init(alloc),
+            .eeprom = Eeprom.init(allocator),
         };
 
-        if (backup.save_path) |p| backup.loadSaveFromDisk(p) catch |e| log.err("Failed to load save: {}", .{e});
+        if (backup.save_path) |p| backup.loadSaveFromDisk(allocator, p) catch |e| log.err("Failed to load save: {}", .{e});
         return backup;
     }
 
-    pub fn guessKind(rom: []const u8) ?BackupKind {
+    pub fn guessKind(rom: []const u8) ?Kind {
         for (backup_kinds) |needle| {
             const needle_len = needle.str.len;
 
@@ -67,13 +75,13 @@ pub const Backup = struct {
     }
 
     pub fn deinit(self: Self) void {
-        if (self.save_path) |path| self.writeSaveToDisk(path) catch |e| log.err("Failed to write save: {}", .{e});
+        if (self.save_path) |path| self.writeSaveToDisk(self.alloc, path) catch |e| log.err("Failed to write save: {}", .{e});
         self.alloc.free(self.buf);
     }
 
-    fn loadSaveFromDisk(self: *Self, path: []const u8) !void {
+    fn loadSaveFromDisk(self: *Self, allocator: Allocator, path: []const u8) !void {
-        const file_path = try self.getSaveFilePath(path);
+        const file_path = try self.getSaveFilePath(allocator, path);
-        defer self.alloc.free(file_path);
+        defer allocator.free(file_path);
 
         // FIXME: Don't rely on this lol
         if (std.mem.eql(u8, file_path[file_path.len - 12 .. file_path.len], "untitled.sav")) {
@@ -81,8 +89,8 @@ pub const Backup = struct {
         }
 
         const file: std.fs.File = try std.fs.openFileAbsolute(file_path, .{});
-        const file_buf = try file.readToEndAlloc(self.alloc, try file.getEndPos());
+        const file_buf = try file.readToEndAlloc(allocator, try file.getEndPos());
-        defer self.alloc.free(file_buf);
+        defer allocator.free(file_buf);
 
         switch (self.kind) {
             .Sram, .Flash, .Flash1M => {
@@ -97,7 +105,7 @@ pub const Backup = struct {
                 if (file_buf.len == 0x200 or file_buf.len == 0x2000) {
                     self.eeprom.kind = if (file_buf.len == 0x200) .Small else .Large;
 
-                    self.buf = try self.alloc.alloc(u8, file_buf.len);
+                    self.buf = try allocator.alloc(u8, file_buf.len);
                     std.mem.copy(u8, self.buf, file_buf);
                     return log.info("Loaded Save from {s}", .{file_path});
                 }
@@ -111,23 +119,23 @@ pub const Backup = struct {
         }
     }
 
-    fn getSaveFilePath(self: *const Self, path: []const u8) ![]const u8 {
+    fn getSaveFilePath(self: *const Self, allocator: Allocator, path: []const u8) ![]const u8 {
-        const filename = try self.getSaveFilename();
+        const filename = try self.getSaveFilename(allocator);
-        defer self.alloc.free(filename);
+        defer allocator.free(filename);
 
-        return try std.fs.path.join(self.alloc, &[_][]const u8{ path, filename });
+        return try std.fs.path.join(allocator, &[_][]const u8{ path, filename });
     }
 
-    fn getSaveFilename(self: *const Self) ![]const u8 {
+    fn getSaveFilename(self: *const Self, allocator: Allocator) ![]const u8 {
-        const title = asString(escape(self.title));
+        const title_str = asStringSlice(&escape(self.title));
-        const name = if (title.len != 0) title else "untitled";
+        const name = if (title_str.len != 0) title_str else "untitled";
 
-        return try std.mem.concat(self.alloc, u8, &[_][]const u8{ name, ".sav" });
+        return try std.mem.concat(allocator, u8, &[_][]const u8{ name, ".sav" });
     }
 
-    fn writeSaveToDisk(self: Self, path: []const u8) !void {
+    fn writeSaveToDisk(self: Self, allocator: Allocator, path: []const u8) !void {
-        const file_path = try self.getSaveFilePath(path);
+        const file_path = try self.getSaveFilePath(allocator, path);
-        defer self.alloc.free(file_path);
+        defer allocator.free(file_path);
 
         switch (self.kind) {
             .Sram, .Flash, .Flash1M, .Eeprom => {
@@ -201,21 +209,13 @@ pub const Backup = struct {
     }
 };
 
-const BackupKind = enum {
-    Eeprom,
-    Sram,
-    Flash,
-    Flash1M,
-    None,
-};
-
 const Needle = struct {
     const Self = @This();
 
     str: []const u8,
-    kind: BackupKind,
+    kind: Backup.Kind,
 
-    fn init(str: []const u8, kind: BackupKind) Self {
+    fn init(str: []const u8, kind: Backup.Kind) Self {
         return .{
             .str = str,
             .kind = kind,
@@ -230,7 +230,7 @@ const SaveError = error{
 const Flash = struct {
     const Self = @This();
 
-    state: FlashState,
+    state: State,
 
     id_mode: bool,
     set_bank: bool,
@@ -239,6 +239,12 @@ const Flash = struct {
 
     bank: u1,
 
+    const State = enum {
+        Ready,
+        Set,
+        Command,
+    };
+
     fn init() Self {
         return .{
             .state = .Ready,
@@ -293,12 +299,6 @@ const Flash = struct {
     }
 };
 
-const FlashState = enum {
-    Ready,
-    Set,
-    Command,
-};
-
 const Eeprom = struct {
     const Self = @This();
 

src/core/cpu.zig

@@ -12,7 +12,7 @@ const File = std.fs.File;
 
 // ARM Instructions
 pub const arm = struct {
-    pub const InstrFn = fn (*Arm7tdmi, *Bus, u32) void;
+    pub const InstrFn = *const fn (*Arm7tdmi, *Bus, u32) void;
     const lut: [0x1000]InstrFn = populate();
 
     const processing = @import("cpu/arm/data_processing.zig").dataProcessing;
@@ -110,7 +110,7 @@ pub const arm = struct {
 
 // THUMB Instructions
 pub const thumb = struct {
-    pub const InstrFn = fn (*Arm7tdmi, *Bus, u16) void;
+    pub const InstrFn = *const fn (*Arm7tdmi, *Bus, u16) void;
     const lut: [0x400]InstrFn = populate();
 
     const processing = @import("cpu/thumb/data_processing.zig");
@@ -233,6 +233,7 @@ pub const Arm7tdmi = struct {
     const Self = @This();
 
     r: [16]u32,
+    pipe: Pipline,
     sched: *Scheduler,
     bus: *Bus,
     cpsr: PSR,
@@ -253,6 +254,7 @@ pub const Arm7tdmi = struct {
     pub fn init(sched: *Scheduler, bus: *Bus) Self {
         return Self{
             .r = [_]u32{0x00} ** 16,
+            .pipe = Pipline.init(),
             .sched = sched,
             .bus = bus,
             .cpsr = .{ .raw = 0x0000_001F },
@@ -316,8 +318,21 @@ pub const Arm7tdmi = struct {
         return self.bus.io.haltcnt == .Halt;
     }
 
+    pub fn setCpsrNoFlush(self: *Self, value: u32) void {
+        if (value & 0x1F != self.cpsr.raw & 0x1F) self.changeModeFromIdx(@truncate(u5, value & 0x1F));
+        self.cpsr.raw = value;
+    }
+
     pub fn setCpsr(self: *Self, value: u32) void {
         if (value & 0x1F != self.cpsr.raw & 0x1F) self.changeModeFromIdx(@truncate(u5, value & 0x1F));
+
+        const new: PSR = .{ .raw = value };
+        if (self.cpsr.t.read() != new.t.read()) {
+            // If THUMB to ARM or ARM to THUMB, flush pipeline
+            self.r[15] &= if (new.t.read()) ~@as(u32, 1) else ~@as(u32, 3);
+            if (new.t.read()) self.pipe.reload(u16, self) else self.pipe.reload(u32, self);
+        }
+
         self.cpsr.raw = value;
     }
 
@@ -408,31 +423,36 @@ pub const Arm7tdmi = struct {
     pub fn fastBoot(self: *Self) void {
         self.r = std.mem.zeroes([16]u32);
 
-        self.r[0] = 0x08000000;
+        // self.r[0] = 0x08000000;
-        self.r[1] = 0x000000EA;
+        // self.r[1] = 0x000000EA;
         self.r[13] = 0x0300_7F00;
         self.r[15] = 0x0800_0000;
 
         self.banked_r[bankedIdx(.Irq, .R13)] = 0x0300_7FA0;
         self.banked_r[bankedIdx(.Supervisor, .R13)] = 0x0300_7FE0;
 
-        self.cpsr.raw = 0x6000001F;
+        // self.cpsr.raw = 0x6000001F;
+        self.cpsr.raw = 0x0000_001F;
     }
 
     pub fn step(self: *Self) void {
-        if (self.cpsr.t.read()) {
+        if (self.cpsr.t.read()) blk: {
-            const opcode = self.fetch(u16);
+            const opcode = @truncate(u16, self.pipe.step(self, u16) orelse break :blk);
             if (cpu_logging) self.logger.?.mgbaLog(self, opcode);
 
             thumb.lut[thumbIdx(opcode)](self, self.bus, opcode);
-        } else {
+        } else blk: {
-            const opcode = self.fetch(u32);
+            const opcode = self.pipe.step(self, u32) orelse break :blk;
             if (cpu_logging) self.logger.?.mgbaLog(self, opcode);
 
             if (checkCond(self.cpsr, @truncate(u4, opcode >> 28))) {
                 arm.lut[armIdx(opcode)](self, self.bus, opcode);
             }
         }
+
+        if (self.pipe.flushed) self.r[15] += if (self.cpsr.t.read()) 2 else @as(u32, 4);
+        self.r[15] += if (self.cpsr.t.read()) 2 else @as(u32, 4);
+        self.pipe.flushed = false;
     }
 
     pub fn stepDmaTransfer(self: *Self) bool {
@@ -467,27 +487,26 @@ pub const Arm7tdmi = struct {
     pub fn handleInterrupt(self: *Self) void {
         const should_handle = self.bus.io.ie.raw & self.bus.io.irq.raw;
 
-        if (should_handle != 0) {
+        // Return if IME is disabled, CPSR I is set or there is nothing to handle
+        if (!self.bus.io.ime or self.cpsr.i.read() or should_handle == 0) return;
+
+        // If pipeline isn't full, return but reschedule the handling of the event
+        if (!self.pipe.isFull()) return;
+
+        // log.debug("Handling Interrupt!", .{});
         self.bus.io.haltcnt = .Execute;
-            // log.debug("An Interrupt was Fired!", .{});
 
-            // Either IME is not true or I in CPSR is true
+        const ret_addr = self.r[15] - if (self.cpsr.t.read()) 2 else @as(u32, 4);
-            // Don't handle interrupts
+        const new_spsr = self.cpsr.raw;
-            if (!self.bus.io.ime or self.cpsr.i.read()) return;
-            // log.debug("An interrupt was Handled!", .{});
-
-            // retAddr.gba says r15 on it's own is off by -04h in both ARM and THUMB mode
-            const r15 = self.r[15] + 4;
-            const cpsr = self.cpsr.raw;
 
         self.changeMode(.Irq);
         self.cpsr.t.write(false);
         self.cpsr.i.write(true);
 
-            self.r[14] = r15;
+        self.r[14] = ret_addr;
-            self.spsr.raw = cpsr;
+        self.spsr.raw = new_spsr;
-            self.r[15] = 0x000_0018;
+        self.r[15] = 0x0000_0018;
-        }
+        self.pipe.reload(u32, self);
     }
 
     inline fn fetch(self: *Self, comptime T: type) T {
@@ -501,8 +520,12 @@ pub const Arm7tdmi = struct {
         return self.bus.read(T, self.r[15]);
     }
 
-    pub fn fakePC(self: *const Self) u32 {
+    fn debug_log(self: *const Self, file: *const File, opcode: u32) void {
-        return self.r[15] + 4;
+        if (self.binary_log) {
+            self.skyLog(file) catch unreachable;
+        } else {
+            self.mgbaLog(file, opcode) catch unreachable;
+        }
     }
 
     pub fn panic(self: *const Self, comptime format: []const u8, args: anytype) noreturn {
@@ -582,7 +605,7 @@ pub const Arm7tdmi = struct {
         const r12 = self.r[12];
         const r13 = self.r[13];
         const r14 = self.r[14];
-        const r15 = self.r[15];
+        const r15 = self.r[15] -| if (self.cpsr.t.read()) 2 else @as(u32, 4);
 
         const c_psr = self.cpsr.raw;
 
@@ -590,7 +613,7 @@ pub const Arm7tdmi = struct {
         if (self.cpsr.t.read()) {
             if (opcode >> 11 == 0x1E) {
                 // Instruction 1 of a BL Opcode, print in ARM mode
-                const other_half = self.bus.dbgRead(u16, self.r[15]);
+                const other_half = self.bus.debugRead(u16, self.r[15] - 2);
                 const bl_opcode = @as(u32, opcode) << 16 | other_half;
 
                 log_str = try std.fmt.bufPrint(&buf, arm_fmt, .{ r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r13, r14, r15, c_psr, bl_opcode });
@@ -634,6 +657,57 @@ pub fn checkCond(cpsr: PSR, cond: u4) bool {
     };
 }
 
+const Pipline = struct {
+    const Self = @This();
+    stage: [2]?u32,
+    flushed: bool,
+
+    fn init() Self {
+        return .{
+            .stage = [_]?u32{null} ** 2,
+            .flushed = false,
+        };
+    }
+
+    pub fn flush(self: *Self) void {
+        for (self.stage) |*opcode| opcode.* = null;
+        self.flushed = true;
+
+        // Note: If using this, add
+        // if (!self.pipe.flushed) self.r[15] += if (self.cpsr.t.read()) 2 else @as(u32, 4);
+        // to the end of Arm7tdmi.step
+    }
+
+    pub fn isFull(self: *const Self) bool {
+        return self.stage[0] != null and self.stage[1] != null;
+    }
+
+    pub fn step(self: *Self, cpu: *Arm7tdmi, comptime T: type) ?u32 {
+        comptime std.debug.assert(T == u32 or T == u16);
+
+        // FIXME: https://github.com/ziglang/zig/issues/12642
+        const opcode = self.stage[0..1][0];
+
+        self.stage[0] = self.stage[1];
+        self.stage[1] = cpu.bus.read(T, cpu.r[15]);
+
+        return opcode;
+    }
+
+    pub fn reload(self: *Self, comptime T: type, cpu: *Arm7tdmi) void {
+        comptime std.debug.assert(T == u32 or T == u16);
+
+        // Sometimes, the pipeline can be reloaded twice in the same instruction
+        // This can happen if:
+        // 1. R15 is written to
+        // 2. The CPSR is written to (and T changes), so R15 is written to again
+
+        self.stage[0] = cpu.bus.read(T, cpu.r[15]);
+        self.stage[1] = cpu.bus.read(T, cpu.r[15] + if (T == u32) 4 else @as(u32, 2));
+        self.flushed = true;
+    }
+};
+
 pub const PSR = extern union {
     mode: Bitfield(u32, 0, 5),
     t: Bit(u32, 5),

src/core/cpu/arm/block_data_transfer.zig

@@ -55,8 +55,10 @@ pub fn blockDataTransfer(comptime P: bool, comptime U: bool, comptime S: bool, c
 
                 if (L) {
                     cpu.r[15] = bus.read(u32, und_addr);
+                    cpu.pipe.reload(u32, cpu);
                 } else {
-                    bus.write(u32, und_addr, cpu.r[15] + 8);
+                    // FIXME: Should r15 on write be +12 ahead?
+                    bus.write(u32, und_addr, cpu.r[15] + 4);
                 }
 
                 cpu.r[rn] = if (U) cpu.r[rn] + 0x40 else cpu.r[rn] - 0x40;
@@ -86,17 +88,23 @@ pub fn blockDataTransfer(comptime P: bool, comptime U: bool, comptime S: bool, c
                     cpu.setUserModeRegister(i, bus.read(u32, address));
                 } else {
                     const value = bus.read(u32, address);
-                    cpu.r[i] = if (i == 0xF) value & 0xFFFF_FFFC else value;
+
-                    if (S and i == 0xF) cpu.setCpsr(cpu.spsr.raw);
+                    cpu.r[i] = value;
+                    if (i == 0xF) {
+                        cpu.r[i] &= ~@as(u32, 3); // Align r15
+                        cpu.pipe.reload(u32, cpu);
+
+                        if (S) cpu.setCpsr(cpu.spsr.raw);
+                    }
                 }
             } else {
                 if (S) {
                     // Always Transfer User mode Registers
                     // This happens regardless if r15 is in the list
                     const value = cpu.getUserModeRegister(i);
-                    bus.write(u32, address, value + if (i == 0xF) 8 else @as(u32, 0)); // PC is already 4 ahead to make 12
+                    bus.write(u32, address, value + if (i == 0xF) 4 else @as(u32, 0)); // PC is already 8 ahead to make 12
                 } else {
-                    bus.write(u32, address, cpu.r[i] + if (i == 0xF) 8 else @as(u32, 0));
+                    bus.write(u32, address, cpu.r[i] + if (i == 0xF) 4 else @as(u32, 0));
                 }
             }
         }

src/core/cpu/arm/branch.zig

@@ -9,14 +9,20 @@ const sext = @import("../../util.zig").sext;
 pub fn branch(comptime L: bool) InstrFn {
     return struct {
         fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u32) void {
-            if (L) cpu.r[14] = cpu.r[15];
+            if (L) cpu.r[14] = cpu.r[15] - 4;
-            cpu.r[15] = cpu.fakePC() +% (sext(u32, u24, opcode) << 2);
+
+            cpu.r[15] +%= sext(u32, u24, opcode) << 2;
+            cpu.pipe.reload(u32, cpu);
         }
     }.inner;
 }
 
 pub fn branchAndExchange(cpu: *Arm7tdmi, _: *Bus, opcode: u32) void {
     const rn = opcode & 0xF;
-    cpu.cpsr.t.write(cpu.r[rn] & 1 == 1);
+
-    cpu.r[15] = cpu.r[rn] & 0xFFFF_FFFE;
+    const thumb = cpu.r[rn] & 1 == 1;
+    cpu.r[15] = cpu.r[rn] & if (thumb) ~@as(u32, 1) else ~@as(u32, 3);
+
+    cpu.cpsr.t.write(thumb);
+    if (thumb) cpu.pipe.reload(u16, cpu) else cpu.pipe.reload(u32, cpu);
 }

src/core/cpu/arm/data_processing.zig

@@ -5,7 +5,7 @@ const InstrFn = @import("../../cpu.zig").arm.InstrFn;
 const rotateRight = @import("../barrel_shifter.zig").rotateRight;
 const execute = @import("../barrel_shifter.zig").execute;
 
-pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime instrKind: u4) InstrFn {
+pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime kind: u4) InstrFn {
     return struct {
         fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u32) void {
             const rd = @truncate(u4, opcode >> 12 & 0xF);
@@ -13,124 +13,276 @@ pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime instrKind: u4
             const old_carry = @boolToInt(cpu.cpsr.c.read());
 
             // If certain conditions are met, PC is 12 ahead instead of 8
+            // TODO: Why these conditions?
             if (!I and opcode >> 4 & 1 == 1) cpu.r[15] += 4;
+            const op1 = cpu.r[rn];
 
-            const op1 = if (rn == 0xF) cpu.fakePC() else cpu.r[rn];
-
-            var op2: u32 = undefined;
-            if (I) {
             const amount = @truncate(u8, (opcode >> 8 & 0xF) << 1);
-                op2 = rotateRight(S, &cpu.cpsr, opcode & 0xFF, amount);
+            const op2 = if (I) rotateRight(S, &cpu.cpsr, opcode & 0xFF, amount) else execute(S, cpu, opcode);
-            } else {
-                op2 = execute(S, cpu, opcode);
-            }
 
             // Undo special condition from above
             if (!I and opcode >> 4 & 1 == 1) cpu.r[15] -= 4;
 
-            switch (instrKind) {
+            var result: u32 = undefined;
-                0x0 => {
+            var didOverflow: bool = undefined;
-                    // AND
+
-                    const result = op1 & op2;
+            // Perform Data Processing Logic
-                    cpu.r[rd] = result;
+            switch (kind) {
-                    setArmLogicOpFlags(S, cpu, rd, result);
+                0x0 => result = op1 & op2, // AND
-                },
+                0x1 => result = op1 ^ op2, // EOR
-                0x1 => {
+                0x2 => result = op1 -% op2, // SUB
-                    // EOR
+                0x3 => result = op2 -% op1, // RSB
-                    const result = op1 ^ op2;
+                0x4 => result = newAdd(&didOverflow, op1, op2), // ADD
-                    cpu.r[rd] = result;
+                0x5 => result = newAdc(&didOverflow, op1, op2, old_carry), // ADC
-                    setArmLogicOpFlags(S, cpu, rd, result);
+                0x6 => result = newSbc(op1, op2, old_carry), // SBC
-                },
+                0x7 => result = newSbc(op2, op1, old_carry), // RSC
-                0x2 => {
-                    // SUB
-                    cpu.r[rd] = armSub(S, cpu, rd, op1, op2);
-                },
-                0x3 => {
-                    // RSB
-                    cpu.r[rd] = armSub(S, cpu, rd, op2, op1);
-                },
-                0x4 => {
-                    // ADD
-                    cpu.r[rd] = armAdd(S, cpu, rd, op1, op2);
-                },
-                0x5 => {
-                    // ADC
-                    cpu.r[rd] = armAdc(S, cpu, rd, op1, op2, old_carry);
-                },
-                0x6 => {
-                    // SBC
-                    cpu.r[rd] = armSbc(S, cpu, rd, op1, op2, old_carry);
-                },
-                0x7 => {
-                    // RSC
-                    cpu.r[rd] = armSbc(S, cpu, rd, op2, op1, old_carry);
-                },
                 0x8 => {
                     // TST
-                    if (rd == 0xF) {
+                    if (rd == 0xF)
-                        undefinedTestBehaviour(cpu);
+                        return undefinedTestBehaviour(cpu);
-                        return;
-                    }
 
-                    const result = op1 & op2;
+                    result = op1 & op2;
-                    setTestOpFlags(S, cpu, opcode, result);
                 },
                 0x9 => {
                     // TEQ
-                    if (rd == 0xF) {
+                    if (rd == 0xF)
-                        undefinedTestBehaviour(cpu);
+                        return undefinedTestBehaviour(cpu);
-                        return;
-                    }
 
-                    const result = op1 ^ op2;
+                    result = op1 ^ op2;
-                    setTestOpFlags(S, cpu, opcode, result);
                 },
                 0xA => {
                     // CMP
-                    if (rd == 0xF) {
+                    if (rd == 0xF)
-                        undefinedTestBehaviour(cpu);
+                        return undefinedTestBehaviour(cpu);
-                        return;
-                    }
 
-                    cmp(cpu, op1, op2);
+                    result = op1 -% op2;
                 },
                 0xB => {
                     // CMN
-                    if (rd == 0xF) {
+                    if (rd == 0xF)
-                        undefinedTestBehaviour(cpu);
+                        return undefinedTestBehaviour(cpu);
-                        return;
+
+                    didOverflow = @addWithOverflow(u32, op1, op2, &result);
+                },
+                0xC => result = op1 | op2, // ORR
+                0xD => result = op2, // MOV
+                0xE => result = op1 & ~op2, // BIC
+                0xF => result = ~op2, // MVN
             }
 
-                    cmn(cpu, op1, op2);
+            // Write to Destination Register
-                },
+            switch (kind) {
-                0xC => {
+                0x8, 0x9, 0xA, 0xB => {}, // Test Operations
-                    // ORR
+                else => {
-                    const result = op1 | op2;
                     cpu.r[rd] = result;
-                    setArmLogicOpFlags(S, cpu, rd, result);
+                    if (rd == 0xF) cpu.pipe.reload(u32, cpu);
                 },
-                0xD => {
+            }
-                    // MOV
+
-                    cpu.r[rd] = op2;
+            // Write Flags
-                    setArmLogicOpFlags(S, cpu, rd, op2);
+            switch (kind) {
+                0x0, 0x1, 0xC, 0xD, 0xE, 0xF => {
+                    // Logic Operation Flags
+                    if (S) {
+                        if (rd == 0xF) {
+                            cpu.setCpsr(cpu.spsr.raw);
+                        } else {
+                            cpu.cpsr.n.write(result >> 31 & 1 == 1);
+                            cpu.cpsr.z.write(result == 0);
+                            // C set by Barrel Shifter, V is unaffected
+                        }
+                    }
                 },
-                0xE => {
+                0x2, 0x3 => {
-                    // BIC
+                    // SUB, RSB Flags
-                    const result = op1 & ~op2;
+                    if (S) {
-                    cpu.r[rd] = result;
+                        cpu.cpsr.n.write(result >> 31 & 1 == 1);
-                    setArmLogicOpFlags(S, cpu, rd, result);
+                        cpu.cpsr.z.write(result == 0);
+
+                        if (kind == 0x2) {
+                            // SUB specific
+                            cpu.cpsr.c.write(op2 <= op1);
+                            cpu.cpsr.v.write(((op1 ^ result) & (~op2 ^ result)) >> 31 & 1 == 1);
+                        } else {
+                            // RSB Specific
+                            cpu.cpsr.c.write(op1 <= op2);
+                            cpu.cpsr.v.write(((op2 ^ result) & (~op1 ^ result)) >> 31 & 1 == 1);
+                        }
+
+                        if (rd == 0xF) cpu.setCpsr(cpu.spsr.raw);
+                    }
                 },
-                0xF => {
+                0x4, 0x5 => {
-                    // MVN
+                    // ADD, ADC Flags
-                    const result = ~op2;
+                    if (S) {
-                    cpu.r[rd] = result;
+                        cpu.cpsr.n.write(result >> 31 & 1 == 1);
-                    setArmLogicOpFlags(S, cpu, rd, result);
+                        cpu.cpsr.z.write(result == 0);
+                        cpu.cpsr.c.write(didOverflow);
+                        cpu.cpsr.v.write(((op1 ^ result) & (op2 ^ result)) >> 31 & 1 == 1);
+
+                        if (rd == 0xF) cpu.setCpsr(cpu.spsr.raw);
+                    }
+                },
+                0x6, 0x7 => {
+                    // SBC, RSC Flags
+                    if (S) {
+                        cpu.cpsr.n.write(result >> 31 & 1 == 1);
+                        cpu.cpsr.z.write(result == 0);
+
+                        if (kind == 0x6) {
+                            // SBC specific
+                            const subtrahend = @as(u64, op2) -% old_carry +% 1;
+                            cpu.cpsr.c.write(subtrahend <= op1);
+                            cpu.cpsr.v.write(((op1 ^ result) & (~op2 ^ result)) >> 31 & 1 == 1);
+                        } else {
+                            // RSC Specific
+                            const subtrahend = @as(u64, op1) -% old_carry +% 1;
+                            cpu.cpsr.c.write(subtrahend <= op2);
+                            cpu.cpsr.v.write(((op2 ^ result) & (~op1 ^ result)) >> 31 & 1 == 1);
+                        }
+
+                        if (rd == 0xF) cpu.setCpsr(cpu.spsr.raw);
+                    }
+                },
+                0x8, 0x9, 0xA, 0xB => {
+                    // Test Operation Flags
+                    cpu.cpsr.n.write(result >> 31 & 1 == 1);
+                    cpu.cpsr.z.write(result == 0);
+
+                    if (kind == 0xA) {
+                        // CMP specific
+                        cpu.cpsr.c.write(op2 <= op1);
+                        cpu.cpsr.v.write(((op1 ^ result) & (~op2 ^ result)) >> 31 & 1 == 1);
+                    } else if (kind == 0xB) {
+                        // CMN specific
+                        cpu.cpsr.c.write(didOverflow);
+                        cpu.cpsr.v.write(((op1 ^ result) & (op2 ^ result)) >> 31 & 1 == 1);
+                    } else {
+                        // TEST, TEQ specific
+                        // Barrel Shifter should always calc CPSR C in TST
+                        if (!S) _ = execute(true, cpu, opcode);
+                    }
                 },
             }
         }
     }.inner;
 }
 
+// pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime instrKind: u4) InstrFn {
+//     return struct {
+//         fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u32) void {
+//             const rd = @truncate(u4, opcode >> 12 & 0xF);
+//             const rn = opcode >> 16 & 0xF;
+//             const old_carry = @boolToInt(cpu.cpsr.c.read());
+
+//             // If certain conditions are met, PC is 12 ahead instead of 8
+//             // TODO: What are these conditions? I can't remember
+//             if (!I and opcode >> 4 & 1 == 1) cpu.r[15] += 4;
+//             const op1 = cpu.r[rn];
+
+//             const amount = @truncate(u8, (opcode >> 8 & 0xF) << 1);
+//             const op2 = if (I) rotateRight(S, &cpu.cpsr, opcode & 0xFF, amount) else execute(S, cpu, opcode);
+
+//             // Undo special condition from above
+//             if (!I and opcode >> 4 & 1 == 1) cpu.r[15] -= 4;
+
+//             switch (instrKind) {
+//                 0x0 => {
+//                     // AND
+//                     const result = op1 & op2;
+//                     cpu.r[rd] = result;
+//                     setArmLogicOpFlags(S, cpu, rd, result);
+//                 },
+//                 0x1 => {
+//                     // EOR
+//                     const result = op1 ^ op2;
+//                     cpu.r[rd] = result;
+//                     setArmLogicOpFlags(S, cpu, rd, result);
+//                 },
+//                 0x2 => {
+//                     // SUB
+//                     cpu.r[rd] = armSub(S, cpu, rd, op1, op2);
+//                 },
+//                 0x3 => {
+//                     // RSB
+//                     cpu.r[rd] = armSub(S, cpu, rd, op2, op1);
+//                 },
+//                 0x4 => {
+//                     // ADD
+//                     cpu.r[rd] = armAdd(S, cpu, rd, op1, op2);
+//                 },
+//                 0x5 => {
+//                     // ADC
+//                     cpu.r[rd] = armAdc(S, cpu, rd, op1, op2, old_carry);
+//                 },
+//                 0x6 => {
+//                     // SBC
+//                     cpu.r[rd] = armSbc(S, cpu, rd, op1, op2, old_carry);
+//                 },
+//                 0x7 => {
+//                     // RSC
+//                     cpu.r[rd] = armSbc(S, cpu, rd, op2, op1, old_carry);
+//                 },
+//                 0x8 => {
+//                     // TST
+//                     if (rd == 0xF)
+//                         return undefinedTestBehaviour(cpu);
+
+//                     const result = op1 & op2;
+//                     setTestOpFlags(S, cpu, opcode, result);
+//                 },
+//                 0x9 => {
+//                     // TEQ
+//                     if (rd == 0xF)
+//                         return undefinedTestBehaviour(cpu);
+
+//                     const result = op1 ^ op2;
+//                     setTestOpFlags(S, cpu, opcode, result);
+//                 },
+//                 0xA => {
+//                     // CMP
+//                     if (rd == 0xF)
+//                         return undefinedTestBehaviour(cpu);
+
+//                     cmp(cpu, op1, op2);
+//                 },
+//                 0xB => {
+//                     // CMN
+//                     if (rd == 0xF)
+//                         return undefinedTestBehaviour(cpu);
+
+//                     cmn(cpu, op1, op2);
+//                 },
+//                 0xC => {
+//                     // ORR
+//                     const result = op1 | op2;
+//                     cpu.r[rd] = result;
+//                     setArmLogicOpFlags(S, cpu, rd, result);
+//                 },
+//                 0xD => {
+//                     // MOV
+//                     cpu.r[rd] = op2;
+//                     setArmLogicOpFlags(S, cpu, rd, op2);
+//                 },
+//                 0xE => {
+//                     // BIC
+//                     const result = op1 & ~op2;
+//                     cpu.r[rd] = result;
+//                     setArmLogicOpFlags(S, cpu, rd, result);
+//                 },
+//                 0xF => {
+//                     // MVN
+//                     const result = ~op2;
+//                     cpu.r[rd] = result;
+//                     setArmLogicOpFlags(S, cpu, rd, result);
+//                 },
+//             }
+
+//             if (rd == 0xF) cpu.pipe.reload(u32, cpu);
+//         }
+//     }.inner;
+// }
+
 fn armSbc(comptime S: bool, cpu: *Arm7tdmi, rd: u4, left: u32, right: u32, old_carry: u1) u32 {
     var result: u32 = undefined;
     if (S and rd == 0xF) {
@@ -143,6 +295,14 @@ fn armSbc(comptime S: bool, cpu: *Arm7tdmi, rd: u4, left: u32, right: u32, old_c
     return result;
 }
 
+fn newSbc(left: u32, right: u32, old_carry: u1) u32 {
+    // TODO: Make your own version (thanks peach.bot)
+    const subtrahend = @as(u64, right) -% old_carry +% 1;
+    const ret = @truncate(u32, left -% subtrahend);
+
+    return ret;
+}
+
 pub fn sbc(comptime S: bool, cpu: *Arm7tdmi, left: u32, right: u32, old_carry: u1) u32 {
     // TODO: Make your own version (thanks peach.bot)
     const subtrahend = @as(u64, right) -% old_carry +% 1;
@@ -195,6 +355,12 @@ fn armAdd(comptime S: bool, cpu: *Arm7tdmi, rd: u4, left: u32, right: u32) u32 {
     return result;
 }
 
+fn newAdd(didOverflow: *bool, left: u32, right: u32) u32 {
+    var ret: u32 = undefined;
+    didOverflow.* = @addWithOverflow(u32, left, right, &ret);
+    return ret;
+}
+
 pub fn add(comptime S: bool, cpu: *Arm7tdmi, left: u32, right: u32) u32 {
     var result: u32 = undefined;
     const didOverflow = @addWithOverflow(u32, left, right, &result);
@@ -221,6 +387,15 @@ fn armAdc(comptime S: bool, cpu: *Arm7tdmi, rd: u4, left: u32, right: u32, old_c
     return result;
 }
 
+fn newAdc(didOverflow: *bool, left: u32, right: u32, old_carry: u1) u32 {
+    var ret: u32 = undefined;
+    const did = @addWithOverflow(u32, left, right, &ret);
+    const overflow = @addWithOverflow(u32, ret, old_carry, &ret);
+
+    didOverflow.* = did or overflow;
+    return ret;
+}
+
 pub fn adc(comptime S: bool, cpu: *Arm7tdmi, left: u32, right: u32, old_carry: u1) u32 {
     var result: u32 = undefined;
     const did = @addWithOverflow(u32, left, right, &result);
@@ -280,5 +455,5 @@ fn setTestOpFlags(comptime S: bool, cpu: *Arm7tdmi, opcode: u32, result: u32) vo
 
 fn undefinedTestBehaviour(cpu: *Arm7tdmi) void {
     @setCold(true);
-    cpu.setCpsr(cpu.spsr.raw);
+    cpu.setCpsrNoFlush(cpu.spsr.raw);
 }

src/core/cpu/arm/half_signed_data_transfer.zig

@@ -15,20 +15,8 @@ pub fn halfAndSignedDataTransfer(comptime P: bool, comptime U: bool, comptime I:
             const rm = opcode & 0xF;
             const imm_offset_high = opcode >> 8 & 0xF;
 
-            var base: u32 = undefined;
+            const base = cpu.r[rn] + if (!L and rn == 0xF) 4 else @as(u32, 0);
-            if (rn == 0xF) {
+            const offset = if (I) imm_offset_high << 4 | rm else cpu.r[rm];
-                base = cpu.fakePC();
-                if (!L) base += 4;
-            } else {
-                base = cpu.r[rn];
-            }
-
-            var offset: u32 = undefined;
-            if (I) {
-                offset = imm_offset_high << 4 | rm;
-            } else {
-                offset = cpu.r[rm];
-            }
 
             const modified_base = if (U) base +% offset else base -% offset;
             var address = if (P) modified_base else base;

src/core/cpu/arm/single_data_transfer.zig

@@ -14,13 +14,8 @@ pub fn singleDataTransfer(comptime I: bool, comptime P: bool, comptime U: bool,
             const rn = opcode >> 16 & 0xF;
             const rd = opcode >> 12 & 0xF;
 
-            var base: u32 = undefined;
+            // rn is r15 and L is not set, the PC is 12 ahead
-            if (rn == 0xF) {
+            const base = cpu.r[rn] + if (!L and rn == 0xF) 4 else @as(u32, 0);
-                base = cpu.fakePC();
-                if (!L) base += 4; // Offset of 12
-            } else {
-                base = cpu.r[rn];
-            }
 
             const offset = if (I) shifter.immShift(false, cpu, opcode) else opcode & 0xFFF;
 
@@ -40,18 +35,26 @@ pub fn singleDataTransfer(comptime I: bool, comptime P: bool, comptime U: bool,
             } else {
                 if (B) {
                     // STRB
-                    const value = if (rd == 0xF) cpu.r[rd] + 8 else cpu.r[rd];
+                    const value = cpu.r[rd] + if (rd == 0xF) 4 else @as(u32, 0); // PC is 12 ahead
                     bus.write(u8, address, @truncate(u8, value));
                 } else {
                     // STR
-                    const value = if (rd == 0xF) cpu.r[rd] + 8 else cpu.r[rd];
+                    const value = cpu.r[rd] + if (rd == 0xF) 4 else @as(u32, 0);
                     bus.write(u32, address, value);
                 }
             }
 
             address = modified_base;
-            if (W and P or !P) cpu.r[rn] = address;
+            if (W and P or !P) {
-            if (L) cpu.r[rd] = result; // This emulates the LDR rd == rn behaviour
+                cpu.r[rn] = address;
+                if (rn == 0xF) cpu.pipe.reload(u32, cpu);
+            }
+
+            if (L) {
+                // This emulates the LDR rd == rn behaviour
+                cpu.r[rd] = result;
+                if (rd == 0xF) cpu.pipe.reload(u32, cpu);
+            }
         }
     }.inner;
 }

src/core/cpu/arm/software_interrupt.zig

@@ -6,7 +6,7 @@ pub fn armSoftwareInterrupt() InstrFn {
     return struct {
         fn inner(cpu: *Arm7tdmi, _: *Bus, _: u32) void {
             // Copy Values from Current Mode
-            const r15 = cpu.r[15];
+            const ret_addr = cpu.r[15] - 4;
             const cpsr = cpu.cpsr.raw;
 
             // Switch Mode
@@ -14,9 +14,10 @@ pub fn armSoftwareInterrupt() InstrFn {
             cpu.cpsr.t.write(false); // Force ARM Mode
             cpu.cpsr.i.write(true); // Disable normal interrupts
 
-            cpu.r[14] = r15; // Resume Execution
+            cpu.r[14] = ret_addr; // Resume Execution
             cpu.spsr.raw = cpsr; // Previous mode CPSR
             cpu.r[15] = 0x0000_0008;
+            cpu.pipe.reload(u32, cpu);
         }
     }.inner;
 }

src/core/cpu/barrel_shifter.zig

@@ -18,11 +18,9 @@ pub fn execute(comptime S: bool, cpu: *Arm7tdmi, opcode: u32) u32 {
 
 fn registerShift(comptime S: bool, cpu: *Arm7tdmi, opcode: u32) u32 {
     const rs_idx = opcode >> 8 & 0xF;
+    const rm = cpu.r[opcode & 0xF];
     const rs = @truncate(u8, cpu.r[rs_idx]);
 
-    const rm_idx = opcode & 0xF;
-    const rm = if (rm_idx == 0xF) cpu.fakePC() else cpu.r[rm_idx];
-
     return switch (@truncate(u2, opcode >> 5)) {
         0b00 => logicalLeft(S, &cpu.cpsr, rm, rs),
         0b01 => logicalRight(S, &cpu.cpsr, rm, rs),
@@ -33,9 +31,7 @@ fn registerShift(comptime S: bool, cpu: *Arm7tdmi, opcode: u32) u32 {
 
 pub fn immShift(comptime S: bool, cpu: *Arm7tdmi, opcode: u32) u32 {
     const amount = @truncate(u8, opcode >> 7 & 0x1F);
-
+    const rm = cpu.r[opcode & 0xF];
-    const rm_idx = opcode & 0xF;
-    const rm = if (rm_idx == 0xF) cpu.fakePC() else cpu.r[rm_idx];
 
     var result: u32 = undefined;
     if (amount == 0) {

src/core/cpu/thumb/block_data_transfer.zig

@@ -33,7 +33,8 @@ pub fn fmt14(comptime L: bool, comptime R: bool) InstrFn {
             if (R) {
                 if (L) {
                     const value = bus.read(u32, address);
-                    cpu.r[15] = value & 0xFFFF_FFFE;
+                    cpu.r[15] = value & ~@as(u32, 1);
+                    cpu.pipe.reload(u16, cpu);
                 } else {
                     bus.write(u32, address, cpu.r[14]);
                 }
@@ -52,7 +53,13 @@ pub fn fmt15(comptime L: bool, comptime rb: u3) InstrFn {
             const end_address = cpu.r[rb] + 4 * countRlist(opcode);
 
             if (opcode & 0xFF == 0) {
-                if (L) cpu.r[15] = bus.read(u32, address) else bus.write(u32, address, cpu.r[15] + 4);
+                if (L) {
+                    cpu.r[15] = bus.read(u32, address);
+                    cpu.pipe.reload(u16, cpu);
+                } else {
+                    bus.write(u32, address, cpu.r[15] + 2);
+                }
+
                 cpu.r[rb] += 0x40;
                 return;
             }

src/core/cpu/thumb/branch.zig

@@ -9,16 +9,13 @@ pub fn fmt16(comptime cond: u4) InstrFn {
     return struct {
         fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void {
             // B
-            const offset = sext(u32, u8, opcode & 0xFF) << 1;
+            if (cond == 0xE or cond == 0xF)
+                cpu.panic("[CPU/THUMB.16] Undefined conditional branch with condition {}", .{cond});
 
-            const should_execute = switch (cond) {
+            if (!checkCond(cpu.cpsr, cond)) return;
-                0xE, 0xF => cpu.panic("[CPU/THUMB.16] Undefined conditional branch with condition {}", .{cond}),
-                else => checkCond(cpu.cpsr, cond),
-            };
 
-            if (should_execute) {
+            cpu.r[15] +%= sext(u32, u8, opcode & 0xFF) << 1;
-                cpu.r[15] = (cpu.r[15] + 2) +% offset;
+            cpu.pipe.reload(u16, cpu);
-            }
         }
     }.inner;
 }
@@ -27,8 +24,8 @@ pub fn fmt18() InstrFn {
     return struct {
         // B but conditional
         fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void {
-            const offset = sext(u32, u11, opcode & 0x7FF) << 1;
+            cpu.r[15] +%= sext(u32, u11, opcode & 0x7FF) << 1;
-            cpu.r[15] = (cpu.r[15] + 2) +% offset;
+            cpu.pipe.reload(u16, cpu);
         }
     }.inner;
 }
@@ -41,13 +38,16 @@ pub fn fmt19(comptime is_low: bool) InstrFn {
 
             if (is_low) {
                 // Instruction 2
-                const old_pc = cpu.r[15];
+                const next_opcode = cpu.r[15] - 2;
 
                 cpu.r[15] = cpu.r[14] +% (offset << 1);
-                cpu.r[14] = old_pc | 1;
+                cpu.r[14] = next_opcode | 1;
+
+                cpu.pipe.reload(u16, cpu);
             } else {
                 // Instruction 1
-                cpu.r[14] = (cpu.r[15] + 2) +% (sext(u32, u11, offset) << 12);
+                const lr_offset = sext(u32, u11, offset) << 12;
+                cpu.r[14] = (cpu.r[15] +% lr_offset) & ~@as(u32, 1);
             }
         }
     }.inner;

src/core/cpu/thumb/data_processing.zig

@@ -77,10 +77,18 @@ pub fn fmt5(comptime op: u2, comptime h1: u1, comptime h2: u1) InstrFn {
                 },
                 0b11 => {
                     // BX
-                    cpu.cpsr.t.write(src & 1 == 1);
+                    const thumb = src & 1 == 1;
-                    cpu.r[15] = src & 0xFFFF_FFFE;
+                    cpu.r[15] = src & ~@as(u32, 1);
+                    cpu.cpsr.t.write(thumb);
+
+                    if (thumb) cpu.pipe.reload(u16, cpu) else cpu.pipe.reload(u32, cpu);
+
+                    // Pipeline alrady flushed
+                    return; // FIXME: Is this necessary? (Refactor out?)
                 },
             }
+
+            if (dst_idx == 0xF) cpu.pipe.reload(u16, cpu);
         }
     }.inner;
 }
@@ -133,10 +141,9 @@ pub fn fmt12(comptime isSP: bool, comptime rd: u3) InstrFn {
     return struct {
         fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void {
             // ADD
-            const left = if (isSP) cpu.r[13] else (cpu.r[15] + 2) & 0xFFFF_FFFD;
+            const left = if (isSP) cpu.r[13] else cpu.r[15] & ~@as(u32, 2);
             const right = (opcode & 0xFF) << 2;
-            const result = left + right;
+            cpu.r[rd] = left + right;
-            cpu.r[rd] = result;
         }
     }.inner;
 }

src/core/cpu/thumb/data_transfer.zig

@@ -11,7 +11,9 @@ pub fn fmt6(comptime rd: u3) InstrFn {
         fn inner(cpu: *Arm7tdmi, bus: *Bus, opcode: u16) void {
             // LDR
             const offset = (opcode & 0xFF) << 2;
-            cpu.r[rd] = bus.read(u32, (cpu.r[15] + 2 & 0xFFFF_FFFD) + offset);
+
+            // Bit 1 of the PC intentionally ignored
+            cpu.r[rd] = bus.read(u32, (cpu.r[15] & ~@as(u32, 2)) + offset);
         }
     }.inner;
 }

src/core/cpu/thumb/software_interrupt.zig

@@ -6,7 +6,7 @@ pub fn fmt17() InstrFn {
     return struct {
         fn inner(cpu: *Arm7tdmi, _: *Bus, _: u16) void {
             // Copy Values from Current Mode
-            const r15 = cpu.r[15];
+            const ret_addr = cpu.r[15] - 2;
             const cpsr = cpu.cpsr.raw;
 
             // Switch Mode
@@ -14,9 +14,10 @@ pub fn fmt17() InstrFn {
             cpu.cpsr.t.write(false); // Force ARM Mode
             cpu.cpsr.i.write(true); // Disable normal interrupts
 
-            cpu.r[14] = r15; // Resume Execution
+            cpu.r[14] = ret_addr; // Resume Execution
             cpu.spsr.raw = cpsr; // Previous mode CPSR
             cpu.r[15] = 0x0000_0008;
+            cpu.pipe.reload(u32, cpu);
         }
     }.inner;
 }

src/core/util.zig

@@ -69,7 +69,7 @@ pub fn intToBytes(comptime T: type, value: anytype) [@sizeOf(T)]u8 {
 ///
 /// This function returns a slice of everything just before the first
 /// `\0`
-pub fn asString(title: [12]u8) []const u8 {
+pub fn asStringSlice(title: *const [12]u8) []const u8 {
     var len = title.len;
     for (title) |char, i| {
         if (char == 0) {
@@ -127,6 +127,7 @@ pub const Logger = struct {
 
     pub fn print(self: *Self, comptime format: []const u8, args: anytype) !void {
         try self.buf.writer().print(format, args);
+        try self.buf.flush(); // FIXME: On panics, whatever is in the buffer isn't written to file
     }
 
     pub fn mgbaLog(self: *Self, arm7tdmi: *const Arm7tdmi, opcode: u32) void {
@@ -166,7 +167,7 @@ pub const Logger = struct {
             arm7tdmi.r[12],
             arm7tdmi.r[13],
             arm7tdmi.r[14],
-            arm7tdmi.r[15],
+            arm7tdmi.r[15] - if (arm7tdmi.cpsr.t.read()) 2 else @as(u32, 4),
             arm7tdmi.cpsr.raw,
             opcode,
         };