feat(cpu): implement SUB in THUMB format 3

src/cpu/arm/data_processing.zig

@@ -29,6 +29,18 @@ pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime instrKind: u4
             }
 
             switch (instrKind) {
+                0x2 => {
+                    // SUB
+                    const result = op1 -% op2;
+                    cpu.r[rd] = result;
+
+                    if (S and rd != 0xF) {
+                        cpu.cpsr.n.write(result >> 31 & 1 == 1);
+                        cpu.cpsr.z.write(result == 0);
+                        cpu.cpsr.c.write(op2 <= op1);
+                        cpu.cpsr.v.write(((op1 ^ result) & (~op2 ^ result)) >> 31 & 1 == 1);
+                    }
+                },
                 0x4 => {
                     // ADD
                     var result: u32 = undefined;
@@ -67,7 +79,7 @@ pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime instrKind: u4
                     if (S and rd != 0xF) {
                         cpu.cpsr.n.write(op2 >> 31 & 1 == 1);
                         cpu.cpsr.z.write(op2 == 0);
-                        // C set by Barr0x15el Shifter, V is unnafected
+                        // C set by Barrel Shifter, V is unaffected
                     }
                 },
                 0xA => {
@@ -87,7 +99,18 @@ pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime instrKind: u4
                     if (S and rd != 0xF) {
                         cpu.cpsr.n.write(result >> 31 & 1 == 1);
                         cpu.cpsr.z.write(result == 0);
-                        // C set by Barr0x15el Shifter, V is unnafected
+                        // C set by Barrel Shifter, V is unaffected
+                    }
+                },
+                0xF => {
+                    // MVN
+                    const result = ~op2;
+                    cpu.r[rd] = result;
+
+                    if (S and rd != 0xF) {
+                        cpu.cpsr.n.write(result >> 31 & 1 == 1);
+                        cpu.cpsr.z.write(result == 0);
+                        // C set by Barrel Shifter, V is unaffected
                     }
                 },
                 else => std.debug.panic("[CPU] TODO: implement data processing type {}", .{instrKind}),

src/cpu/thumb/format3.zig

@@ -28,6 +28,7 @@ pub fn format3(comptime op: u2, comptime rd: u3) InstrFn {
                     cpu.cpsr.v.write(((left ^ result) & (~offset ^ result)) >> 31 & 1 == 1);
                 },
                 0b10 => {
+                    // ADD
                     const left = cpu.r[rd];
 
                     var result: u32 = undefined;
@@ -40,7 +41,15 @@ pub fn format3(comptime op: u2, comptime rd: u3) InstrFn {
                     cpu.cpsr.v.write(((left ^ result) & (offset ^ result)) >> 31 & 1 == 1);
                 },
                 0b11 => {
-                    std.debug.panic("TODO: Implement sub R{}, #0x{X:0>2}", .{ rd, offset });
+                    // SUB
+                    const left = cpu.r[rd];
+                    const result = left -% offset;
+                    cpu.r[rd] = result;
+
+                    cpu.cpsr.n.write(result >> 31 & 1 == 1);
+                    cpu.cpsr.z.write(result == 0);
+                    cpu.cpsr.c.write(offset <= left);
+                    cpu.cpsr.v.write(((left ^ result) & (~offset ^ result)) >> 31 & 1 == 1);
                 },
             }
         }