Rekai Nyangadzayi Musuka
|
b4e0682801
|
fix(cpu): allow for select values to overflow
FuzzARM found these operations which panicked, when they should
have overflowed. These are now fixed
n = 8000
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2022-10-21 05:12:12 -03:00 |
Rekai Nyangadzayi Musuka
|
af10c1b076
|
feat(cpu): implement format 13
While bugs do exist, at this point all THUMB and ARMv4 instructions
have been implemented! Yay!
|
2022-10-21 05:12:12 -03:00 |
Rekai Nyangadzayi Musuka
|
e6a0eab667
|
feat(cpu): implement THUMB format 17
|
2022-10-21 05:12:12 -03:00 |
Rekai Nyangadzayi Musuka
|
523b9d2736
|
feat(cpu): implement THUMB format11
|
2022-10-21 05:12:12 -03:00 |
Rekai Nyangadzayi Musuka
|
c37546d273
|
chore: progress towards passing ldr/str thumb in armwrestler
|
2022-10-21 05:12:11 -03:00 |
Rekai Nyangadzayi Musuka
|
fbedebb938
|
fix(cpu): properly negate in NEG
|
2022-10-21 05:12:11 -03:00 |
Rekai Nyangadzayi Musuka
|
1773a3acc8
|
fix(cpu): reimplement THUMB offset shifts
|
2022-10-21 05:12:11 -03:00 |
Rekai Nyangadzayi Musuka
|
058c02150c
|
fix(cpu): op == 0b00 decodes to add in format 5
|
2022-10-21 05:12:11 -03:00 |
Rekai Nyangadzayi Musuka
|
8d841ead50
|
fix(cpu): account for overflow in THUMB alu MUL
|
2022-10-21 05:12:10 -03:00 |
Rekai Nyangadzayi Musuka
|
7dbd2fc556
|
fix(cpu): account for rn in rlist in block data transfer
|
2022-10-21 05:12:10 -03:00 |
Rekai Nyangadzayi Musuka
|
85e0924669
|
feat: implement LDM/STM behaviour when S is set
|
2022-10-21 05:12:10 -03:00 |
Rekai Nyangadzayi Musuka
|
97919f646d
|
feat(cpu): Pass all LDR/STR ARMwrestler tests
|
2022-10-21 05:12:10 -03:00 |
Rekai Nyangadzayi Musuka
|
151de2eab4
|
feat(cpu): implement ARM SWP and SWPB
|
2022-10-21 05:12:10 -03:00 |
Rekai Nyangadzayi Musuka
|
da681c946e
|
feat(cpu): Implement Multiply Long ARM instructions
|
2022-10-21 05:12:09 -03:00 |
Rekai Nyangadzayi Musuka
|
7013389288
|
feat(cpu): implement format 18 THUMB instructions
|
2022-10-21 05:12:09 -03:00 |
Rekai Nyangadzayi Musuka
|
443520ecae
|
chore: more detailed panic message
|
2022-10-21 05:12:09 -03:00 |
Rekai Nyangadzayi Musuka
|
96d7285111
|
feat(cpu): implement format 10 THUMB instructions
|
2022-10-21 05:12:08 -03:00 |
Rekai Nyangadzayi Musuka
|
7e6fc44191
|
feat(cpu): implement SWP
|
2022-10-21 05:12:08 -03:00 |
Rekai Nyangadzayi Musuka
|
9cb4ebaa7f
|
fix(cpu): perform MUL with u64s, throw away upper 32 bits
|
2022-10-21 05:12:08 -03:00 |
Rekai Nyangadzayi Musuka
|
e1fec48a0e
|
fix(cpu): properly decode multiply instructions
|
2022-10-21 05:12:07 -03:00 |
Rekai Nyangadzayi Musuka
|
0778ee8dd7
|
feat(cpu): implement ARM multiply instructions
|
2022-10-21 05:12:07 -03:00 |
Rekai Nyangadzayi Musuka
|
980e4ff5dd
|
fix(cpu): properly decode THUMB PUSH and POP at comptime
|
2022-10-21 05:12:06 -03:00 |
Rekai Nyangadzayi Musuka
|
1ac193c506
|
fix(cpu): don't ignore 11th bit of THUMB BL offset
|
2022-10-21 05:12:06 -03:00 |
Rekai Nyangadzayi Musuka
|
d6ed071bc6
|
feat(cpu): implement thumb push / pop and stub format 13 thumb instrs
|
2022-10-21 05:12:06 -03:00 |
Rekai Nyangadzayi Musuka
|
a3d53d40fb
|
feat(cpu): implement THUMB format 9 loads / stores
|
2022-10-21 05:12:06 -03:00 |
Rekai Nyangadzayi Musuka
|
a17dfbe41f
|
fix(cpu): resolve issues with unexpected PC value in THUMB
|
2022-10-21 05:12:06 -03:00 |
Rekai Nyangadzayi Musuka
|
b9a81baa47
|
feat(cpu): implement THUMB ldmia stmia
|
2022-10-21 05:12:06 -03:00 |
Rekai Nyangadzayi Musuka
|
97b236225e
|
chore: implement THUMB format 4 instructions
|
2022-10-21 05:12:05 -03:00 |
Rekai Nyangadzayi Musuka
|
8113146b86
|
chore: dedup code in THUMB instructions
|
2022-10-21 05:12:05 -03:00 |
Rekai Nyangadzayi Musuka
|
e6625113db
|
chore: refactor and genericize ARM data processing calculations
|
2022-10-21 05:12:05 -03:00 |
Rekai Nyangadzayi Musuka
|
2643504eb5
|
chore: relocate barrel_shifter zig file
|
2022-10-21 05:12:05 -03:00 |
Rekai Nyangadzayi Musuka
|
f7518d1bab
|
feat(cpu): implement format2 THUMB instructions
|
2022-10-21 05:12:05 -03:00 |
Rekai Nyangadzayi Musuka
|
800ca798cd
|
feat(cpu): implement format19 THUMB instructions
|
2022-10-21 05:12:05 -03:00 |
Rekai Nyangadzayi Musuka
|
7bc186a03c
|
feat(cpu): implement format16 THUMB instructions
|
2022-10-21 05:12:04 -03:00 |
Rekai Nyangadzayi Musuka
|
b94b87d186
|
feat(cpu): implement format 1 THUMB instructions
|
2022-10-21 05:12:04 -03:00 |
Rekai Nyangadzayi Musuka
|
93922b65e3
|
feat(cpu): implement format 6 THUMB instructions
|
2022-10-21 05:12:04 -03:00 |
Rekai Nyangadzayi Musuka
|
c4e131b92d
|
chore: binary logging + file logging + DP chanes + fastBoot changes
|
2022-10-21 05:12:02 -03:00 |
Rekai Nyangadzayi Musuka
|
4bdb85834c
|
feat(cpu): implement SWI
|
2022-10-21 05:12:02 -03:00 |
Rekai Nyangadzayi Musuka
|
8bb7ea6be6
|
fix(cpu): interim solution to weird program counter behaviour on illegal tst instruction
|
2022-10-21 05:12:01 -03:00 |
Rekai Nyangadzayi Musuka
|
60a1f7fa99
|
chore(cpu): implement behaviour for undefined test instruction
|
2022-10-21 05:12:01 -03:00 |
Rekai Nyangadzayi Musuka
|
b3b8182f85
|
fix(cpu): fix PC offset when barrel shifter and bit 4 of DP is set
|
2022-10-21 05:12:01 -03:00 |
Rekai Nyangadzayi Musuka
|
56e660714c
|
fix(cpu): implement S set + rd == 15 case for data processing
|
2022-10-21 05:12:01 -03:00 |
Rekai Nyangadzayi Musuka
|
eb632056a2
|
feat(cpu): implement banked registers
|
2022-10-21 05:12:01 -03:00 |
Rekai Nyangadzayi Musuka
|
fbc9de0335
|
fix(cpu): improve MRS and MSR instructions
|
2022-10-21 05:12:01 -03:00 |
Rekai Nyangadzayi Musuka
|
5c7539cd26
|
feat(cpu): implement CMN
|
2022-10-21 05:12:00 -03:00 |
Rekai Nyangadzayi Musuka
|
7c20e5fdb5
|
fix(barrel_shifter): fix PC being 1 word ahead in barrel shifter
|
2022-10-21 05:12:00 -03:00 |
Rekai Nyangadzayi Musuka
|
f79e7126ee
|
feat(cpu): Implement RSC
|
2022-10-21 05:12:00 -03:00 |
Rekai Nyangadzayi Musuka
|
15e92bc6af
|
feat(cpu): implement RSB
|
2022-10-21 05:12:00 -03:00 |
Rekai Nyangadzayi Musuka
|
47fc96fe00
|
feat(cpu): implement BIC
|
2022-10-21 05:12:00 -03:00 |
Rekai Nyangadzayi Musuka
|
4ac5ad42c6
|
feat(cpu): implement EOR
|
2022-10-21 05:12:00 -03:00 |