 Rekai Nyangadzayi Musuka
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ff70aadfdb
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fix(cpu): make Data Processing instructions r15-aware
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2022-10-21 05:11:55 -03:00 |
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Rekai Nyangadzayi Musuka
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9a5959e46c
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fix(cpu): write results of ORR to destination register
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2022-10-21 05:11:54 -03:00 |
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Rekai Nyangadzayi Musuka
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780c717409
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feat(cpu): implement TEQ
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2022-10-21 05:11:53 -03:00 |
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Rekai Nyangadzayi Musuka
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34c6df344d
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feat(cpu): Implement ORR
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2022-10-21 05:11:53 -03:00 |
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Rekai Nyangadzayi Musuka
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036b861b05
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chore: code cleanup
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2022-10-21 05:11:50 -03:00 |
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Rekai Nyangadzayi Musuka
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880546468c
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chore(bus): refactor bus.zig
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2022-10-21 05:11:50 -03:00 |
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Rekai Nyangadzayi Musuka
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1a9c9ba4cb
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chore: refactor instruction exec code
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2022-10-21 05:11:50 -03:00 |
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Rekai Nyangadzayi Musuka
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d495f5b4c5
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feat: implement S (when rd != 15) for several data processing instructions
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2022-10-21 05:11:49 -03:00 |
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Rekai Nyangadzayi Musuka
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788bef188d
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feat: implement dedicated Barrel Shifter SHL and SHR
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2022-10-21 05:11:49 -03:00 |
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Rekai Nyangadzayi Musuka
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bff9be03cc
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chore: stub TST
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2022-10-21 05:11:48 -03:00 |
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Rekai Nyangadzayi Musuka
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46c694d95a
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fix(cpu): properly implement SUB/CMP CSPSR carry bit condition
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2022-10-21 05:11:48 -03:00 |
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Rekai Nyangadzayi Musuka
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cbcc6282df
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feat(bus): add Io Struct
Also, add more information to all panic messages
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2022-10-21 05:11:46 -03:00 |
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Rekai Nyangadzayi Musuka
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7016fcdb79
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chore: use bitfield library
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2022-10-21 05:11:45 -03:00 |
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Rekai Nyangadzayi Musuka
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c98e8d384a
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chore: conform to zig style guides
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2022-10-21 05:11:44 -03:00 |
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Rekai Nyangadzayi Musuka
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e841bf44ca
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chore(cpu): iron out some false assumptions
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2022-10-21 05:11:44 -03:00 |
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Rekai Nyangadzayi Musuka
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5b3b81e4dc
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Initial Commit
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2021-12-29 15:09:00 -06:00 |