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132 Commits

Author SHA1 Message Date
Rekai Nyangadzayi Musuka 1a23073424 fix: incorrect order-of-operations in ARM BL impl 2022-10-21 05:12:39 -03:00
Rekai Nyangadzayi Musuka e690f88cda chore: misc improvements 2022-10-21 05:12:37 -03:00
Rekai Nyangadzayi Musuka 40f3600de2 fix: remove accidental rotation in ldrsh instructions 2022-10-21 05:12:35 -03:00
Rekai Nyangadzayi Musuka 601e717850 chore: reimplement bus read/writes 2022-10-21 05:12:33 -03:00
Rekai Nyangadzayi Musuka 886b9abf3d fix: force align reads/writes in memory bus rather than in CPU 2022-10-21 05:12:32 -03:00
Rekai Nyangadzayi Musuka c3ae727ed1 fix: improve perf of instructions w/ rotr 2022-10-21 05:12:28 -03:00
Rekai Nyangadzayi Musuka 68b0601a42 chore: replace unnecessarily complex sign extension implementation 2022-10-21 05:12:24 -03:00
Rekai Nyangadzayi Musuka acf1a10f91 chore: don't panic on 32-bit I/O 2022-10-21 05:12:21 -03:00
Rekai Nyangadzayi Musuka 37fd8dab84 chore: squash bugs preventing swi_demo.gba from working 2022-10-21 05:12:19 -03:00
Rekai Nyangadzayi Musuka 05bf245b5a fix: don't mask away MSB in THUMB.5 add 2022-10-21 05:12:19 -03:00
Rekai Nyangadzayi Musuka f9e7128061 fix: properly decode format 11 instructions 2022-10-21 05:12:18 -03:00
Rekai Nyangadzayi Musuka 603e4b6fdf chore: make use of scoped logging 2022-10-21 05:12:18 -03:00
Rekai Nyangadzayi Musuka 599a1f2973 chore: remove TODOs and some useless imports 2022-10-21 05:12:18 -03:00
Rekai Nyangadzayi Musuka 67a785cc22 fix(cpu): force align thumb and arm block data transfers 2022-10-21 05:12:18 -03:00
Rekai Nyangadzayi Musuka 4eb3842606 feat: pass arm.gba 2022-10-21 05:12:17 -03:00
Rekai Nyangadzayi Musuka 1ee8b51b2b chore: reimplement ARM LDM/STM 2022-10-21 05:12:17 -03:00
Rekai Nyangadzayi Musuka 130310e5cc chore: improve arm ldm/stm 2022-10-21 05:12:17 -03:00
Rekai Nyangadzayi Musuka e933d7e5c7 fix(cpu): force-align SWP reads and writes 2022-10-21 05:12:17 -03:00
Rekai Nyangadzayi Musuka 44e8b5b882 fix: force-align ARM STRH reads 2022-10-21 05:12:17 -03:00
Rekai Nyangadzayi Musuka 28361e8b7d fix: implement the same LDRSH logic as THUMB LDRSH 2022-10-21 05:12:16 -03:00
Rekai Nyangadzayi Musuka 75921d6413 fix: PC is 12 ahead when it is rd in str and strb 2022-10-21 05:12:16 -03:00
Rekai Nyangadzayi Musuka 17226d8f75 fix: listen to my past self 
By deleting this line I go from test 234 to test 355 in arm.gba
 2022-10-21 05:12:16 -03:00
Rekai Nyangadzayi Musuka 8006ca31e6 chore: remove unnecessary @as calls 2022-10-21 05:12:16 -03:00
Rekai Nyangadzayi Musuka 82b92b4733 feat: pass thumb.gba 2022-10-21 05:12:15 -03:00
Rekai Nyangadzayi Musuka bf42d3ae2f chore: account for empty rlist in THUMB LDM/STM 2022-10-21 05:12:15 -03:00
Rekai Nyangadzayi Musuka f63ae76931 fix(cpu): handle edge case in LDRSH 2022-10-21 05:12:15 -03:00
Rekai Nyangadzayi Musuka d8bd6da563 fix: resolve decoding mixup in THUMB format 8 instructions 2022-10-21 05:12:14 -03:00
Rekai Nyangadzayi Musuka 271f42cf0e feat: rename ARM and THUMB SWI functions 2022-10-21 05:12:13 -03:00
Rekai Nyangadzayi Musuka 01e15584da chore: group THUMB and select ARM instructions together (same file) 2022-10-21 05:12:13 -03:00
Rekai Nyangadzayi Musuka c8f2db69df fix(cpu): resolve edge cases in THUMB Format 5 2022-10-21 05:12:12 -03:00
Rekai Nyangadzayi Musuka b4e0682801 fix(cpu): allow for select values to overflow 
FuzzARM found these operations which panicked, when they should
have overflowed. These are now fixed

n = 8000
 2022-10-21 05:12:12 -03:00
Rekai Nyangadzayi Musuka af10c1b076 feat(cpu): implement format 13 
While bugs do exist, at this point all THUMB and ARMv4 instructions
have been implemented! Yay!
 2022-10-21 05:12:12 -03:00
Rekai Nyangadzayi Musuka e6a0eab667 feat(cpu): implement THUMB format 17 2022-10-21 05:12:12 -03:00
Rekai Nyangadzayi Musuka 523b9d2736 feat(cpu): implement THUMB format11 2022-10-21 05:12:12 -03:00
Rekai Nyangadzayi Musuka c37546d273 chore: progress towards passing ldr/str thumb in armwrestler 2022-10-21 05:12:11 -03:00
Rekai Nyangadzayi Musuka fbedebb938 fix(cpu): properly negate in NEG 2022-10-21 05:12:11 -03:00
Rekai Nyangadzayi Musuka 1773a3acc8 fix(cpu): reimplement THUMB offset shifts 2022-10-21 05:12:11 -03:00
Rekai Nyangadzayi Musuka 058c02150c fix(cpu): op == 0b00 decodes to add in format 5 2022-10-21 05:12:11 -03:00
Rekai Nyangadzayi Musuka 8d841ead50 fix(cpu): account for overflow in THUMB alu MUL 2022-10-21 05:12:10 -03:00
Rekai Nyangadzayi Musuka 7dbd2fc556 fix(cpu): account for rn in rlist in block data transfer 2022-10-21 05:12:10 -03:00
Rekai Nyangadzayi Musuka 85e0924669 feat: implement LDM/STM behaviour when S is set 2022-10-21 05:12:10 -03:00
Rekai Nyangadzayi Musuka 97919f646d feat(cpu): Pass all LDR/STR ARMwrestler tests 2022-10-21 05:12:10 -03:00
Rekai Nyangadzayi Musuka 151de2eab4 feat(cpu): implement ARM SWP and SWPB 2022-10-21 05:12:10 -03:00
Rekai Nyangadzayi Musuka da681c946e feat(cpu): Implement Multiply Long ARM instructions 2022-10-21 05:12:09 -03:00
Rekai Nyangadzayi Musuka 7013389288 feat(cpu): implement format 18 THUMB instructions 2022-10-21 05:12:09 -03:00
Rekai Nyangadzayi Musuka 443520ecae chore: more detailed panic message 2022-10-21 05:12:09 -03:00
Rekai Nyangadzayi Musuka 96d7285111 feat(cpu): implement format 10 THUMB instructions 2022-10-21 05:12:08 -03:00
Rekai Nyangadzayi Musuka 7e6fc44191 feat(cpu): implement SWP 2022-10-21 05:12:08 -03:00
Rekai Nyangadzayi Musuka 9cb4ebaa7f fix(cpu): perform MUL with u64s, throw away upper 32 bits 2022-10-21 05:12:08 -03:00
Rekai Nyangadzayi Musuka e1fec48a0e fix(cpu): properly decode multiply instructions 2022-10-21 05:12:07 -03:00