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68b0601a42
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chore: replace unnecessarily complex sign extension implementation
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2022-10-21 05:12:24 -03:00 |
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603e4b6fdf
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chore: make use of scoped logging
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2022-10-21 05:12:18 -03:00 |
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599a1f2973
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chore: remove TODOs and some useless imports
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2022-10-21 05:12:18 -03:00 |
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67a785cc22
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fix(cpu): force align thumb and arm block data transfers
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2022-10-21 05:12:18 -03:00 |
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4eb3842606
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feat: pass arm.gba
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2022-10-21 05:12:17 -03:00 |
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1ee8b51b2b
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chore: reimplement ARM LDM/STM
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2022-10-21 05:12:17 -03:00 |
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130310e5cc
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chore: improve arm ldm/stm
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2022-10-21 05:12:17 -03:00 |
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e933d7e5c7
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fix(cpu): force-align SWP reads and writes
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2022-10-21 05:12:17 -03:00 |
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44e8b5b882
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fix: force-align ARM STRH reads
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2022-10-21 05:12:17 -03:00 |
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28361e8b7d
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fix: implement the same LDRSH logic as THUMB LDRSH
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2022-10-21 05:12:16 -03:00 |
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75921d6413
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fix: PC is 12 ahead when it is rd in str and strb
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2022-10-21 05:12:16 -03:00 |
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17226d8f75
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fix: listen to my past self
By deleting this line I go from test 234 to test 355 in arm.gba
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2022-10-21 05:12:16 -03:00 |
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8006ca31e6
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chore: remove unnecessary @as calls
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2022-10-21 05:12:16 -03:00 |
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271f42cf0e
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feat: rename ARM and THUMB SWI functions
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2022-10-21 05:12:13 -03:00 |
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01e15584da
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chore: group THUMB and select ARM instructions together (same file)
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2022-10-21 05:12:13 -03:00 |
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b4e0682801
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fix(cpu): allow for select values to overflow
FuzzARM found these operations which panicked, when they should
have overflowed. These are now fixed
n = 8000
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2022-10-21 05:12:12 -03:00 |
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7dbd2fc556
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fix(cpu): account for rn in rlist in block data transfer
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2022-10-21 05:12:10 -03:00 |
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85e0924669
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feat: implement LDM/STM behaviour when S is set
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2022-10-21 05:12:10 -03:00 |
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97919f646d
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feat(cpu): Pass all LDR/STR ARMwrestler tests
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2022-10-21 05:12:10 -03:00 |
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151de2eab4
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feat(cpu): implement ARM SWP and SWPB
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2022-10-21 05:12:10 -03:00 |
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da681c946e
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feat(cpu): Implement Multiply Long ARM instructions
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2022-10-21 05:12:09 -03:00 |
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443520ecae
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chore: more detailed panic message
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2022-10-21 05:12:09 -03:00 |
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7e6fc44191
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feat(cpu): implement SWP
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2022-10-21 05:12:08 -03:00 |
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9cb4ebaa7f
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fix(cpu): perform MUL with u64s, throw away upper 32 bits
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2022-10-21 05:12:08 -03:00 |
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e1fec48a0e
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fix(cpu): properly decode multiply instructions
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2022-10-21 05:12:07 -03:00 |
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0778ee8dd7
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feat(cpu): implement ARM multiply instructions
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2022-10-21 05:12:07 -03:00 |
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8113146b86
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chore: dedup code in THUMB instructions
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2022-10-21 05:12:05 -03:00 |
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e6625113db
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chore: refactor and genericize ARM data processing calculations
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2022-10-21 05:12:05 -03:00 |
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2643504eb5
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chore: relocate barrel_shifter zig file
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2022-10-21 05:12:05 -03:00 |
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f7518d1bab
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feat(cpu): implement format2 THUMB instructions
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2022-10-21 05:12:05 -03:00 |
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c4e131b92d
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chore: binary logging + file logging + DP chanes + fastBoot changes
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2022-10-21 05:12:02 -03:00 |
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4bdb85834c
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feat(cpu): implement SWI
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2022-10-21 05:12:02 -03:00 |
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8bb7ea6be6
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fix(cpu): interim solution to weird program counter behaviour on illegal tst instruction
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2022-10-21 05:12:01 -03:00 |
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60a1f7fa99
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chore(cpu): implement behaviour for undefined test instruction
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2022-10-21 05:12:01 -03:00 |
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b3b8182f85
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fix(cpu): fix PC offset when barrel shifter and bit 4 of DP is set
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2022-10-21 05:12:01 -03:00 |
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56e660714c
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fix(cpu): implement S set + rd == 15 case for data processing
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2022-10-21 05:12:01 -03:00 |
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eb632056a2
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feat(cpu): implement banked registers
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2022-10-21 05:12:01 -03:00 |
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fbc9de0335
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fix(cpu): improve MRS and MSR instructions
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2022-10-21 05:12:01 -03:00 |
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5c7539cd26
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feat(cpu): implement CMN
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2022-10-21 05:12:00 -03:00 |
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7c20e5fdb5
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fix(barrel_shifter): fix PC being 1 word ahead in barrel shifter
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2022-10-21 05:12:00 -03:00 |
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f79e7126ee
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feat(cpu): Implement RSC
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2022-10-21 05:12:00 -03:00 |
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15e92bc6af
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feat(cpu): implement RSB
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2022-10-21 05:12:00 -03:00 |
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47fc96fe00
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feat(cpu): implement BIC
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2022-10-21 05:12:00 -03:00 |
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4ac5ad42c6
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feat(cpu): implement EOR
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2022-10-21 05:12:00 -03:00 |
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c93153672f
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feat(cpu): implement ADD
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2022-10-21 05:11:59 -03:00 |
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a46dd448f4
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feat(cpu): implement fix for ADC and implement SBC
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2022-10-21 05:11:59 -03:00 |
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01f75112ce
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chore(barrel_shifter): remove panic from ASR
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2022-10-21 05:11:59 -03:00 |
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051b98bc02
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fix(barrel_shifter): should not modify cpsr when amount == 0
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2022-10-21 05:11:59 -03:00 |
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5d0bc1b335
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chore(cpu): refactor the barrel shifter once again
|
2022-10-21 05:11:59 -03:00 |
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43d011538e
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feat(cpu): implement ADC
ADC interacting w/ the Barrel Shifter is not working though
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2022-10-21 05:11:59 -03:00 |
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