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56e660714c
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fix(cpu): implement S set + rd == 15 case for data processing
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2022-10-21 05:12:01 -03:00 |
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5c7539cd26
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feat(cpu): implement CMN
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2022-10-21 05:12:00 -03:00 |
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f79e7126ee
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feat(cpu): Implement RSC
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2022-10-21 05:12:00 -03:00 |
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15e92bc6af
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feat(cpu): implement RSB
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2022-10-21 05:12:00 -03:00 |
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47fc96fe00
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feat(cpu): implement BIC
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2022-10-21 05:12:00 -03:00 |
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4ac5ad42c6
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feat(cpu): implement EOR
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2022-10-21 05:12:00 -03:00 |
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c93153672f
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feat(cpu): implement ADD
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2022-10-21 05:11:59 -03:00 |
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a46dd448f4
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feat(cpu): implement fix for ADC and implement SBC
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2022-10-21 05:11:59 -03:00 |
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5d0bc1b335
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chore(cpu): refactor the barrel shifter once again
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2022-10-21 05:11:59 -03:00 |
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43d011538e
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feat(cpu): implement ADC
ADC interacting w/ the Barrel Shifter is not working though
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2022-10-21 05:11:59 -03:00 |
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2ba09868ba
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feat(cpu): implement ARM SUB in data processing
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2022-10-21 05:11:58 -03:00 |
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9394754593
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feat(cpu): implement MVN
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2022-10-21 05:11:58 -03:00 |
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41bab3d6ba
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chore(cpu): refactor barrel shifter
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2022-10-21 05:11:58 -03:00 |
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99b686b2d7
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fix(cpu): use barrel shifter in data processing immediates
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2022-10-21 05:11:58 -03:00 |
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0eba3aca1f
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chore(cpu): lay groundwork for THUMB instruction decoding and execution
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2022-10-21 05:11:57 -03:00 |
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83a5370196
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chore(cpu): refactor ARM functions to make room for THUMB
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2022-10-21 05:11:56 -03:00 |
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