16 Commits

Author SHA1 Message Date
56e660714c fix(cpu): implement S set + rd == 15 case for data processing 2022-10-21 05:12:01 -03:00
5c7539cd26 feat(cpu): implement CMN 2022-10-21 05:12:00 -03:00
f79e7126ee feat(cpu): Implement RSC 2022-10-21 05:12:00 -03:00
15e92bc6af feat(cpu): implement RSB 2022-10-21 05:12:00 -03:00
47fc96fe00 feat(cpu): implement BIC 2022-10-21 05:12:00 -03:00
4ac5ad42c6 feat(cpu): implement EOR 2022-10-21 05:12:00 -03:00
c93153672f feat(cpu): implement ADD 2022-10-21 05:11:59 -03:00
a46dd448f4 feat(cpu): implement fix for ADC and implement SBC 2022-10-21 05:11:59 -03:00
5d0bc1b335 chore(cpu): refactor the barrel shifter once again 2022-10-21 05:11:59 -03:00
43d011538e feat(cpu): implement ADC
ADC interacting w/ the Barrel Shifter is not working though
2022-10-21 05:11:59 -03:00
2ba09868ba feat(cpu): implement ARM SUB in data processing 2022-10-21 05:11:58 -03:00
9394754593 feat(cpu): implement MVN 2022-10-21 05:11:58 -03:00
41bab3d6ba chore(cpu): refactor barrel shifter 2022-10-21 05:11:58 -03:00
99b686b2d7 fix(cpu): use barrel shifter in data processing immediates 2022-10-21 05:11:58 -03:00
0eba3aca1f chore(cpu): lay groundwork for THUMB instruction decoding and execution 2022-10-21 05:11:57 -03:00
83a5370196 chore(cpu): refactor ARM functions to make room for THUMB 2022-10-21 05:11:56 -03:00