 Rekai Nyangadzayi Musuka
|
2a33716166
|
fix(cpu): fix imm value calculation in MSR
|
2022-10-21 05:11:56 -03:00 |
|
Rekai Nyangadzayi Musuka
|
9b26454c72
|
fix(cpu): resolve off-by-one error when executing LDM
|
2022-10-21 05:11:56 -03:00 |
|
Rekai Nyangadzayi Musuka
|
97b933d9ea
|
feat(cpu): implement branch and exchange
If I want to continue with armwrestler, I'll have to implement
THUMB instructions now
|
2022-10-21 05:11:56 -03:00 |
|
Rekai Nyangadzayi Musuka
|
ff70aadfdb
|
fix(cpu): make Data Processing instructions r15-aware
|
2022-10-21 05:11:55 -03:00 |
|
Rekai Nyangadzayi Musuka
|
ae53f92d40
|
fix(cpu): make LDRH and STRH aware of r15
|
2022-10-21 05:11:55 -03:00 |
|
Rekai Nyangadzayi Musuka
|
f51e1d3154
|
fix(cpu): account for r15 in LDR and STR instructions
|
2022-10-21 05:11:55 -03:00 |
|
Rekai Nyangadzayi Musuka
|
a21f94569f
|
fix(cpu): flip two branches in PSR Transfer execution
|
2022-10-21 05:11:55 -03:00 |
|
Rekai Nyangadzayi Musuka
|
b9255bffe7
|
feat(cpu): implement MSR and MRS
|
2022-10-21 05:11:55 -03:00 |
|
Rekai Nyangadzayi Musuka
|
e1f8400343
|
feat(cpu): stub PSR Transfer instructions
|
2022-10-21 05:11:55 -03:00 |
|
Rekai Nyangadzayi Musuka
|
9a5959e46c
|
fix(cpu): write results of ORR to destination register
|
2022-10-21 05:11:54 -03:00 |
|
Rekai Nyangadzayi Musuka
|
780c717409
|
feat(cpu): implement TEQ
|
2022-10-21 05:11:53 -03:00 |
|
Rekai Nyangadzayi Musuka
|
34c6df344d
|
feat(cpu): Implement ORR
|
2022-10-21 05:11:53 -03:00 |
|
Rekai Nyangadzayi Musuka
|
cffffab8ea
|
feat(cpu): refactor LDM/STM
|
2022-10-21 05:11:53 -03:00 |
|
Rekai Nyangadzayi Musuka
|
527bd2889e
|
feat(cpu): implement LDM/STM
|
2022-10-21 05:11:53 -03:00 |
|
Rekai Nyangadzayi Musuka
|
4f629227ab
|
fix(cpu): fix off-by-word bug in BL
|
2022-10-21 05:11:52 -03:00 |
|
Rekai Nyangadzayi Musuka
|
357211a4cc
|
chore: remove premature inlines
|
2022-10-21 05:11:52 -03:00 |
|
Rekai Nyangadzayi Musuka
|
036b861b05
|
chore: code cleanup
|
2022-10-21 05:11:50 -03:00 |
|
Rekai Nyangadzayi Musuka
|
880546468c
|
chore(bus): refactor bus.zig
|
2022-10-21 05:11:50 -03:00 |
|
Rekai Nyangadzayi Musuka
|
1a9c9ba4cb
|
chore: refactor instruction exec code
|
2022-10-21 05:11:50 -03:00 |
|
Rekai Nyangadzayi Musuka
|
d495f5b4c5
|
feat: implement S (when rd != 15) for several data processing instructions
|
2022-10-21 05:11:49 -03:00 |
|
Rekai Nyangadzayi Musuka
|
788bef188d
|
feat: implement dedicated Barrel Shifter SHL and SHR
|
2022-10-21 05:11:49 -03:00 |
|
Rekai Nyangadzayi Musuka
|
bff9be03cc
|
chore: stub TST
|
2022-10-21 05:11:48 -03:00 |
|
Rekai Nyangadzayi Musuka
|
4b43dcd256
|
fix(cpu): improve LDR/STR write-back logic
|
2022-10-21 05:11:48 -03:00 |
|
Rekai Nyangadzayi Musuka
|
46c694d95a
|
fix(cpu): properly implement SUB/CMP CSPSR carry bit condition
|
2022-10-21 05:11:48 -03:00 |
|
Rekai Nyangadzayi Musuka
|
faced77161
|
fix(cpu): resolve reversed if statement + write back on W = 0
|
2022-10-21 05:11:47 -03:00 |
|
Rekai Nyangadzayi Musuka
|
182392bf1c
|
feat(cpu): properly implement STR STRH and STRB
|
2022-10-21 05:11:46 -03:00 |
|
Rekai Nyangadzayi Musuka
|
cbcc6282df
|
feat(bus): add Io Struct
Also, add more information to all panic messages
|
2022-10-21 05:11:46 -03:00 |
|
Rekai Nyangadzayi Musuka
|
7016fcdb79
|
chore: use bitfield library
|
2022-10-21 05:11:45 -03:00 |
|
Rekai Nyangadzayi Musuka
|
d50aff30c9
|
feat(bus): implement Gameboy Advance MMIO
|
2022-10-21 05:11:45 -03:00 |
|
Rekai Nyangadzayi Musuka
|
c98e8d384a
|
chore: conform to zig style guides
|
2022-10-21 05:11:44 -03:00 |
|
Rekai Nyangadzayi Musuka
|
e841bf44ca
|
chore(cpu): iron out some false assumptions
|
2022-10-21 05:11:44 -03:00 |
|
Rekai Nyangadzayi Musuka
|
1991bd8525
|
feat: implement LDR STR
|
2022-10-21 05:11:44 -03:00 |
|
Rekai Nyangadzayi Musuka
|
6c6d7d463d
|
chore: run zig fmt
|
2022-10-21 05:11:43 -03:00 |
|
Rekai Nyangadzayi Musuka
|
5b3b81e4dc
|
Initial Commit
|
2021-12-29 15:09:00 -06:00 |