2a5cfde49f
fix: 8-bit writes to WIN PPU registers
...
Advance Wars depends on these registers similar to Mario Kart's 8-bit
writes to Affine Background registers:
2022-10-21 05:34:09 -03:00
79af17a457
chore: refactor window
2022-10-21 05:14:22 -03:00
0f18389eb8
chore: crude background window impl (no affine)
2022-10-21 05:14:22 -03:00
da825ad144
chore: rename function (misspelt until now somehow)
2022-10-21 05:14:22 -03:00
4262688fa8
chore(ppu): remove BGR555 -> RGBA888 LUT
...
LUT probably couldn't fit in CPU cache anyways.
TODO: Consider whether LUTs for separate channels (size 32 * 3 * 3
instead of std.math.maxInt(u15))
2022-10-21 05:13:12 -03:00
44b2e9be88
chore(gpio): add missing errdefer
2022-10-21 05:13:11 -03:00
2c88f9bbce
fix(bios): set addr_latch even if bios is skipped
2022-10-21 05:13:09 -03:00
3b144e581a
fix(bus): make open bus impl aware of CPU pipeline
2022-10-21 05:13:09 -03:00
0117a52f4d
style(bus): cpu ptr doesn't need to be optional
2022-10-21 05:13:09 -03:00
3cf7c83269
style: code cleanup
2022-10-21 05:13:09 -03:00
85d4690c56
fix: resolve timing regressions
...
make sure to use fetch timings when fetching instructions
2022-10-21 05:13:08 -03:00
130d40bc7f
fix: rename Pipline to Pipeline
2022-10-21 05:13:08 -03:00
2c928eafec
feat: working pipeline implementation
2022-10-21 05:13:08 -03:00
dcbeeee7cc
chore: refactor ARM/THUMB data processing instructions
2022-10-21 05:13:08 -03:00
84ccb7224b
fix: don't flush pipeline when reloading CPSR in ARM Data Processing
2022-10-21 05:13:08 -03:00
dd4bb4ff03
chore: don't write to CPSR + swap with SPSR at the same time
2022-10-21 05:13:07 -03:00
e29c20019d
fix: advance r15, even when the pipeline is reloaded from the scheduler
...
The PC would fall behind whenever an IRQ was called because the pipeline
was reloaded (+8 to PC), however that was never actually done by any code
Now, the PC is always incremented when the pipeline is reloaded
2022-10-21 05:13:07 -03:00
d8c397248f
chore: dump pipeline state on cpu panic
2022-10-21 05:13:07 -03:00
64aed01869
fix: reimpl THUMB.5 instructions
...
pipeline branch now passes arm.gba and thumb.gba again
(TODO: Stop rewriting my commits away)
2022-10-21 05:13:07 -03:00
29f2a0288f
fix: impl workaround for stage2 miscompilation
2022-10-21 05:13:07 -03:00
27ada16377
chore: instantly refill the pipeline on flush
...
I believe this to be necessary in order to get hardware interrupts
working.
thumb.gba test 108 fails but I'm committing anyways (despite the
regression) because this is kind of rebase/merge hell and I have
something that at least sort of works rn
2022-10-21 05:13:06 -03:00
ad1cec58e7
fix: reimpl handleInterrupt code
2022-10-21 05:13:06 -03:00
97d9edab93
feat: implement basic pipeline
...
passes arm.gba, thumb.gb and armwrestler, fails in actual games
TODO: run FuzzARM debug specific titles
2022-10-21 05:13:06 -03:00
efce1a6dce
chore(emu): refactor code
2022-10-21 05:13:05 -03:00
8b9ab6f4b5
feat(config): add support for (and read from) TOML config file
2022-10-21 05:13:05 -03:00
207a99edbe
style: improve code quality
2022-10-21 05:13:04 -03:00
3c5b30dece
feat: rewrite device ticks
2022-10-21 05:13:04 -03:00
739d38533a
style(scheduler): rename scheduler event handlers
2022-10-21 05:13:04 -03:00
ae6b8e2f03
style: code refactoring
2022-10-21 05:13:04 -03:00
208f4b522d
style(apu): split apu.zig into multiple files + refactor
2022-10-21 05:13:03 -03:00
bd54700103
style(backup): refactor code
2022-10-21 05:13:03 -03:00
08d27520e0
style(flash): move flash code into it's own file
2022-10-21 05:13:03 -03:00
bfe97c671e
style(eeprom): move eeprom code to it's own file
2022-10-21 05:13:03 -03:00
9baadadba2
style(bus): refactor several hardware abstractions
2022-10-21 05:13:03 -03:00
1acc5e35e9
chore: move util.zig
2022-10-21 05:13:02 -03:00
df73cdbecc
chore: disable audio sync by default
...
forgot SDL2 AudioStream doesn't work well for my use-case
2022-10-21 05:13:02 -03:00
6738dfac85
chore: change default settings
2022-10-21 05:13:02 -03:00
11985f4019
chore: reimpl util.escape
...
should make use of stdlib when I can
2022-10-21 05:13:02 -03:00
7cad3aca13
fix: Detect FRAM ROMs
2022-10-21 05:13:01 -03:00
2bbc12cd1a
chore: improve util and Gui API
2022-10-21 05:13:01 -03:00
270db2b5ff
chore: move Gpio and Clock structs to separate file
2022-10-21 05:13:01 -03:00
2d9b03a725
feat: add option to force-enable RTC
2022-10-21 05:13:01 -03:00
c34752ac65
feat: auto-detect RTC in commercial ROMS
2022-10-21 05:13:00 -03:00
60680a36e2
fix: account for lateness in RTC scheduler event
2022-10-21 05:13:00 -03:00
4111bb5e4f
fix: RTC day is 6 bits wide, not 3
2022-10-21 05:13:00 -03:00
612f5fe30e
feat: put RTC Sync on Scheduler
...
TODO: Database to see what games have what GPIO devices
2022-10-21 05:13:00 -03:00
d9776e99d3
chore: import datetime library + default time for RTC
2022-10-21 05:13:00 -03:00
960efcd428
fix: ignore RTC Time/DateTime writes
...
this falls in-line with better emulators
2022-10-21 05:13:00 -03:00
b07dc8484d
chore: use Clock.Writer for Command parsing, delete Clock.Command
2022-10-21 05:12:59 -03:00
ebcae80a9d
feat: implement RTC Read/Writes
2022-10-21 05:12:59 -03:00
