14ba0dbca9
feat: working pipeline implementation
2022-09-28 16:11:25 -03:00
be3ce71a96
fix: advance r15, even when the pipeline is reloaded from the scheduler
...
The PC would fall behind whenever an IRQ was called because the pipeline
was reloaded (+8 to PC), however that was never actually done by any code
Now, the PC is always incremented when the pipeline is reloaded
2022-09-26 16:26:45 -03:00
8e2022dffd
chore: dump pipeline state on cpu panic
2022-09-26 16:26:45 -03:00
41f10c6c12
fix: impl workaround for stage2 miscompilation
2022-09-26 16:26:45 -03:00
d5acfb6eb0
chore: instantly refill the pipeline on flush
...
I believe this to be necessary in order to get hardware interrupts
working.
thumb.gba test 108 fails but I'm committing anyways (despite the
regression) because this is kind of rebase/merge hell and I have
something that at least sort of works rn
2022-09-26 16:26:45 -03:00
6428be5f22
fix: reimpl handleInterrupt code
2022-09-26 16:26:45 -03:00
1d09554ea4
feat: implement basic pipeline
...
passes arm.gba, thumb.gb and armwrestler, fails in actual games
TODO: run FuzzARM debug specific titles
2022-09-26 16:26:45 -03:00
92cfc763c0
chore: move util.zig
2022-09-19 16:07:19 -03:00
fa862f095a
chore: move arm/thumb lut idx functions
2022-09-06 23:58:24 -03:00
5f8c6833f4
chore: improve init/deinit methods
2022-08-29 01:07:25 -05:00
2ab8769b7a
feat: Get ZBA working on Zig's new stage2/stage3 compiler
2022-08-21 12:28:31 -05:00
739db99c83
fix: reimpl debug reads w/out throwing away *const Self
2022-08-07 05:11:29 -05:00
2c8616f610
feat: reimplement cpu logging
2022-07-27 14:50:28 -03:00
53eec5c3ff
chore: don't init bus in Arm7tdmi init
2022-07-27 13:44:24 -03:00
c397b7069d
feat: move arm instr decoding to module
2022-07-27 13:23:29 -03:00
9d037fdc3e
feat: move thumb instr decoding to module
2022-07-27 13:10:58 -03:00
53191b0eeb
chore: change directory structure
2022-07-22 21:11:19 -03:00
