 Rekai Nyangadzayi Musuka
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c4e131b92d
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chore: binary logging + file logging + DP chanes + fastBoot changes
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2022-10-21 05:12:02 -03:00 |
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Rekai Nyangadzayi Musuka
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90e0d9139c
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chore: ignore .bin files
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2022-10-21 05:12:02 -03:00 |
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Rekai Nyangadzayi Musuka
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2e54be76d6
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chore: rename skipBios to fastBoot
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2022-10-21 05:12:02 -03:00 |
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Rekai Nyangadzayi Musuka
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7914268702
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chore: set correct values for select banked registers on fast boot
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2022-10-21 05:12:02 -03:00 |
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Rekai Nyangadzayi Musuka
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4bdb85834c
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feat(cpu): implement SWI
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2022-10-21 05:12:02 -03:00 |
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Rekai Nyangadzayi Musuka
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f89a37936f
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chore(bios): allow reading from BIOS
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2022-10-21 05:12:02 -03:00 |
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Rekai Nyangadzayi Musuka
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8bb7ea6be6
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fix(cpu): interim solution to weird program counter behaviour on illegal tst instruction
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2022-10-21 05:12:01 -03:00 |
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Rekai Nyangadzayi Musuka
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60a1f7fa99
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chore(cpu): implement behaviour for undefined test instruction
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2022-10-21 05:12:01 -03:00 |
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Rekai Nyangadzayi Musuka
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b3b8182f85
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fix(cpu): fix PC offset when barrel shifter and bit 4 of DP is set
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2022-10-21 05:12:01 -03:00 |
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Rekai Nyangadzayi Musuka
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19094b492e
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chore: remove reccomended extension
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2022-10-21 05:12:01 -03:00 |
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Rekai Nyangadzayi Musuka
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56e660714c
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fix(cpu): implement S set + rd == 15 case for data processing
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2022-10-21 05:12:01 -03:00 |
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Rekai Nyangadzayi Musuka
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eb632056a2
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feat(cpu): implement banked registers
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2022-10-21 05:12:01 -03:00 |
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Rekai Nyangadzayi Musuka
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fbc9de0335
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fix(cpu): improve MRS and MSR instructions
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2022-10-21 05:12:01 -03:00 |
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Rekai Nyangadzayi Musuka
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5c7539cd26
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feat(cpu): implement CMN
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2022-10-21 05:12:00 -03:00 |
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Rekai Nyangadzayi Musuka
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7c20e5fdb5
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fix(barrel_shifter): fix PC being 1 word ahead in barrel shifter
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2022-10-21 05:12:00 -03:00 |
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Rekai Nyangadzayi Musuka
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f79e7126ee
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feat(cpu): Implement RSC
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2022-10-21 05:12:00 -03:00 |
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Rekai Nyangadzayi Musuka
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15e92bc6af
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feat(cpu): implement RSB
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2022-10-21 05:12:00 -03:00 |
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Rekai Nyangadzayi Musuka
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47fc96fe00
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feat(cpu): implement BIC
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2022-10-21 05:12:00 -03:00 |
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Rekai Nyangadzayi Musuka
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4ac5ad42c6
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feat(cpu): implement EOR
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2022-10-21 05:12:00 -03:00 |
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Rekai Nyangadzayi Musuka
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c93153672f
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feat(cpu): implement ADD
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2022-10-21 05:11:59 -03:00 |
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Rekai Nyangadzayi Musuka
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a46dd448f4
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feat(cpu): implement fix for ADC and implement SBC
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2022-10-21 05:11:59 -03:00 |
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Rekai Nyangadzayi Musuka
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01f75112ce
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chore(barrel_shifter): remove panic from ASR
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2022-10-21 05:11:59 -03:00 |
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Rekai Nyangadzayi Musuka
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051b98bc02
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fix(barrel_shifter): should not modify cpsr when amount == 0
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2022-10-21 05:11:59 -03:00 |
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Rekai Nyangadzayi Musuka
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5d0bc1b335
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chore(cpu): refactor the barrel shifter once again
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2022-10-21 05:11:59 -03:00 |
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Rekai Nyangadzayi Musuka
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43d011538e
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feat(cpu): implement ADC
ADC interacting w/ the Barrel Shifter is not working though
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2022-10-21 05:11:59 -03:00 |
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Rekai Nyangadzayi Musuka
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f3ad5e90ff
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feat(cpu): implement RRX for Barrel Shifter
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2022-10-21 05:11:58 -03:00 |
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Rekai Nyangadzayi Musuka
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9b867c02e0
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feat(cpu): implement SUB in THUMB format 3
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2022-10-21 05:11:58 -03:00 |
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Rekai Nyangadzayi Musuka
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2ba09868ba
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feat(cpu): implement ARM SUB in data processing
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2022-10-21 05:11:58 -03:00 |
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Rekai Nyangadzayi Musuka
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9394754593
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feat(cpu): implement MVN
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2022-10-21 05:11:58 -03:00 |
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Rekai Nyangadzayi Musuka
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41bab3d6ba
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chore(cpu): refactor barrel shifter
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2022-10-21 05:11:58 -03:00 |
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Rekai Nyangadzayi Musuka
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99b686b2d7
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fix(cpu): use barrel shifter in data processing immediates
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2022-10-21 05:11:58 -03:00 |
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Rekai Nyangadzayi Musuka
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daad98bbfe
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feat(cpu): implement format 12 thumb instructions
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2022-10-21 05:11:57 -03:00 |
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Rekai Nyangadzayi Musuka
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2fb01577af
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feat(cpu): implement some already decoded format 3 instructions
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2022-10-21 05:11:57 -03:00 |
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Rekai Nyangadzayi Musuka
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96d21f27a5
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feat(cpu): implement THUMB format 5 instructions
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2022-10-21 05:11:57 -03:00 |
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Rekai Nyangadzayi Musuka
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793110f315
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chore: mgba log now supports printing THUMB instructions
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2022-10-21 05:11:57 -03:00 |
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Rekai Nyangadzayi Musuka
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5ed5c5d52d
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feat(cpu): implement like 1 THUMB instruction
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2022-10-21 05:11:57 -03:00 |
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Rekai Nyangadzayi Musuka
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01385ee46b
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chore: distinguish between undefined ARM and THUMB instr
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2022-10-21 05:11:57 -03:00 |
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Rekai Nyangadzayi Musuka
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0eba3aca1f
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chore(cpu): lay groundwork for THUMB instruction decoding and execution
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2022-10-21 05:11:57 -03:00 |
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Rekai Nyangadzayi Musuka
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83a5370196
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chore(cpu): refactor ARM functions to make room for THUMB
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2022-10-21 05:11:56 -03:00 |
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Rekai Nyangadzayi Musuka
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b0b6247f06
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fix(cpu): fix conditions for GT cond
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2022-10-21 05:11:56 -03:00 |
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Rekai Nyangadzayi Musuka
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2a33716166
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fix(cpu): fix imm value calculation in MSR
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2022-10-21 05:11:56 -03:00 |
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Rekai Nyangadzayi Musuka
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9b26454c72
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fix(cpu): resolve off-by-one error when executing LDM
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2022-10-21 05:11:56 -03:00 |
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Rekai Nyangadzayi Musuka
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97b933d9ea
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feat(cpu): implement branch and exchange
If I want to continue with armwrestler, I'll have to implement
THUMB instructions now
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2022-10-21 05:11:56 -03:00 |
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Rekai Nyangadzayi Musuka
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ff70aadfdb
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fix(cpu): make Data Processing instructions r15-aware
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2022-10-21 05:11:55 -03:00 |
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Rekai Nyangadzayi Musuka
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ae53f92d40
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fix(cpu): make LDRH and STRH aware of r15
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2022-10-21 05:11:55 -03:00 |
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Rekai Nyangadzayi Musuka
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f51e1d3154
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fix(cpu): account for r15 in LDR and STR instructions
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2022-10-21 05:11:55 -03:00 |
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Rekai Nyangadzayi Musuka
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a21f94569f
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fix(cpu): flip two branches in PSR Transfer execution
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2022-10-21 05:11:55 -03:00 |
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Rekai Nyangadzayi Musuka
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b9255bffe7
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feat(cpu): implement MSR and MRS
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2022-10-21 05:11:55 -03:00 |
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Rekai Nyangadzayi Musuka
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e1f8400343
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feat(cpu): stub PSR Transfer instructions
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2022-10-21 05:11:55 -03:00 |
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Rekai Nyangadzayi Musuka
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52493831cc
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chore(io): implement IE and IME
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2022-10-21 05:11:54 -03:00 |