 Rekai Nyangadzayi Musuka
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8113146b86
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chore: dedup code in THUMB instructions
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2022-10-21 05:12:05 -03:00 |
|
Rekai Nyangadzayi Musuka
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e6625113db
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chore: refactor and genericize ARM data processing calculations
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2022-10-21 05:12:05 -03:00 |
|
Rekai Nyangadzayi Musuka
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2643504eb5
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chore: relocate barrel_shifter zig file
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2022-10-21 05:12:05 -03:00 |
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Rekai Nyangadzayi Musuka
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f7518d1bab
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feat(cpu): implement format2 THUMB instructions
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2022-10-21 05:12:05 -03:00 |
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Rekai Nyangadzayi Musuka
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800ca798cd
|
feat(cpu): implement format19 THUMB instructions
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2022-10-21 05:12:05 -03:00 |
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Rekai Nyangadzayi Musuka
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7bc186a03c
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feat(cpu): implement format16 THUMB instructions
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2022-10-21 05:12:04 -03:00 |
|
Rekai Nyangadzayi Musuka
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b94b87d186
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feat(cpu): implement format 1 THUMB instructions
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2022-10-21 05:12:04 -03:00 |
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Rekai Nyangadzayi Musuka
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93922b65e3
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feat(cpu): implement format 6 THUMB instructions
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2022-10-21 05:12:04 -03:00 |
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Rekai Nyangadzayi Musuka
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c4e131b92d
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chore: binary logging + file logging + DP chanes + fastBoot changes
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2022-10-21 05:12:02 -03:00 |
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Rekai Nyangadzayi Musuka
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4bdb85834c
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feat(cpu): implement SWI
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2022-10-21 05:12:02 -03:00 |
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Rekai Nyangadzayi Musuka
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8bb7ea6be6
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fix(cpu): interim solution to weird program counter behaviour on illegal tst instruction
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2022-10-21 05:12:01 -03:00 |
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Rekai Nyangadzayi Musuka
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60a1f7fa99
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chore(cpu): implement behaviour for undefined test instruction
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2022-10-21 05:12:01 -03:00 |
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Rekai Nyangadzayi Musuka
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b3b8182f85
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fix(cpu): fix PC offset when barrel shifter and bit 4 of DP is set
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2022-10-21 05:12:01 -03:00 |
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Rekai Nyangadzayi Musuka
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56e660714c
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fix(cpu): implement S set + rd == 15 case for data processing
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2022-10-21 05:12:01 -03:00 |
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Rekai Nyangadzayi Musuka
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eb632056a2
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feat(cpu): implement banked registers
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2022-10-21 05:12:01 -03:00 |
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Rekai Nyangadzayi Musuka
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fbc9de0335
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fix(cpu): improve MRS and MSR instructions
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2022-10-21 05:12:01 -03:00 |
|
Rekai Nyangadzayi Musuka
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5c7539cd26
|
feat(cpu): implement CMN
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2022-10-21 05:12:00 -03:00 |
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Rekai Nyangadzayi Musuka
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7c20e5fdb5
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fix(barrel_shifter): fix PC being 1 word ahead in barrel shifter
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2022-10-21 05:12:00 -03:00 |
|
Rekai Nyangadzayi Musuka
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f79e7126ee
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feat(cpu): Implement RSC
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2022-10-21 05:12:00 -03:00 |
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Rekai Nyangadzayi Musuka
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15e92bc6af
|
feat(cpu): implement RSB
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2022-10-21 05:12:00 -03:00 |
|
Rekai Nyangadzayi Musuka
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47fc96fe00
|
feat(cpu): implement BIC
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2022-10-21 05:12:00 -03:00 |
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Rekai Nyangadzayi Musuka
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4ac5ad42c6
|
feat(cpu): implement EOR
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2022-10-21 05:12:00 -03:00 |
|
Rekai Nyangadzayi Musuka
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c93153672f
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feat(cpu): implement ADD
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2022-10-21 05:11:59 -03:00 |
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Rekai Nyangadzayi Musuka
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a46dd448f4
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feat(cpu): implement fix for ADC and implement SBC
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2022-10-21 05:11:59 -03:00 |
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Rekai Nyangadzayi Musuka
|
01f75112ce
|
chore(barrel_shifter): remove panic from ASR
|
2022-10-21 05:11:59 -03:00 |
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Rekai Nyangadzayi Musuka
|
051b98bc02
|
fix(barrel_shifter): should not modify cpsr when amount == 0
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2022-10-21 05:11:59 -03:00 |
|
Rekai Nyangadzayi Musuka
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5d0bc1b335
|
chore(cpu): refactor the barrel shifter once again
|
2022-10-21 05:11:59 -03:00 |
|
Rekai Nyangadzayi Musuka
|
43d011538e
|
feat(cpu): implement ADC
ADC interacting w/ the Barrel Shifter is not working though
|
2022-10-21 05:11:59 -03:00 |
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Rekai Nyangadzayi Musuka
|
f3ad5e90ff
|
feat(cpu): implement RRX for Barrel Shifter
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2022-10-21 05:11:58 -03:00 |
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Rekai Nyangadzayi Musuka
|
9b867c02e0
|
feat(cpu): implement SUB in THUMB format 3
|
2022-10-21 05:11:58 -03:00 |
|
Rekai Nyangadzayi Musuka
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2ba09868ba
|
feat(cpu): implement ARM SUB in data processing
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2022-10-21 05:11:58 -03:00 |
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Rekai Nyangadzayi Musuka
|
9394754593
|
feat(cpu): implement MVN
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2022-10-21 05:11:58 -03:00 |
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Rekai Nyangadzayi Musuka
|
41bab3d6ba
|
chore(cpu): refactor barrel shifter
|
2022-10-21 05:11:58 -03:00 |
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Rekai Nyangadzayi Musuka
|
99b686b2d7
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fix(cpu): use barrel shifter in data processing immediates
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2022-10-21 05:11:58 -03:00 |
|
Rekai Nyangadzayi Musuka
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daad98bbfe
|
feat(cpu): implement format 12 thumb instructions
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2022-10-21 05:11:57 -03:00 |
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Rekai Nyangadzayi Musuka
|
2fb01577af
|
feat(cpu): implement some already decoded format 3 instructions
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2022-10-21 05:11:57 -03:00 |
|
Rekai Nyangadzayi Musuka
|
96d21f27a5
|
feat(cpu): implement THUMB format 5 instructions
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2022-10-21 05:11:57 -03:00 |
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Rekai Nyangadzayi Musuka
|
5ed5c5d52d
|
feat(cpu): implement like 1 THUMB instruction
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2022-10-21 05:11:57 -03:00 |
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Rekai Nyangadzayi Musuka
|
0eba3aca1f
|
chore(cpu): lay groundwork for THUMB instruction decoding and execution
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2022-10-21 05:11:57 -03:00 |
|
Rekai Nyangadzayi Musuka
|
83a5370196
|
chore(cpu): refactor ARM functions to make room for THUMB
|
2022-10-21 05:11:56 -03:00 |
|
Rekai Nyangadzayi Musuka
|
2a33716166
|
fix(cpu): fix imm value calculation in MSR
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2022-10-21 05:11:56 -03:00 |
|
Rekai Nyangadzayi Musuka
|
9b26454c72
|
fix(cpu): resolve off-by-one error when executing LDM
|
2022-10-21 05:11:56 -03:00 |
|
Rekai Nyangadzayi Musuka
|
97b933d9ea
|
feat(cpu): implement branch and exchange
If I want to continue with armwrestler, I'll have to implement
THUMB instructions now
|
2022-10-21 05:11:56 -03:00 |
|
Rekai Nyangadzayi Musuka
|
ff70aadfdb
|
fix(cpu): make Data Processing instructions r15-aware
|
2022-10-21 05:11:55 -03:00 |
|
Rekai Nyangadzayi Musuka
|
ae53f92d40
|
fix(cpu): make LDRH and STRH aware of r15
|
2022-10-21 05:11:55 -03:00 |
|
Rekai Nyangadzayi Musuka
|
f51e1d3154
|
fix(cpu): account for r15 in LDR and STR instructions
|
2022-10-21 05:11:55 -03:00 |
|
Rekai Nyangadzayi Musuka
|
a21f94569f
|
fix(cpu): flip two branches in PSR Transfer execution
|
2022-10-21 05:11:55 -03:00 |
|
Rekai Nyangadzayi Musuka
|
b9255bffe7
|
feat(cpu): implement MSR and MRS
|
2022-10-21 05:11:55 -03:00 |
|
Rekai Nyangadzayi Musuka
|
e1f8400343
|
feat(cpu): stub PSR Transfer instructions
|
2022-10-21 05:11:55 -03:00 |
|
Rekai Nyangadzayi Musuka
|
9a5959e46c
|
fix(cpu): write results of ORR to destination register
|
2022-10-21 05:11:54 -03:00 |
|
Rekai Nyangadzayi Musuka
|
780c717409
|
feat(cpu): implement TEQ
|
2022-10-21 05:11:53 -03:00 |
|
Rekai Nyangadzayi Musuka
|
34c6df344d
|
feat(cpu): Implement ORR
|
2022-10-21 05:11:53 -03:00 |
|
Rekai Nyangadzayi Musuka
|
cffffab8ea
|
feat(cpu): refactor LDM/STM
|
2022-10-21 05:11:53 -03:00 |
|
Rekai Nyangadzayi Musuka
|
527bd2889e
|
feat(cpu): implement LDM/STM
|
2022-10-21 05:11:53 -03:00 |
|
Rekai Nyangadzayi Musuka
|
4f629227ab
|
fix(cpu): fix off-by-word bug in BL
|
2022-10-21 05:11:52 -03:00 |
|
Rekai Nyangadzayi Musuka
|
357211a4cc
|
chore: remove premature inlines
|
2022-10-21 05:11:52 -03:00 |
|
Rekai Nyangadzayi Musuka
|
036b861b05
|
chore: code cleanup
|
2022-10-21 05:11:50 -03:00 |
|
Rekai Nyangadzayi Musuka
|
880546468c
|
chore(bus): refactor bus.zig
|
2022-10-21 05:11:50 -03:00 |
|
Rekai Nyangadzayi Musuka
|
1a9c9ba4cb
|
chore: refactor instruction exec code
|
2022-10-21 05:11:50 -03:00 |
|
Rekai Nyangadzayi Musuka
|
d495f5b4c5
|
feat: implement S (when rd != 15) for several data processing instructions
|
2022-10-21 05:11:49 -03:00 |
|
Rekai Nyangadzayi Musuka
|
788bef188d
|
feat: implement dedicated Barrel Shifter SHL and SHR
|
2022-10-21 05:11:49 -03:00 |
|
Rekai Nyangadzayi Musuka
|
bff9be03cc
|
chore: stub TST
|
2022-10-21 05:11:48 -03:00 |
|
Rekai Nyangadzayi Musuka
|
4b43dcd256
|
fix(cpu): improve LDR/STR write-back logic
|
2022-10-21 05:11:48 -03:00 |
|
Rekai Nyangadzayi Musuka
|
46c694d95a
|
fix(cpu): properly implement SUB/CMP CSPSR carry bit condition
|
2022-10-21 05:11:48 -03:00 |
|
Rekai Nyangadzayi Musuka
|
faced77161
|
fix(cpu): resolve reversed if statement + write back on W = 0
|
2022-10-21 05:11:47 -03:00 |
|
Rekai Nyangadzayi Musuka
|
182392bf1c
|
feat(cpu): properly implement STR STRH and STRB
|
2022-10-21 05:11:46 -03:00 |
|
Rekai Nyangadzayi Musuka
|
cbcc6282df
|
feat(bus): add Io Struct
Also, add more information to all panic messages
|
2022-10-21 05:11:46 -03:00 |
|
Rekai Nyangadzayi Musuka
|
7016fcdb79
|
chore: use bitfield library
|
2022-10-21 05:11:45 -03:00 |
|
Rekai Nyangadzayi Musuka
|
d50aff30c9
|
feat(bus): implement Gameboy Advance MMIO
|
2022-10-21 05:11:45 -03:00 |
|
Rekai Nyangadzayi Musuka
|
c98e8d384a
|
chore: conform to zig style guides
|
2022-10-21 05:11:44 -03:00 |
|
Rekai Nyangadzayi Musuka
|
e841bf44ca
|
chore(cpu): iron out some false assumptions
|
2022-10-21 05:11:44 -03:00 |
|
Rekai Nyangadzayi Musuka
|
1991bd8525
|
feat: implement LDR STR
|
2022-10-21 05:11:44 -03:00 |
|
Rekai Nyangadzayi Musuka
|
6c6d7d463d
|
chore: run zig fmt
|
2022-10-21 05:11:43 -03:00 |
|
Rekai Nyangadzayi Musuka
|
5b3b81e4dc
|
Initial Commit
|
2021-12-29 15:09:00 -06:00 |