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fix(cpu): improve MRS and MSR instructions

This commit is contained in:
Rekai Nyangadzayi Musuka 2022-10-21 05:12:01 -03:00
parent 5c7539cd26
commit fbc9de0335
2 changed files with 41 additions and 30 deletions
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5
src/cpu.zig
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@ -201,9 +201,10 @@ fn armPopulate() [0x1000]ArmInstrFn {
if (i >> 10 & 0x3 == 0b00 and i >> 7 & 0x3 == 0b10 and i >> 4 & 1 == 0) { if (i >> 10 & 0x3 == 0b00 and i >> 7 & 0x3 == 0b10 and i >> 4 & 1 == 0) {
// PSR Transfer // PSR Transfer
const I = i >> 9 & 1 == 1; const I = i >> 9 & 1 == 1;
const isSpsr = i >> 6 & 1 == 1; const R = i >> 6 & 1 == 1;
const kind = i >> 4 & 0x3;
lut[i] = psrTransfer(I, isSpsr); lut[i] = psrTransfer(I, R, kind);
} }
if (i == 0x121) { if (i == 0x121) {

66
src/cpu/arm/psr_transfer.zig
View File

@ -3,49 +3,59 @@ const std = @import("std");
const Bus = @import("../../Bus.zig"); const Bus = @import("../../Bus.zig");
const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi; const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
const InstrFn = @import("../../cpu.zig").ArmInstrFn; const InstrFn = @import("../../cpu.zig").ArmInstrFn;
const PSR = @import("../../cpu.zig").PSR;
pub fn psrTransfer(comptime I: bool, comptime isSpsr: bool) InstrFn { pub fn psrTransfer(comptime I: bool, comptime R: bool, comptime kind: u2) InstrFn {
return struct { return struct {
fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u32) void { fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u32) void {
switch (@truncate(u3, opcode >> 19)) { switch (kind) {
0b001 => { 0b00 => {
// MRS // MRS
const rn = opcode >> 12 & 0xF; const rd = opcode >> 12 & 0xF;
if (isSpsr) { if (R) {
std.debug.panic("[CPU] TODO: MRS on SPSR_<current_mode> is unimplemented", .{}); std.debug.panic("[CPU/PSR Transfer] TODO: MRS on SPSR_<current_mode> is unimplemented", .{});
} else { } else {
cpu.r[rn] = cpu.cpsr.raw; cpu.r[rd] = cpu.cpsr.raw;
} }
}, },
0b101 => { 0b10 => {
// MSR // MSR
const rm = opcode & 0xF; const field_mask = @truncate(u4, opcode >> 16 & 0xF);
switch (@truncate(u3, opcode >> 16)) { if (I) {
0b000 => { const imm = std.math.rotr(u32, opcode & 0xFF, (opcode >> 8 & 0xF) << 1);
const right = if (I) std.math.rotr(u32, opcode & 0xFF, opcode >> 7 & 0xF) else cpu.r[rm];
if (isSpsr) { if (R) {
std.debug.panic("[CPU] TODO: MSR (flags only) on SPSR_<current_mode> is unimplemented", .{}); std.debug.panic("[CPU/PSR Transfer] TODO: MSR (flags only) on SPSR_<current_mode> is unimplemented", .{});
} else { } else {
const mask: u32 = 0xF000_0000; cpu.cpsr.raw = fieldMask(&cpu.cpsr, field_mask, imm);
cpu.cpsr.raw = (cpu.cpsr.raw & ~mask) | (right & mask); }
} } else {
}, const rm_idx = opcode & 0xF;
0b001 => {
if (isSpsr) {
std.debug.panic("[CPU] TODO: MSR on SPSR_<current_mode> is unimplemented", .{});
} else {
cpu.cpsr = .{ .raw = cpu.r[rm] };
}
},
else => unreachable, if (R) {
std.debug.panic("[CPU/PSR Transfer] TODO: MSR on SPSR_<current_mode> is unimplemented", .{});
} else {
cpu.cpsr.raw = fieldMask(&cpu.cpsr, field_mask, cpu.r[rm_idx]);
}
} }
}, },
else => unreachable, else => std.debug.panic("[CPU/PSR Transfer] Bits 21:220 of {X:0>8} are undefined", .{opcode}),
} }
} }
}.inner; }.inner;
} }
fn fieldMask(psr: *const PSR, field_mask: u4, right: u32) u32 {
const bits = @truncate(u2, (field_mask >> 2 & 0x2) | (field_mask & 1));
const mask: u32 = switch (bits) {
0b00 => 0x0000_0000,
0b01 => 0x0000_00FF,
0b10 => 0xF000_0000,
0b11 => 0xF000_00FF,
};
return (psr.raw & ~mask) | (right & mask);
}