chore: refactor instruction exec code

src/cpu/branch.zig

@@ -0,0 +1,19 @@
+const arm = @import("../cpu.zig");
+const util = @import("../util.zig");
+
+const Bus = @import("../bus.zig").Bus;
+
+const Arm7tdmi = arm.Arm7tdmi;
+const InstrFn = arm.InstrFn;
+
+pub fn branch(comptime L: bool) InstrFn {
+    return struct {
+        fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u32) void {
+            if (L) {
+                cpu.r[14] = cpu.r[15] - 4;
+            }
+
+            cpu.r[15] = cpu.fakePC() +% util.u32SignExtend(24, opcode << 2);
+        }
+    }.inner;
+}

src/cpu/data_processing.zig

@@ -6,9 +6,9 @@ const Bus = @import("../bus.zig").Bus;
 const Arm7tdmi = arm.Arm7tdmi;
 const InstrFn = arm.InstrFn;
 
-pub fn comptimeDataProcessing(comptime I: bool, comptime S: bool, comptime instrKind: u4) InstrFn {
+pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime instrKind: u4) InstrFn {
     return struct {
-        fn dataProcessing(cpu: *Arm7tdmi, _: *Bus, opcode: u32) void {
+        fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u32) void {
             const rd = opcode >> 12 & 0xF;
             const op1 = opcode >> 16 & 0xF;
 
@@ -68,5 +68,5 @@ pub fn comptimeDataProcessing(comptime I: bool, comptime S: bool, comptime instr
                 else => std.debug.panic("[CPU] TODO: implement data processing type {}", .{instrKind}),
             }
         }
-    }.dataProcessing;
+    }.inner;
 }

src/cpu/half_signed_data_transfer.zig

@@ -6,9 +6,9 @@ const Bus = @import("../bus.zig").Bus;
 const Arm7tdmi = arm.Arm7tdmi;
 const InstrFn = arm.InstrFn;
 
-pub fn comptimeHalfSignedDataTransfer(comptime P: bool, comptime U: bool, comptime I: bool, comptime W: bool, comptime L: bool) InstrFn {
+pub fn halfAndSignedDataTransfer(comptime P: bool, comptime U: bool, comptime I: bool, comptime W: bool, comptime L: bool) InstrFn {
     return struct {
-        fn halfSignedDataTransfer(cpu: *Arm7tdmi, bus: *Bus, opcode: u32) void {
+        fn inner(cpu: *Arm7tdmi, bus: *Bus, opcode: u32) void {
             const rn = opcode >> 16 & 0xF;
             const rd = opcode >> 12 & 0xF;
             const rm = opcode & 0xF;
@@ -59,5 +59,5 @@ pub fn comptimeHalfSignedDataTransfer(comptime P: bool, comptime U: bool, compti
             address = modified_base;
             if (W and P or !P) cpu.r[rn] = address;
         }
-    }.halfSignedDataTransfer;
+    }.inner;
 }

src/cpu/single_data_transfer.zig

@@ -8,9 +8,9 @@ const Arm7tdmi = arm.Arm7tdmi;
 const InstrFn = arm.InstrFn;
 const CPSR = arm.CPSR;
 
-pub fn comptimeSingleDataTransfer(comptime I: bool, comptime P: bool, comptime U: bool, comptime B: bool, comptime W: bool, comptime L: bool) InstrFn {
+pub fn singleDataTransfer(comptime I: bool, comptime P: bool, comptime U: bool, comptime B: bool, comptime W: bool, comptime L: bool) InstrFn {
     return struct {
-        fn singleDataTransfer(cpu: *Arm7tdmi, bus: *Bus, opcode: u32) void {
+        fn inner(cpu: *Arm7tdmi, bus: *Bus, opcode: u32) void {
             const rn = opcode >> 16 & 0xF;
             const rd = opcode >> 12 & 0xF;
 
@@ -46,7 +46,7 @@ pub fn comptimeSingleDataTransfer(comptime I: bool, comptime P: bool, comptime U
 
             // TODO: W-bit forces non-privledged mode for the transfer
         }
-    }.singleDataTransfer;
+    }.inner;
 }
 
 fn registerOffset(cpu: *Arm7tdmi, opcode: u32) u32 {