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feat(cpu): implement format2 THUMB instructions

This commit is contained in:
Rekai Nyangadzayi Musuka 2022-10-21 05:12:05 -03:00
parent 800ca798cd
commit f7518d1bab
3 changed files with 61 additions and 18 deletions
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8
src/cpu.zig
View File

@ -22,6 +22,7 @@ const softwareInterrupt = @import("cpu/arm/software_interrupt.zig").softwareInte
// THUMB Instruction Groups
const format1 = @import("cpu/thumb/format1.zig").format1;
const format3 = @import("cpu/thumb/format3.zig").format3;
const format2 = @import("cpu/thumb/format2.zig").format2;
const format5 = @import("cpu/thumb/format5.zig").format5;
const format6 = @import("cpu/thumb/format6.zig").format6;
const format12 = @import("cpu/thumb/format12.zig").format12;
@ -332,6 +333,13 @@ fn thumbPopulate() [0x400]ThumbInstrFn {
lut[i] = format1(op, offset);
}
if (i >> 5 & 0x1F == 0b00011) {
const I = i >> 4 & 1 == 1;
const is_sub = i >> 3 & 1 == 1;
const rn = i & 0x7;
lut[i] = format2(I, is_sub, rn);
}
if (i >> 7 & 0x7 == 0b001) {
const op = i >> 5 & 0x3;

38
src/cpu/arm/data_processing.zig
View File

@ -43,23 +43,7 @@ pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime instrKind: u4
},
0x2 => cpu.r[rd] = sub(S, cpu, rd, op1, op2), // SUB
0x3 => cpu.r[rd] = sub(S, cpu, rd, op2, op1), // RSB
0x4 => {
// ADD
var result: u32 = undefined;
const didOverflow = @addWithOverflow(u32, op1, op2, &result);
cpu.r[rd] = result;
if (S) {
if (rd == 0xF) {
cpu.setCpsr(cpu.spsr.raw);
} else {
cpu.cpsr.n.write(result >> 31 & 1 == 1);
cpu.cpsr.z.write(result == 0);
cpu.cpsr.c.write(didOverflow);
cpu.cpsr.v.write(((op1 ^ result) & (op2 ^ result)) >> 31 & 1 == 1);
}
}
},
0x4 => cpu.r[rd] = add(S, cpu, rd, op1, op2), // ADD
0x5 => {
// ADC
var result: u32 = undefined;
@ -181,7 +165,7 @@ fn sbc(comptime S: bool, cpu: *Arm7tdmi, rd: u4, left: u32, right: u32, old_carr
return result;
}
fn sub(comptime S: bool, cpu: *Arm7tdmi, rd: u4, left: u32, right: u32) u32 {
pub fn sub(comptime S: bool, cpu: *Arm7tdmi, rd: u4, left: u32, right: u32) u32 {
const result = left -% right;
if (S) {
@ -198,6 +182,24 @@ fn sub(comptime S: bool, cpu: *Arm7tdmi, rd: u4, left: u32, right: u32) u32 {
return result;
}
pub fn add(comptime S: bool, cpu: *Arm7tdmi, rd: u4, left: u32, right: u32) u32 {
var result: u32 = undefined;
const didOverflow = @addWithOverflow(u32, left, right, &result);
if (S) {
if (rd == 0xF) {
cpu.setCpsr(cpu.spsr.raw);
} else {
cpu.cpsr.n.write(result >> 31 & 1 == 1);
cpu.cpsr.z.write(result == 0);
cpu.cpsr.c.write(didOverflow);
cpu.cpsr.v.write(((left ^ result) & (right ^ result)) >> 31 & 1 == 1);
}
}
return result;
}
fn logicFlags(comptime S: bool, cpu: *Arm7tdmi, rd: u4, result: u32) void {
if (S) {
if (rd == 0xF) {

33
src/cpu/thumb/format2.zig Normal file
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@ -0,0 +1,33 @@
const std = @import("std");
const Bus = @import("../../Bus.zig");
const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
const InstrFn = @import("../../cpu.zig").ThumbInstrFn;
const add = @import("../arm/data_processing.zig").add;
const sub = @import("../arm/data_processing.zig").sub;
pub fn format2(comptime I: bool, is_sub: bool, rn: u3) InstrFn {
return struct {
fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void {
const rs = opcode >> 3 & 0x7;
const rd = @truncate(u3, opcode);
if (is_sub) {
// SUB
cpu.r[rd] = if (I) blk: {
break :blk sub(true, cpu, rd, cpu.r[rs], @as(u32, rn));
} else blk: {
break :blk sub(true, cpu, rd, cpu.r[rs], cpu.r[rn]);
};
} else {
// ADD
cpu.r[rd] = if (I) blk: {
break :blk add(true, cpu, rd, cpu.r[rs], @as(u32, rn));
} else blk: {
break :blk add(true, cpu, rd, cpu.r[rs], cpu.r[rn]);
};
}
}
}.inner;
}