feat(sched): add HBlank and VBlank events to the scheduler
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parent
5037b8f0cc
commit
f709458638
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@ -1,5 +1,6 @@
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const std = @import("std");
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const std = @import("std");
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const Scheduler = @import("scheduler.zig").Scheduler;
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const Io = @import("bus/io.zig").Io;
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const Io = @import("bus/io.zig").Io;
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const Bios = @import("bus/bios.zig").Bios;
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const Bios = @import("bus/bios.zig").Bios;
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const GamePak = @import("bus/pak.zig").GamePak;
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const GamePak = @import("bus/pak.zig").GamePak;
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@ -13,11 +14,11 @@ pub const Bus = struct {
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ppu: Ppu,
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ppu: Ppu,
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io: Io,
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io: Io,
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pub fn init(alloc: Allocator, path: []const u8) !@This() {
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pub fn init(alloc: Allocator, sched: *Scheduler, path: []const u8) !@This() {
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return @This(){
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return @This(){
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.pak = try GamePak.init(alloc, path),
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.pak = try GamePak.init(alloc, path),
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.bios = try Bios.init(alloc, "./bin/gba_bios.bin"), // TODO: don't hardcode this + bundle open-sorce Boot ROM
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.bios = try Bios.init(alloc, "./bin/gba_bios.bin"), // TODO: don't hardcode this + bundle open-sorce Boot ROM
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.ppu = try Ppu.init(alloc),
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.ppu = try Ppu.init(alloc, sched),
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.io = Io.init(),
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.io = Io.init(),
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};
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};
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}
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}
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@ -18,14 +18,14 @@ const arm_lut: [0x1000]InstrFn = populate();
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pub const Arm7tdmi = struct {
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pub const Arm7tdmi = struct {
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r: [16]u32,
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r: [16]u32,
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sch: *Scheduler,
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sched: *Scheduler,
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bus: *Bus,
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bus: *Bus,
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cpsr: CPSR,
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cpsr: CPSR,
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pub fn init(scheduler: *Scheduler, bus: *Bus) @This() {
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pub fn init(sched: *Scheduler, bus: *Bus) @This() {
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return .{
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return .{
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.r = [_]u32{0x00} ** 16,
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.r = [_]u32{0x00} ** 16,
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.sch = scheduler,
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.sched = sched,
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.bus = bus,
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.bus = bus,
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.cpsr = .{ .raw = 0x0000_00DF },
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.cpsr = .{ .raw = 0x0000_00DF },
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};
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};
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@ -4,14 +4,14 @@ const Bus = @import("bus.zig").Bus;
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const cycles_per_frame: u64 = 100; // TODO: How many cycles actually?
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const cycles_per_frame: u64 = 100; // TODO: How many cycles actually?
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pub fn runFrame(sch: *Scheduler, cpu: *Arm7tdmi, bus: *Bus) void {
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pub fn runFrame(sched: *Scheduler, cpu: *Arm7tdmi, bus: *Bus) void {
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var cycles: u64 = 0;
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var cycles: u64 = 0;
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while (cycles < cycles_per_frame) : (cycles += 1) {
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while (cycles < cycles_per_frame) : (cycles += 1) {
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sch.tick += 1;
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sched.tick += 1;
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_ = cpu.step();
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_ = cpu.step();
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while (sch.tick >= sch.nextTimestamp()) {
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while (sched.tick >= sched.nextTimestamp()) {
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sch.handleEvent(cpu, bus);
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sched.handleEvent(cpu, bus);
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}
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}
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}
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}
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}
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}
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@ -23,12 +23,12 @@ pub fn main() anyerror!void {
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return;
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return;
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}
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}
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var bus = try Bus.init(alloc, zba_args[0]);
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defer bus.deinit();
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var scheduler = Scheduler.init(alloc);
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var scheduler = Scheduler.init(alloc);
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defer scheduler.deinit();
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defer scheduler.deinit();
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var bus = try Bus.init(alloc, &scheduler, zba_args[0]);
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defer bus.deinit();
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var cpu = Arm7tdmi.init(&scheduler, &bus);
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var cpu = Arm7tdmi.init(&scheduler, &bus);
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cpu.skipBios();
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cpu.skipBios();
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@ -1,15 +1,18 @@
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const std = @import("std");
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const std = @import("std");
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const Allocator = std.mem.Allocator;
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const Allocator = std.mem.Allocator;
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const Scheduler = @import("scheduler.zig").Scheduler;
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pub const Ppu = struct {
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pub const Ppu = struct {
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vram: Vram,
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vram: Vram,
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palette: Palette,
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palette: Palette,
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sched: *Scheduler,
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pub fn init(alloc: Allocator) !@This() {
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pub fn init(alloc: Allocator, sched: *Scheduler) !@This() {
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return @This(){
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return @This(){
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.vram = try Vram.init(alloc),
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.vram = try Vram.init(alloc),
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.palette = try Palette.init(alloc),
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.palette = try Palette.init(alloc),
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.sched = sched,
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};
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};
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}
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}
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@ -35,6 +35,12 @@ pub const Scheduler = struct {
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.HeatDeath => {
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.HeatDeath => {
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std.debug.panic("[Scheduler] Somehow, a u64 overflowed", .{});
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std.debug.panic("[Scheduler] Somehow, a u64 overflowed", .{});
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},
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},
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.HBlank => {
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std.debug.panic("[Scheduler] tick {}: Hblank", .{self.tick});
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},
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.VBlank => {
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std.debug.panic("[Scheduler] tick {}: VBlank", .{self.tick});
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},
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}
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}
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}
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}
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}
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}
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@ -57,4 +63,6 @@ fn lessThan(_: void, a: Event, b: Event) Order {
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pub const EventKind = enum {
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pub const EventKind = enum {
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HeatDeath,
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HeatDeath,
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HBlank,
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VBlank,
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};
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};
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