chore: refactor ARM/THUMB data processing instructions
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parent
f616ed29d1
commit
f466ae2ae2
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@ -24,7 +24,7 @@ pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime kind: u4) Ins
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if (!I and opcode >> 4 & 1 == 1) cpu.r[15] -= 4;
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var result: u32 = undefined;
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var didOverflow: bool = undefined;
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var overflow: bool = undefined;
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// Perform Data Processing Logic
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switch (kind) {
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@ -32,8 +32,8 @@ pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime kind: u4) Ins
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0x1 => result = op1 ^ op2, // EOR
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0x2 => result = op1 -% op2, // SUB
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0x3 => result = op2 -% op1, // RSB
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0x4 => result = newAdd(&didOverflow, op1, op2), // ADD
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0x5 => result = newAdc(&didOverflow, op1, op2, old_carry), // ADC
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0x4 => result = add(&overflow, op1, op2), // ADD
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0x5 => result = adc(&overflow, op1, op2, old_carry), // ADC
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0x6 => result = sbc(op1, op2, old_carry), // SBC
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0x7 => result = sbc(op2, op1, old_carry), // RSC
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0x8 => {
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@ -62,7 +62,7 @@ pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime kind: u4) Ins
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if (rd == 0xF)
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return undefinedTestBehaviour(cpu);
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didOverflow = @addWithOverflow(u32, op1, op2, &result);
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overflow = @addWithOverflow(u32, op1, op2, &result);
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},
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0xC => result = op1 | op2, // ORR
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0xD => result = op2, // MOV
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@ -111,7 +111,7 @@ pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime kind: u4) Ins
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// ADD, ADC Flags
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cpu.cpsr.n.write(result >> 31 & 1 == 1);
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cpu.cpsr.z.write(result == 0);
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cpu.cpsr.c.write(didOverflow);
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cpu.cpsr.c.write(overflow);
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cpu.cpsr.v.write(((op1 ^ result) & (op2 ^ result)) >> 31 & 1 == 1);
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},
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0x6, 0x7 => if (S and rd != 0xF) {
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@ -142,7 +142,7 @@ pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime kind: u4) Ins
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cpu.cpsr.v.write(((op1 ^ result) & (~op2 ^ result)) >> 31 & 1 == 1);
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} else if (kind == 0xB) {
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// CMN specific
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cpu.cpsr.c.write(didOverflow);
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cpu.cpsr.c.write(overflow);
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cpu.cpsr.v.write(((op1 ^ result) & (op2 ^ result)) >> 31 & 1 == 1);
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} else {
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// TST, TEQ specific
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@ -163,65 +163,21 @@ pub fn sbc(left: u32, right: u32, old_carry: u1) u32 {
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return ret;
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}
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pub fn sub(comptime S: bool, cpu: *Arm7tdmi, left: u32, right: u32) u32 {
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const result = left -% right;
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if (S) {
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cpu.cpsr.n.write(result >> 31 & 1 == 1);
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cpu.cpsr.z.write(result == 0);
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cpu.cpsr.c.write(right <= left);
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cpu.cpsr.v.write(((left ^ result) & (~right ^ result)) >> 31 & 1 == 1);
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}
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return result;
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}
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fn newAdd(didOverflow: *bool, left: u32, right: u32) u32 {
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pub fn add(overflow: *bool, left: u32, right: u32) u32 {
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var ret: u32 = undefined;
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didOverflow.* = @addWithOverflow(u32, left, right, &ret);
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overflow.* = @addWithOverflow(u32, left, right, &ret);
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return ret;
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}
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pub fn add(comptime S: bool, cpu: *Arm7tdmi, left: u32, right: u32) u32 {
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var result: u32 = undefined;
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const didOverflow = @addWithOverflow(u32, left, right, &result);
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if (S) {
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cpu.cpsr.n.write(result >> 31 & 1 == 1);
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cpu.cpsr.z.write(result == 0);
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cpu.cpsr.c.write(didOverflow);
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cpu.cpsr.v.write(((left ^ result) & (right ^ result)) >> 31 & 1 == 1);
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}
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return result;
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}
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pub fn newAdc(didOverflow: *bool, left: u32, right: u32, old_carry: u1) u32 {
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pub fn adc(overflow: *bool, left: u32, right: u32, old_carry: u1) u32 {
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var ret: u32 = undefined;
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const did = @addWithOverflow(u32, left, right, &ret);
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const overflow = @addWithOverflow(u32, ret, old_carry, &ret);
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const first = @addWithOverflow(u32, left, right, &ret);
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const second = @addWithOverflow(u32, ret, old_carry, &ret);
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didOverflow.* = did or overflow;
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overflow.* = first or second;
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return ret;
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}
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pub fn cmp(cpu: *Arm7tdmi, left: u32, right: u32) void {
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const result = left -% right;
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cpu.cpsr.n.write(result >> 31 & 1 == 1);
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cpu.cpsr.z.write(result == 0);
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cpu.cpsr.c.write(right <= left);
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cpu.cpsr.v.write(((left ^ result) & (~right ^ result)) >> 31 & 1 == 1);
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}
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pub fn setLogicOpFlags(comptime S: bool, cpu: *Arm7tdmi, result: u32) void {
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if (S) {
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cpu.cpsr.n.write(result >> 31 & 1 == 1);
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cpu.cpsr.z.write(result == 0);
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// C set by Barrel Shifter, V is unaffected
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}
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}
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fn undefinedTestBehaviour(cpu: *Arm7tdmi) void {
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@setCold(true);
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cpu.setCpsrNoFlush(cpu.spsr.raw);
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@ -2,7 +2,7 @@ const Bus = @import("../../Bus.zig");
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const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
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const InstrFn = @import("../../cpu.zig").thumb.InstrFn;
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const adc = @import("../arm/data_processing.zig").newAdc;
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const adc = @import("../arm/data_processing.zig").adc;
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const sbc = @import("../arm/data_processing.zig").sbc;
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const lsl = @import("../barrel_shifter.zig").logicalLeft;
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@ -17,25 +17,28 @@ pub fn fmt4(comptime op: u4) InstrFn {
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const rd = opcode & 0x7;
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const carry = @boolToInt(cpu.cpsr.c.read());
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const op1 = cpu.r[rd];
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const op2 = cpu.r[rs];
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var result: u32 = undefined;
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var didOverflow: bool = undefined;
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var overflow: bool = undefined;
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switch (op) {
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0x0 => result = cpu.r[rd] & cpu.r[rs], // AND
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0x1 => result = cpu.r[rd] ^ cpu.r[rs], // EOR
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0x2 => result = lsl(true, &cpu.cpsr, cpu.r[rd], @truncate(u8, cpu.r[rs])), // LSL
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0x3 => result = lsr(true, &cpu.cpsr, cpu.r[rd], @truncate(u8, cpu.r[rs])), // LSR
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0x4 => result = asr(true, &cpu.cpsr, cpu.r[rd], @truncate(u8, cpu.r[rs])), // ASR
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0x5 => result = adc(&didOverflow, cpu.r[rd], cpu.r[rs], carry), // ADC
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0x6 => result = sbc(cpu.r[rd], cpu.r[rs], carry), // SBC
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0x7 => result = ror(true, &cpu.cpsr, cpu.r[rd], @truncate(u8, cpu.r[rs])), // ROR
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0x8 => result = cpu.r[rd] & cpu.r[rs], // TST
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0x9 => result = 0 -% cpu.r[rs], // NEG
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0xA => result = cpu.r[rd] -% cpu.r[rs], // CMP
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0xB => didOverflow = @addWithOverflow(u32, cpu.r[rd], cpu.r[rs], &result), // CMN
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0xC => result = cpu.r[rd] | cpu.r[rs], // ORR
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0xD => result = @truncate(u32, @as(u64, cpu.r[rs]) * @as(u64, cpu.r[rd])),
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0xE => result = cpu.r[rd] & ~cpu.r[rs],
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0xF => result = ~cpu.r[rs],
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0x0 => result = op1 & op2, // AND
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0x1 => result = op1 ^ op2, // EOR
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0x2 => result = lsl(true, &cpu.cpsr, op1, @truncate(u8, op2)), // LSL
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0x3 => result = lsr(true, &cpu.cpsr, op1, @truncate(u8, op2)), // LSR
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0x4 => result = asr(true, &cpu.cpsr, op1, @truncate(u8, op2)), // ASR
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0x5 => result = adc(&overflow, op1, op2, carry), // ADC
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0x6 => result = sbc(op1, op2, carry), // SBC
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0x7 => result = ror(true, &cpu.cpsr, op1, @truncate(u8, op2)), // ROR
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0x8 => result = op1 & op2, // TST
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0x9 => result = 0 -% op2, // NEG
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0xA => result = op1 -% op2, // CMP
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0xB => overflow = @addWithOverflow(u32, op1, op2, &result), // CMN
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0xC => result = op1 | op2, // ORR
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0xD => result = @truncate(u32, @as(u64, op2) * @as(u64, op1)),
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0xE => result = op1 & ~op2,
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0xF => result = ~op2,
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}
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// Write to Destination Register
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@ -60,16 +63,16 @@ pub fn fmt4(comptime op: u4) InstrFn {
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if (op == 0xA) {
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// CMP specific
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cpu.cpsr.c.write(cpu.r[rs] <= cpu.r[rd]);
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cpu.cpsr.v.write(((cpu.r[rd] ^ result) & (~cpu.r[rs] ^ result)) >> 31 & 1 == 1);
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cpu.cpsr.c.write(op2 <= op1);
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cpu.cpsr.v.write(((op1 ^ result) & (~op2 ^ result)) >> 31 & 1 == 1);
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}
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},
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0x5, 0xB => {
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// ADC, CMN
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cpu.cpsr.n.write(result >> 31 & 1 == 1);
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cpu.cpsr.z.write(result == 0);
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cpu.cpsr.c.write(didOverflow);
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cpu.cpsr.v.write(((cpu.r[rd] ^ result) & (cpu.r[rs] ^ result)) >> 31 & 1 == 1);
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cpu.cpsr.c.write(overflow);
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cpu.cpsr.v.write(((op1 ^ result) & (op2 ^ result)) >> 31 & 1 == 1);
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// FIXME: Pretty sure CMN Is the same
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},
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@ -78,16 +81,16 @@ pub fn fmt4(comptime op: u4) InstrFn {
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cpu.cpsr.n.write(result >> 31 & 1 == 1);
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cpu.cpsr.z.write(result == 0);
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const subtrahend = @as(u64, cpu.r[rs]) -% carry +% 1;
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cpu.cpsr.c.write(subtrahend <= cpu.r[rd]);
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cpu.cpsr.v.write(((cpu.r[rd] ^ result) & (~cpu.r[rs] ^ result)) >> 31 & 1 == 1);
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const subtrahend = @as(u64, op2) -% carry +% 1;
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cpu.cpsr.c.write(subtrahend <= op1);
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cpu.cpsr.v.write(((op1 ^ result) & (~op2 ^ result)) >> 31 & 1 == 1);
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},
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0x9 => {
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// NEG
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cpu.cpsr.n.write(result >> 31 & 1 == 1);
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cpu.cpsr.z.write(result == 0);
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cpu.cpsr.c.write(cpu.r[rs] <= 0);
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cpu.cpsr.v.write(((0 ^ result) & (~cpu.r[rs] ^ result)) >> 31 & 1 == 1);
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cpu.cpsr.c.write(op2 <= 0);
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cpu.cpsr.v.write(((0 ^ result) & (~op2 ^ result)) >> 31 & 1 == 1);
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},
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0xD => {
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// Multiplication
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@ -3,12 +3,12 @@ const std = @import("std");
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const Bus = @import("../../Bus.zig");
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const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
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const InstrFn = @import("../../cpu.zig").thumb.InstrFn;
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const shifter = @import("../barrel_shifter.zig");
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const add = @import("../arm/data_processing.zig").add;
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const sub = @import("../arm/data_processing.zig").sub;
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const cmp = @import("../arm/data_processing.zig").cmp;
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const setLogicOpFlags = @import("../arm/data_processing.zig").setLogicOpFlags;
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const lsl = @import("../barrel_shifter.zig").logicalLeft;
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const lsr = @import("../barrel_shifter.zig").logicalRight;
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const asr = @import("../barrel_shifter.zig").arithmeticRight;
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pub fn fmt1(comptime op: u2, comptime offset: u5) InstrFn {
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return struct {
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@ -22,7 +22,7 @@ pub fn fmt1(comptime op: u2, comptime offset: u5) InstrFn {
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if (offset == 0) {
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break :blk cpu.r[rs];
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} else {
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break :blk shifter.logicalLeft(true, &cpu.cpsr, cpu.r[rs], offset);
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break :blk lsl(true, &cpu.cpsr, cpu.r[rs], offset);
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}
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},
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0b01 => blk: {
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@ -31,7 +31,7 @@ pub fn fmt1(comptime op: u2, comptime offset: u5) InstrFn {
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cpu.cpsr.c.write(cpu.r[rs] >> 31 & 1 == 1);
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break :blk @as(u32, 0);
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} else {
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break :blk shifter.logicalRight(true, &cpu.cpsr, cpu.r[rs], offset);
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break :blk lsr(true, &cpu.cpsr, cpu.r[rs], offset);
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}
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},
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0b10 => blk: {
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@ -40,7 +40,7 @@ pub fn fmt1(comptime op: u2, comptime offset: u5) InstrFn {
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cpu.cpsr.c.write(cpu.r[rs] >> 31 & 1 == 1);
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break :blk @bitCast(u32, @bitCast(i32, cpu.r[rs]) >> 31);
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} else {
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break :blk shifter.arithmeticRight(true, &cpu.cpsr, cpu.r[rs], offset);
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break :blk asr(true, &cpu.cpsr, cpu.r[rs], offset);
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}
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},
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else => cpu.panic("[CPU/THUMB.1] 0b{b:0>2} is not a valid op", .{op}),
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@ -48,7 +48,10 @@ pub fn fmt1(comptime op: u2, comptime offset: u5) InstrFn {
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// Equivalent to an ARM MOVS
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cpu.r[rd] = result;
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setLogicOpFlags(true, cpu, result);
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// Write Flags
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cpu.cpsr.n.write(result >> 31 & 1 == 1);
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cpu.cpsr.z.write(result == 0);
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}
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}.inner;
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}
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@ -59,35 +62,49 @@ pub fn fmt5(comptime op: u2, comptime h1: u1, comptime h2: u1) InstrFn {
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const rs = @as(u4, h2) << 3 | (opcode >> 3 & 0x7);
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const rd = @as(u4, h1) << 3 | (opcode & 0x7);
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const rs_value = if (rs == 0xF) cpu.r[rs] & ~@as(u32, 1) else cpu.r[rs];
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const rd_value = if (rd == 0xF) cpu.r[rd] & ~@as(u32, 1) else cpu.r[rd];
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const op1 = cpu.r[rd];
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const op2 = cpu.r[rs];
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var result: u32 = undefined;
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var overflow: bool = undefined;
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switch (op) {
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0b00 => {
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// ADD
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const sum = add(false, cpu, rd_value, rs_value);
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cpu.r[rd] = if (rd == 0xF) sum & ~@as(u32, 1) else sum;
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},
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0b01 => cmp(cpu, rd_value, rs_value), // CMP
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0b10 => {
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// MOV
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cpu.r[rd] = if (rd == 0xF) rs_value & ~@as(u32, 1) else rs_value;
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},
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0b00 => result = add(&overflow, op1, op2), // ADD
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0b01 => result = op1 -% op2, // CMP
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0b10 => result = op2, // MOV
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0b11 => {},
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}
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// Write to Destination Register
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switch (op) {
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0b01 => {}, // Test Instruction
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0b11 => {
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// BX
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const thumb = rs_value & 1 == 1;
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cpu.r[15] = rs_value & ~@as(u32, 1);
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const is_thumb = op2 & 1 == 1;
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cpu.r[15] = op2 & ~@as(u32, 1);
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cpu.cpsr.t.write(thumb);
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if (thumb) cpu.pipe.reload(u16, cpu) else cpu.pipe.reload(u32, cpu);
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// TODO: We shouldn't need to worry about the if statement
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// below, because in BX, rd SBZ (and H1 is guaranteed to be 0)
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return;
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cpu.cpsr.t.write(is_thumb);
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if (is_thumb) cpu.pipe.reload(u16, cpu) else cpu.pipe.reload(u32, cpu);
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},
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else => {
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cpu.r[rd] = result;
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if (rd == 0xF) {
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cpu.r[15] &= ~@as(u32, 1);
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cpu.pipe.reload(u16, cpu);
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}
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},
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}
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if (rd == 0xF) cpu.pipe.reload(u16, cpu);
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// Write Flags
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switch (op) {
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0b01 => {
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// CMP
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cpu.cpsr.n.write(result >> 31 & 1 == 1);
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cpu.cpsr.z.write(result == 0);
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cpu.cpsr.c.write(op2 <= op1);
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cpu.cpsr.v.write(((op1 ^ result) & (~op2 ^ result)) >> 31 & 1 == 1);
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},
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0b00, 0b10, 0b11 => {}, // MOV and Branch Instruction
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}
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}
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}.inner;
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}
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@ -97,21 +114,28 @@ pub fn fmt2(comptime I: bool, is_sub: bool, rn: u3) InstrFn {
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fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void {
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const rs = opcode >> 3 & 0x7;
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const rd = @truncate(u3, opcode);
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const op1 = cpu.r[rs];
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const op2: u32 = if (I) rn else cpu.r[rn];
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if (is_sub) {
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// SUB
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cpu.r[rd] = if (I) blk: {
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break :blk sub(true, cpu, cpu.r[rs], rn);
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} else blk: {
|
||||
break :blk sub(true, cpu, cpu.r[rs], cpu.r[rn]);
|
||||
};
|
||||
const result = op1 -% op2;
|
||||
cpu.r[rd] = result;
|
||||
|
||||
cpu.cpsr.n.write(result >> 31 & 1 == 1);
|
||||
cpu.cpsr.z.write(result == 0);
|
||||
cpu.cpsr.c.write(op2 <= op1);
|
||||
cpu.cpsr.v.write(((op1 ^ result) & (~op2 ^ result)) >> 31 & 1 == 1);
|
||||
} else {
|
||||
// ADD
|
||||
cpu.r[rd] = if (I) blk: {
|
||||
break :blk add(true, cpu, cpu.r[rs], rn);
|
||||
} else blk: {
|
||||
break :blk add(true, cpu, cpu.r[rs], cpu.r[rn]);
|
||||
};
|
||||
var overflow: bool = undefined;
|
||||
const result = add(&overflow, op1, op2);
|
||||
cpu.r[rd] = result;
|
||||
|
||||
cpu.cpsr.n.write(result >> 31 & 1 == 1);
|
||||
cpu.cpsr.z.write(result == 0);
|
||||
cpu.cpsr.c.write(overflow);
|
||||
cpu.cpsr.v.write(((op1 ^ result) & (op2 ^ result)) >> 31 & 1 == 1);
|
||||
}
|
||||
}
|
||||
}.inner;
|
||||
|
|
@ -120,17 +144,36 @@ pub fn fmt2(comptime I: bool, is_sub: bool, rn: u3) InstrFn {
|
|||
pub fn fmt3(comptime op: u2, comptime rd: u3) InstrFn {
|
||||
return struct {
|
||||
fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void {
|
||||
const offset = @truncate(u8, opcode);
|
||||
const op1 = cpu.r[rd];
|
||||
const op2: u32 = opcode & 0xFF; // Offset
|
||||
|
||||
var overflow: bool = undefined;
|
||||
const result: u32 = switch (op) {
|
||||
0b00 => op2, // MOV
|
||||
0b01 => op1 -% op2, // CMP
|
||||
0b10 => add(&overflow, op1, op2), // ADD
|
||||
0b11 => op1 -% op2, // SUB
|
||||
};
|
||||
|
||||
// Write to Register
|
||||
if (op != 0b01) cpu.r[rd] = result;
|
||||
|
||||
// Write Flags
|
||||
cpu.cpsr.n.write(result >> 31 & 1 == 1);
|
||||
cpu.cpsr.z.write(result == 0);
|
||||
|
||||
switch (op) {
|
||||
0b00 => {
|
||||
// MOV
|
||||
cpu.r[rd] = offset;
|
||||
setLogicOpFlags(true, cpu, offset);
|
||||
0b00 => {}, // MOV | C set by Barrel Shifter, V is unaffected
|
||||
0b01, 0b11 => {
|
||||
// SUB, CMP
|
||||
cpu.cpsr.c.write(op2 <= op1);
|
||||
cpu.cpsr.v.write(((op1 ^ result) & (~op2 ^ result)) >> 31 & 1 == 1);
|
||||
},
|
||||
0b10 => {
|
||||
// ADD
|
||||
cpu.cpsr.c.write(overflow);
|
||||
cpu.cpsr.v.write(((op1 ^ result) & (op2 ^ result)) >> 31 & 1 == 1);
|
||||
},
|
||||
0b01 => cmp(cpu, cpu.r[rd], offset), // CMP
|
||||
0b10 => cpu.r[rd] = add(true, cpu, cpu.r[rd], offset), // ADD
|
||||
0b11 => cpu.r[rd] = sub(true, cpu, cpu.r[rd], offset), // SUB
|
||||
}
|
||||
}
|
||||
}.inner;
|
||||
|
|
|
|||
Loading…
Reference in New Issue