feat(cpu): implement like 1 THUMB instruction
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4606a1ab25
commit
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17
src/cpu.zig
17
src/cpu.zig
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@ -7,6 +7,7 @@ const Bit = @import("bitfield").Bit;
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const Bitfield = @import("bitfield").Bitfield;
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const Bitfield = @import("bitfield").Bitfield;
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const Scheduler = @import("scheduler.zig").Scheduler;
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const Scheduler = @import("scheduler.zig").Scheduler;
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// ARM Instruction Groups
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const dataProcessing = @import("cpu/arm/data_processing.zig").dataProcessing;
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const dataProcessing = @import("cpu/arm/data_processing.zig").dataProcessing;
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const psrTransfer = @import("cpu/arm/psr_transfer.zig").psrTransfer;
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const psrTransfer = @import("cpu/arm/psr_transfer.zig").psrTransfer;
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const singleDataTransfer = @import("cpu/arm/single_data_transfer.zig").singleDataTransfer;
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const singleDataTransfer = @import("cpu/arm/single_data_transfer.zig").singleDataTransfer;
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@ -15,6 +16,9 @@ const blockDataTransfer = @import("cpu/arm/block_data_transfer.zig").blockDataTr
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const branch = @import("cpu/arm/branch.zig").branch;
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const branch = @import("cpu/arm/branch.zig").branch;
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const branchAndExchange = @import("cpu/arm/branch.zig").branchAndExchange;
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const branchAndExchange = @import("cpu/arm/branch.zig").branchAndExchange;
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// THUMB Instruction Groups
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const format3 = @import("cpu/thumb/format3.zig").format3;
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pub const ArmInstrFn = fn (*Arm7tdmi, *Bus, u32) void;
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pub const ArmInstrFn = fn (*Arm7tdmi, *Bus, u32) void;
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pub const ThumbInstrFn = fn (*Arm7tdmi, *Bus, u16) void;
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pub const ThumbInstrFn = fn (*Arm7tdmi, *Bus, u16) void;
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const arm_lut: [0x1000]ArmInstrFn = armPopulate();
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const arm_lut: [0x1000]ArmInstrFn = armPopulate();
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@ -141,12 +145,17 @@ fn checkCond(cpsr: PSR, cond: u4) bool {
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fn thumbPopulate() [0x400]ThumbInstrFn {
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fn thumbPopulate() [0x400]ThumbInstrFn {
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return comptime {
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return comptime {
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@setEvalBranchQuota(0x800);
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@setEvalBranchQuota(0xC00);
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var lut = [_]ThumbInstrFn{thumbUndefined} ** 0x400;
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var lut = [_]ThumbInstrFn{thumbUndefined} ** 0x400;
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var i: usize = 0;
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var i: usize = 0;
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while (i < lut.len) : (i += 1) {
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while (i < lut.len) : (i += 1) {
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lut[i] = thumbUndefined;
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if (i >> 7 & 0x7 == 0b001) {
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const op = i >> 5 & 0x3;
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const rd = i >> 2 & 0x7;
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lut[i] = format3(op, rd);
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}
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}
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}
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return lut;
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return lut;
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@ -245,10 +254,10 @@ const Mode = enum(u5) {
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fn armUndefined(_: *Arm7tdmi, _: *Bus, opcode: u32) void {
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fn armUndefined(_: *Arm7tdmi, _: *Bus, opcode: u32) void {
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const id = armIdx(opcode);
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const id = armIdx(opcode);
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std.debug.panic("[CPU:ARM] {{0x{X:}}} 0x{X:} is an illegal opcode", .{ id, opcode });
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std.debug.panic("[CPU:ARM] ID: 0x{X:0>3} 0x{X:0>8} is an illegal opcode", .{ id, opcode });
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}
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}
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fn thumbUndefined(_: *Arm7tdmi, _: *Bus, opcode: u16) void {
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fn thumbUndefined(_: *Arm7tdmi, _: *Bus, opcode: u16) void {
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const id = thumbIdx(opcode);
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const id = thumbIdx(opcode);
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std.debug.panic("[CPU:THUMB] {{0x{X:}}} 0x{X:} is an illegal opcode", .{ id, opcode });
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std.debug.panic("[CPU:THUMB] ID: 0b{b:0>10} 0x{X:0>2} is an illegal opcode", .{ id, opcode });
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}
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}
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