feat: Initial Implementation of DMA Audio
This commit is contained in:
parent
e69f4cfafe
commit
f039c891c7
26
src/Bus.zig
26
src/Bus.zig
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@ -1,5 +1,6 @@
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const std = @import("std");
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const std = @import("std");
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const AudioDeviceId = @import("sdl2").SDL_AudioDeviceID;
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const Bios = @import("bus/Bios.zig");
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const Bios = @import("bus/Bios.zig");
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const Ewram = @import("bus/Ewram.zig");
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const Ewram = @import("bus/Ewram.zig");
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const GamePak = @import("bus/GamePak.zig");
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const GamePak = @import("bus/GamePak.zig");
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@ -10,6 +11,7 @@ const Apu = @import("apu.zig").Apu;
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const DmaControllers = @import("bus/dma.zig").DmaControllers;
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const DmaControllers = @import("bus/dma.zig").DmaControllers;
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const Timers = @import("bus/timer.zig").Timers;
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const Timers = @import("bus/timer.zig").Timers;
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const Scheduler = @import("scheduler.zig").Scheduler;
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const Scheduler = @import("scheduler.zig").Scheduler;
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const FilePaths = @import("util.zig").FilePaths;
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const io = @import("bus/io.zig");
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const io = @import("bus/io.zig");
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const Allocator = std.mem.Allocator;
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const Allocator = std.mem.Allocator;
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@ -33,12 +35,12 @@ io: Io,
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sched: *Scheduler,
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sched: *Scheduler,
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pub fn init(alloc: Allocator, sched: *Scheduler, rom_path: []const u8, bios_path: ?[]const u8, save_path: ?[]const u8) !Self {
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pub fn init(alloc: Allocator, sched: *Scheduler, dev: AudioDeviceId, paths: FilePaths) !Self {
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return Self{
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return Self{
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.pak = try GamePak.init(alloc, rom_path, save_path),
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.pak = try GamePak.init(alloc, paths.rom, paths.save),
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.bios = try Bios.init(alloc, bios_path),
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.bios = try Bios.init(alloc, paths.bios),
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.ppu = try Ppu.init(alloc, sched),
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.ppu = try Ppu.init(alloc, sched),
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.apu = Apu.init(),
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.apu = Apu.init(dev),
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.iwram = try Iwram.init(alloc),
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.iwram = try Iwram.init(alloc),
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.ewram = try Ewram.init(alloc),
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.ewram = try Ewram.init(alloc),
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.dma = DmaControllers.init(),
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.dma = DmaControllers.init(),
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@ -56,6 +58,22 @@ pub fn deinit(self: Self) void {
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self.ppu.deinit();
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self.ppu.deinit();
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}
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}
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pub fn handleDMATransfers(self: *Self) void {
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while (self.isDmaRunning()) {
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if (self.dma._1.step(self)) continue;
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if (self.dma._0.step(self)) continue;
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if (self.dma._2.step(self)) continue;
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if (self.dma._3.step(self)) continue;
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}
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}
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fn isDmaRunning(self: *const Self) bool {
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return self.dma._0.active or
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self.dma._1.active or
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self.dma._2.active or
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self.dma._3.active;
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}
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pub fn read(self: *const Self, comptime T: type, address: u32) T {
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pub fn read(self: *const Self, comptime T: type, address: u32) T {
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const page = @truncate(u8, address >> 24);
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const page = @truncate(u8, address >> 24);
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const align_addr = alignAddress(T, address);
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const align_addr = alignAddress(T, address);
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117
src/apu.zig
117
src/apu.zig
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@ -1,8 +1,13 @@
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const std = @import("std");
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const std = @import("std");
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const SDL = @import("sdl2");
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const io = @import("bus/io.zig");
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const Arm7tdmi = @import("cpu.zig").Arm7tdmi;
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const SoundFifo = std.fifo.LinearFifo(u8, .{ .Static = 0x20 });
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const SoundFifo = std.fifo.LinearFifo(u8, .{ .Static = 0x20 });
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const AudioDeviceId = SDL.SDL_AudioDeviceID;
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const io = @import("bus/io.zig");
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const intToBytes = @import("util.zig").intToBytes;
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const log = std.log.scoped(.APU);
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pub const Apu = struct {
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pub const Apu = struct {
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const Self = @This();
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const Self = @This();
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@ -11,30 +16,45 @@ pub const Apu = struct {
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ch2: Tone,
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ch2: Tone,
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ch3: Wave,
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ch3: Wave,
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ch4: Noise,
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ch4: Noise,
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chA: DmaSound,
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chA: DmaSound(.A),
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chB: DmaSound,
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chB: DmaSound(.B),
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bias: io.SoundBias,
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bias: io.SoundBias,
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ch_vol_cnt: io.ChannelVolumeControl,
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ch_vol_cnt: io.ChannelVolumeControl,
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dma_cnt: io.DmaSoundControl,
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dma_cnt: io.DmaSoundControl,
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cnt: io.SoundControl,
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cnt: io.SoundControl,
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pub fn init() Self {
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dev: AudioDeviceId,
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pub fn init(dev: AudioDeviceId) Self {
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return .{
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return .{
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.ch1 = ToneSweep.init(),
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.ch1 = ToneSweep.init(),
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.ch2 = Tone.init(),
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.ch2 = Tone.init(),
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.ch3 = Wave.init(),
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.ch3 = Wave.init(),
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.ch4 = Noise.init(),
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.ch4 = Noise.init(),
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.chA = DmaSound.init(),
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.chA = DmaSound(.A).init(),
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.chB = DmaSound.init(),
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.chB = DmaSound(.B).init(),
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.ch_vol_cnt = .{ .raw = 0 },
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.ch_vol_cnt = .{ .raw = 0 },
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.dma_cnt = .{ .raw = 0 },
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.dma_cnt = .{ .raw = 0 },
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.cnt = .{ .raw = 0 },
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.cnt = .{ .raw = 0 },
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.bias = .{ .raw = 0x0200 },
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.bias = .{ .raw = 0x0200 },
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.dev = dev,
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};
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};
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}
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}
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pub fn setDmaCnt(self: *Self, value: u16) void {
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const new: io.DmaSoundControl = .{ .raw = value };
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// Reinitializing instead of resetting is fine because
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// the FIFOs I'm using are stack allocated and 0x20 bytes big
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if (new.sa_reset.read()) self.chA.fifo = SoundFifo.init();
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if (new.sb_reset.read()) self.chB.fifo = SoundFifo.init();
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self.dma_cnt = new;
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}
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pub fn setSoundCntX(self: *Self, value: bool) void {
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pub fn setSoundCntX(self: *Self, value: bool) void {
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self.cnt.apu_enable.write(value);
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self.cnt.apu_enable.write(value);
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}
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}
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@ -50,6 +70,21 @@ pub const Apu = struct {
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pub fn setBiasHigh(self: *Self, byte: u8) void {
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pub fn setBiasHigh(self: *Self, byte: u8) void {
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self.bias.raw = (@as(u16, byte) << 8) | (self.bias.raw & 0xFF);
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self.bias.raw = (@as(u16, byte) << 8) | (self.bias.raw & 0xFF);
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}
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}
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pub fn handleTimerOverflow(self: *Self, kind: DmaSoundKind, cpu: *Arm7tdmi) void {
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if (!self.cnt.apu_enable.read()) return;
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const samples = switch (kind) {
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.A => blk: {
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break :blk self.chA.handleTimerOverflow(cpu, self.dma_cnt);
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},
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.B => blk: {
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break :blk self.chB.handleTimerOverflow(cpu, self.dma_cnt);
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},
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};
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_ = SDL.SDL_QueueAudio(self.dev, &samples, 2);
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}
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};
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};
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const ToneSweep = struct {
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const ToneSweep = struct {
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@ -162,16 +197,66 @@ const Noise = struct {
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};
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};
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}
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}
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};
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};
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const DmaSound = struct {
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const Self = @This();
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a: SoundFifo,
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pub fn DmaSound(comptime kind: DmaSoundKind) type {
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b: SoundFifo,
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return struct {
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const Self = @This();
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fn init() Self {
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fifo: SoundFifo,
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return .{
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.a = SoundFifo.init(),
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kind: DmaSoundKind,
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.b = SoundFifo.init(),
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};
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fn init() Self {
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}
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return .{ .fifo = SoundFifo.init(), .kind = kind };
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}
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pub fn push(self: *Self, value: u32) void {
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self.fifo.write(&intToBytes(u32, value)) catch {};
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}
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pub fn pop(self: *Self) u8 {
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return self.fifo.readItem() orelse 0;
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}
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pub fn len(self: *const Self) usize {
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return self.fifo.readableLength();
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}
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pub fn handleTimerOverflow(self: *Self, cpu: *Arm7tdmi, cnt: io.DmaSoundControl) [2]u8 {
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const sample = self.pop();
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var left: u8 = 0;
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var right: u8 = 0;
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var fifo_addr: u32 = undefined;
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switch (kind) {
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.A => {
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const vol = @boolToInt(!cnt.sa_vol.read()); // if unset, vol is 50%
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if (cnt.sa_left_enable.read()) left = sample >> vol;
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if (cnt.sa_right_enable.read()) right = sample >> vol;
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fifo_addr = 0x0400_00A0;
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},
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.B => {
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const vol = @boolToInt(!cnt.sb_vol.read()); // if unset, vol is 50%
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if (cnt.sb_left_enable.read()) left = sample >> vol;
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if (cnt.sb_right_enable.read()) right = sample >> vol;
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fifo_addr = 0x0400_00A4;
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},
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}
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if (self.len() <= 15) {
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cpu.bus.dma._1.enableSoundDma(fifo_addr);
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cpu.bus.dma._2.enableSoundDma(fifo_addr);
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}
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return .{ left, right };
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}
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};
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}
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const DmaSoundKind = enum {
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A,
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B,
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};
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};
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@ -53,10 +53,13 @@ fn DmaController(comptime id: u2) type {
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/// Internal. Word Count
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/// Internal. Word Count
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_word_count: if (id == 3) u16 else u14,
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_word_count: if (id == 3) u16 else u14,
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// Internal. FIFO Word Count
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_fifo_word_count: u8,
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/// Some DMA Transfers are enabled during Hblank / VBlank and / or
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/// Some DMA Transfers are enabled during Hblank / VBlank and / or
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/// have delays. Thefore bit 15 of DMACNT isn't actually something
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/// have delays. Thefore bit 15 of DMACNT isn't actually something
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/// we can use to control when we do or do not execute a step in a DMA Transfer
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/// we can use to control when we do or do not execute a step in a DMA Transfer
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enabled: bool,
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active: bool,
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pub fn init() Self {
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pub fn init() Self {
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return .{
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return .{
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@ -70,7 +73,8 @@ fn DmaController(comptime id: u2) type {
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._sad = 0,
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._sad = 0,
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._dad = 0,
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._dad = 0,
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._word_count = 0,
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._word_count = 0,
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.enabled = false,
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._fifo_word_count = 4,
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.active = false,
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};
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};
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}
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}
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@ -96,7 +100,7 @@ fn DmaController(comptime id: u2) type {
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self._word_count = if (self.word_count == 0) std.math.maxInt(@TypeOf(self._word_count)) else self.word_count;
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self._word_count = if (self.word_count == 0) std.math.maxInt(@TypeOf(self._word_count)) else self.word_count;
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// Only a Start Timing of 00 has a DMA Transfer immediately begin
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// Only a Start Timing of 00 has a DMA Transfer immediately begin
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self.enabled = new.start_timing.read() == 0b00;
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self.active = new.start_timing.read() == 0b00;
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}
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}
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self.cnt.raw = halfword;
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self.cnt.raw = halfword;
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@ -108,27 +112,50 @@ fn DmaController(comptime id: u2) type {
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}
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}
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pub inline fn check(self: *Self, bus: *Bus) bool {
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pub inline fn check(self: *Self, bus: *Bus) bool {
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if (!self.enabled) return false; // FIXME: Check CNT register?
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if (!self.active) return false; // FIXME: Check CNT register?
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self.step(bus);
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self.step(bus);
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return true;
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return true;
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}
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}
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pub fn step(self: *Self, bus: *Bus) void {
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pub fn step(self: *Self, bus: *Bus) bool {
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@setCold(true);
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if (!self.active) return false;
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const sad_adj = std.meta.intToEnum(Adjustment, self.cnt.sad_adj.read()) catch unreachable;
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const sad_adj = std.meta.intToEnum(Adjustment, self.cnt.sad_adj.read()) catch unreachable;
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const dad_adj = std.meta.intToEnum(Adjustment, self.cnt.dad_adj.read()) catch unreachable;
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const dad_adj = std.meta.intToEnum(Adjustment, self.cnt.dad_adj.read()) catch unreachable;
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const is_fifo = (self.id == 1 or self.id == 2) and self.cnt.start_timing.read() == 0b11;
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var offset: u32 = 0;
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// // if (is_fifo) {
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if (self.cnt.transfer_type.read()) {
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// // const offset = @sizeOf(u32);
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offset = @sizeOf(u32); // 32-bit Transfer
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// // bus.write(u32, self._dad, bus.read(u32, self._sad));
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const word = bus.read(u32, self._sad);
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bus.write(u32, self._dad, word);
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// // // TODO: Deduplicate
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// // switch (sad_adj) {
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// // .Increment => self._sad +%= offset,
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// // .Decrement => self._sad -%= offset,
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// // .Fixed => {},
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// // // TODO: Figure out correct behaviour on Illegal Source Addr Control Type
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// // .IncrementReload => std.debug.panic("panic(DmaTransfer): {} is an illegal src addr adjustment type", .{sad_adj}),
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// // }
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// // self._fifo_word_count -= 1;
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// // if (self._fifo_word_count == 0) {
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// // self._fifo_word_count = 4;
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// // self.active = false;
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// // }
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// // return true;
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// // }
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const transfer_type = self.cnt.transfer_type.read() or is_fifo;
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const offset: u32 = if (transfer_type) @sizeOf(u32) else @sizeOf(u16);
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if (transfer_type) {
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bus.write(u32, self._dad, bus.read(u32, self._sad));
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} else {
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} else {
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offset = @sizeOf(u16); // 16-bit Transfer
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bus.write(u16, self._dad, bus.read(u16, self._sad));
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const halfword = bus.read(u16, self._sad);
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bus.write(u16, self._dad, halfword);
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}
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}
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switch (sad_adj) {
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switch (sad_adj) {
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@ -140,10 +167,12 @@ fn DmaController(comptime id: u2) type {
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.IncrementReload => std.debug.panic("panic(DmaTransfer): {} is an illegal src addr adjustment type", .{sad_adj}),
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.IncrementReload => std.debug.panic("panic(DmaTransfer): {} is an illegal src addr adjustment type", .{sad_adj}),
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}
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}
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switch (dad_adj) {
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if (!is_fifo) {
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.Increment, .IncrementReload => self._dad +%= offset,
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switch (dad_adj) {
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.Decrement => self._dad -%= offset,
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.Increment, .IncrementReload => self._dad +%= offset,
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.Fixed => {},
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.Decrement => self._dad -%= offset,
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.Fixed => {},
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}
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}
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}
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self._word_count -= 1;
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self._word_count -= 1;
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@ -165,8 +194,10 @@ fn DmaController(comptime id: u2) type {
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// We want to disable our internal enabled flag regardless of repeat
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// We want to disable our internal enabled flag regardless of repeat
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// because we only want to step A DMA that repeats during it's specific
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// because we only want to step A DMA that repeats during it's specific
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// timing window
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// timing window
|
||||||
self.enabled = false;
|
self.active = false;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
return true;
|
||||||
}
|
}
|
||||||
|
|
||||||
pub fn isBlocking(self: *const Self) bool {
|
pub fn isBlocking(self: *const Self) bool {
|
||||||
|
@ -175,21 +206,31 @@ fn DmaController(comptime id: u2) type {
|
||||||
}
|
}
|
||||||
|
|
||||||
pub fn pollBlankingDma(self: *Self, comptime kind: DmaKind) void {
|
pub fn pollBlankingDma(self: *Self, comptime kind: DmaKind) void {
|
||||||
if (self.enabled) return;
|
if (self.active) return;
|
||||||
|
|
||||||
switch (kind) {
|
switch (kind) {
|
||||||
.HBlank => self.enabled = self.cnt.enabled.read() and self.cnt.start_timing.read() == 0b10,
|
.HBlank => self.active = self.cnt.enabled.read() and self.cnt.start_timing.read() == 0b10,
|
||||||
.VBlank => self.enabled = self.cnt.enabled.read() and self.cnt.start_timing.read() == 0b01,
|
.VBlank => self.active = self.cnt.enabled.read() and self.cnt.start_timing.read() == 0b01,
|
||||||
.Immediate, .Special => {},
|
.Immediate, .Special => {},
|
||||||
}
|
}
|
||||||
|
|
||||||
if (self.cnt.repeat.read() and self.enabled) {
|
if (self.cnt.repeat.read() and self.active) {
|
||||||
self._word_count = if (self.word_count == 0) std.math.maxInt(@TypeOf(self._word_count)) else self.word_count;
|
self._word_count = if (self.word_count == 0) std.math.maxInt(@TypeOf(self._word_count)) else self.word_count;
|
||||||
|
|
||||||
const dad_adj = std.meta.intToEnum(Adjustment, self.cnt.dad_adj.read()) catch unreachable;
|
const dad_adj = std.meta.intToEnum(Adjustment, self.cnt.dad_adj.read()) catch unreachable;
|
||||||
if (dad_adj == .IncrementReload) self._dad = self.dad;
|
if (dad_adj == .IncrementReload) self._dad = self.dad;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
pub fn enableSoundDma(self: *Self, fifo_addr: u32) void {
|
||||||
|
comptime std.debug.assert(id == 1 or id == 2);
|
||||||
|
|
||||||
|
if (self.cnt.enabled.read() and self.cnt.start_timing.read() == 0b11 and self.dad == fifo_addr) {
|
||||||
|
self.active = true;
|
||||||
|
self._word_count = 4;
|
||||||
|
self.cnt.repeat.set();
|
||||||
|
}
|
||||||
|
}
|
||||||
};
|
};
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
@ -143,8 +143,8 @@ pub fn write(bus: *Bus, comptime T: type, address: u32, value: T) void {
|
||||||
0x0400_001C => bus.ppu.setBgOffsets(3, value),
|
0x0400_001C => bus.ppu.setBgOffsets(3, value),
|
||||||
|
|
||||||
// Sound
|
// Sound
|
||||||
0x0400_00A0 => log.warn("Wrote 0x{X:0>8} to FIFO_A", .{value}),
|
0x0400_00A0 => bus.apu.chA.push(value),
|
||||||
0x0400_00A4 => log.warn("Wrote 0x{X:0>8} to FIFO_B", .{value}),
|
0x0400_00A4 => bus.apu.chB.push(value),
|
||||||
|
|
||||||
// DMA Transfers
|
// DMA Transfers
|
||||||
0x0400_00B0 => bus.dma._0.writeSad(value),
|
0x0400_00B0 => bus.dma._0.writeSad(value),
|
||||||
|
@ -208,7 +208,7 @@ pub fn write(bus: *Bus, comptime T: type, address: u32, value: T) void {
|
||||||
|
|
||||||
// Sound
|
// Sound
|
||||||
0x0400_0080 => bus.apu.ch_vol_cnt.raw = value,
|
0x0400_0080 => bus.apu.ch_vol_cnt.raw = value,
|
||||||
0x0400_0082 => bus.apu.dma_cnt.raw = value,
|
0x0400_0082 => bus.apu.setDmaCnt(value),
|
||||||
0x0400_0084 => bus.apu.setSoundCntX(value >> 7 & 1 == 1),
|
0x0400_0084 => bus.apu.setSoundCntX(value >> 7 & 1 == 1),
|
||||||
0x0400_0088 => bus.apu.bias.raw = value,
|
0x0400_0088 => bus.apu.bias.raw = value,
|
||||||
|
|
||||||
|
|
|
@ -103,6 +103,17 @@ fn Timer(comptime id: u2) type {
|
||||||
cpu.handleInterrupt();
|
cpu.handleInterrupt();
|
||||||
}
|
}
|
||||||
|
|
||||||
|
// DMA Sound Things
|
||||||
|
if (id == 0 or id == 1) {
|
||||||
|
const apu = &cpu.bus.apu;
|
||||||
|
|
||||||
|
const a_tim = @boolToInt(apu.dma_cnt.sa_timer.read());
|
||||||
|
const b_tim = @boolToInt(apu.dma_cnt.sb_timer.read());
|
||||||
|
|
||||||
|
if (a_tim == id) apu.handleTimerOverflow(.A, cpu);
|
||||||
|
if (b_tim == id) apu.handleTimerOverflow(.B, cpu);
|
||||||
|
}
|
||||||
|
|
||||||
// Perform Cascade Behaviour
|
// Perform Cascade Behaviour
|
||||||
switch (id) {
|
switch (id) {
|
||||||
0 => if (tim._1.cnt.cascade.read()) {
|
0 => if (tim._1.cnt.cascade.read()) {
|
||||||
|
|
18
src/cpu.zig
18
src/cpu.zig
|
@ -246,15 +246,6 @@ pub const Arm7tdmi = struct {
|
||||||
}
|
}
|
||||||
|
|
||||||
pub fn step(self: *Self) void {
|
pub fn step(self: *Self) void {
|
||||||
// If we're processing a DMA (not Sound or Blanking) the CPU is disabled
|
|
||||||
if (self.handleDMATransfers()) return;
|
|
||||||
|
|
||||||
// If we're halted, the cpu is disabled
|
|
||||||
if (self.bus.io.haltcnt == .Halt) {
|
|
||||||
self.sched.tick += 1;
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
if (self.cpsr.t.read()) {
|
if (self.cpsr.t.read()) {
|
||||||
const opcode = self.thumbFetch();
|
const opcode = self.thumbFetch();
|
||||||
if (enable_logging) if (self.log_file) |file| self.debug_log(file, opcode);
|
if (enable_logging) if (self.log_file) |file| self.debug_log(file, opcode);
|
||||||
|
@ -296,15 +287,6 @@ pub const Arm7tdmi = struct {
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
fn handleDMATransfers(self: *Self) bool {
|
|
||||||
if (self.bus.dma._0.check(self.bus)) return self.bus.dma._0.isBlocking();
|
|
||||||
if (self.bus.dma._1.check(self.bus)) return self.bus.dma._1.isBlocking();
|
|
||||||
if (self.bus.dma._2.check(self.bus)) return self.bus.dma._2.isBlocking();
|
|
||||||
if (self.bus.dma._3.check(self.bus)) return self.bus.dma._3.isBlocking();
|
|
||||||
|
|
||||||
return false;
|
|
||||||
}
|
|
||||||
|
|
||||||
fn thumbFetch(self: *Self) u16 {
|
fn thumbFetch(self: *Self) u16 {
|
||||||
defer self.r[15] += 2;
|
defer self.r[15] += 2;
|
||||||
return self.bus.read(u16, self.r[15]);
|
return self.bus.read(u16, self.r[15]);
|
||||||
|
|
|
@ -46,7 +46,9 @@ pub fn runFrame(sched: *Scheduler, cpu: *Arm7tdmi, bus: *Bus) void {
|
||||||
const frame_end = sched.tick + cycles_per_frame;
|
const frame_end = sched.tick + cycles_per_frame;
|
||||||
|
|
||||||
while (sched.tick < frame_end) {
|
while (sched.tick < frame_end) {
|
||||||
cpu.step();
|
if (bus.io.haltcnt == .Halt) sched.tick += 1;
|
||||||
|
if (bus.io.haltcnt == .Execute) cpu.step();
|
||||||
|
bus.handleDMATransfers();
|
||||||
|
|
||||||
while (sched.tick >= sched.nextTimestamp()) {
|
while (sched.tick >= sched.nextTimestamp()) {
|
||||||
sched.handleEvent(cpu, bus);
|
sched.handleEvent(cpu, bus);
|
||||||
|
|
29
src/main.zig
29
src/main.zig
|
@ -66,11 +66,33 @@ pub fn main() anyerror!void {
|
||||||
defer if (save_path) |path| alloc.free(path);
|
defer if (save_path) |path| alloc.free(path);
|
||||||
log.info("Save Path: {s}", .{save_path});
|
log.info("Save Path: {s}", .{save_path});
|
||||||
|
|
||||||
|
// Initialize SDL
|
||||||
|
const status = SDL.SDL_Init(SDL.SDL_INIT_VIDEO | SDL.SDL_INIT_EVENTS | SDL.SDL_INIT_AUDIO | SDL.SDL_INIT_GAMECONTROLLER);
|
||||||
|
defer SDL.SDL_Quit();
|
||||||
|
if (status < 0) sdlPanic();
|
||||||
|
|
||||||
|
// Initialize SDL Audio
|
||||||
|
var have: SDL.SDL_AudioSpec = undefined;
|
||||||
|
var want = std.mem.zeroes(SDL.SDL_AudioSpec);
|
||||||
|
want.freq = 32768;
|
||||||
|
want.format = SDL.AUDIO_S8;
|
||||||
|
want.channels = 2;
|
||||||
|
want.samples = 0x200;
|
||||||
|
want.callback = null;
|
||||||
|
|
||||||
|
const audio_dev = SDL.SDL_OpenAudioDevice(null, 0, &want, &have, 0);
|
||||||
|
defer SDL.SDL_CloseAudioDevice(audio_dev);
|
||||||
|
if (audio_dev == 0) sdlPanic();
|
||||||
|
|
||||||
|
// Start Playback on the Audio evice
|
||||||
|
SDL.SDL_PauseAudioDevice(audio_dev, 0);
|
||||||
|
|
||||||
// Initialize Emulator
|
// Initialize Emulator
|
||||||
var scheduler = Scheduler.init(alloc);
|
var scheduler = Scheduler.init(alloc);
|
||||||
defer scheduler.deinit();
|
defer scheduler.deinit();
|
||||||
|
|
||||||
var bus = try Bus.init(alloc, &scheduler, rom_path, bios_path, save_path);
|
const paths = .{ .bios = bios_path, .rom = rom_path, .save = save_path };
|
||||||
|
var bus = try Bus.init(alloc, &scheduler, audio_dev, paths);
|
||||||
defer bus.deinit();
|
defer bus.deinit();
|
||||||
|
|
||||||
var cpu = Arm7tdmi.init(&scheduler, &bus);
|
var cpu = Arm7tdmi.init(&scheduler, &bus);
|
||||||
|
@ -91,11 +113,6 @@ pub fn main() anyerror!void {
|
||||||
const emu_thread = try Thread.spawn(.{}, emu.run, .{ .LimitedFPS, &quit, &emu_rate, &scheduler, &cpu, &bus });
|
const emu_thread = try Thread.spawn(.{}, emu.run, .{ .LimitedFPS, &quit, &emu_rate, &scheduler, &cpu, &bus });
|
||||||
defer emu_thread.join();
|
defer emu_thread.join();
|
||||||
|
|
||||||
// Initialize SDL
|
|
||||||
const status = SDL.SDL_Init(SDL.SDL_INIT_VIDEO | SDL.SDL_INIT_EVENTS | SDL.SDL_INIT_AUDIO | SDL.SDL_INIT_GAMECONTROLLER);
|
|
||||||
if (status < 0) sdlPanic();
|
|
||||||
defer SDL.SDL_Quit();
|
|
||||||
|
|
||||||
const title = correctTitle(bus.pak.title);
|
const title = correctTitle(bus.pak.title);
|
||||||
|
|
||||||
var title_buf: [0x20]u8 = std.mem.zeroes([0x20]u8);
|
var title_buf: [0x20]u8 = std.mem.zeroes([0x20]u8);
|
||||||
|
|
|
@ -101,3 +101,9 @@ pub fn fixTitle(alloc: std.mem.Allocator, title: [12]u8) ![]u8 {
|
||||||
|
|
||||||
return buf;
|
return buf;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
pub const FilePaths = struct {
|
||||||
|
rom: []const u8,
|
||||||
|
bios: ?[]const u8,
|
||||||
|
save: ?[]const u8,
|
||||||
|
};
|
||||||
|
|
Loading…
Reference in New Issue