feat: impelemt THUMB open bus
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c03c142b14
commit
eecd78a008
33
src/Bus.zig
33
src/Bus.zig
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@ -84,12 +84,31 @@ pub fn debugRead(self: *const Self, comptime T: type, address: u32) T {
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}
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fn readOpenBus(self: *const Self, comptime T: type, address: u32) T {
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if (self.cpu.?.cpsr.t.read()) {
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log.err("TODO: {} open bus read in THUMB", .{T});
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return 0;
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}
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const r15 = self.cpu.?.r[15];
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const word = if (self.cpu.?.cpsr.t.read()) blk: {
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const page = @truncate(u8, r15 >> 24);
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switch (page) {
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// EWRAM, PALRAM, VRAM, and Game ROM (16-bit)
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0x02, 0x05, 0x06, 0x08...0x0D => {
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const halfword = self.debugRead(u16, r15 + 2);
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break :blk @as(u32, halfword) << 16 | halfword;
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},
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// BIOS or OAM (32-bit)
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0x00, 0x07 => {
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const offset: u32 = if (address & 3 == 0b00) 2 else 0;
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break :blk @as(u32, self.debugRead(u16, (r15 + 2) + offset)) << 16 | self.debugRead(u16, r15 + offset);
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},
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// IWRAM (16-bit but special)
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0x03 => {
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const offset: u32 = if (address & 3 == 0b00) 2 else 0;
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break :blk @as(u32, self.debugRead(u16, (r15 + 2) - offset)) << 16 | self.debugRead(u16, r15 + offset);
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},
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else => unreachable,
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}
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} else self.debugRead(u32, r15 + 4);
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const word = self.debugRead(u32, self.cpu.?.r[15] + 4);
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return @truncate(T, rotr(u32, word, 8 * (address & 3)));
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}
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@ -152,7 +171,7 @@ pub fn write(self: *Self, comptime T: type, address: u32, value: T) void {
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0x07 => self.ppu.oam.write(T, align_addr, value),
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// External Memory (Game Pak)
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0x08...0x0D => {},
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0x08...0x0D => {}, // EEPROM
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0x0E...0x0F => {
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const rotate_by = switch (T) {
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u32 => address & 3,
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@ -163,7 +182,7 @@ pub fn write(self: *Self, comptime T: type, address: u32, value: T) void {
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self.pak.backup.write(address, @truncate(u8, rotr(T, value, 8 * rotate_by)));
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},
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else => undWrite("Tried to write {} 0x{X:} to 0x{X:0>8}", .{ T, value, address }),
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else => {},
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}
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}
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