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fix: advance r15, even when the pipeline is reloaded from the scheduler 

The PC would fall behind whenever an IRQ was called because the pipeline
was reloaded (+8 to PC), however that was never actually done by any code

Now, the PC is always incremented when the pipeline is reloaded
This commit is contained in:
Rekai Nyangadzayi Musuka 2022-10-21 05:13:07 -03:00
parent d8c397248f
commit e29c20019d
1 changed files with 3 additions and 2 deletions
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5
src/core/cpu.zig
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@ -455,8 +455,7 @@ pub const Arm7tdmi = struct {
} }
} }
if (self.pipe.flushed) self.r[15] += if (self.cpsr.t.read()) 2 else @as(u32, 4); if (!self.pipe.flushed) self.r[15] += if (self.cpsr.t.read()) 2 else @as(u32, 4);
self.r[15] += if (self.cpsr.t.read()) 2 else @as(u32, 4);
self.pipe.flushed = false; self.pipe.flushed = false;
} }
@ -703,6 +702,8 @@ const Pipline = struct {
self.stage[0] = cpu.bus.read(T, cpu.r[15]); self.stage[0] = cpu.bus.read(T, cpu.r[15]);
self.stage[1] = cpu.bus.read(T, cpu.r[15] + if (T == u32) 4 else @as(u32, 2)); self.stage[1] = cpu.bus.read(T, cpu.r[15] + if (T == u32) 4 else @as(u32, 2));
cpu.r[15] += if (T == u32) 8 else @as(u32, 4);
self.flushed = true; self.flushed = true;
} }
}; };