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fix: don't fake the pipeline in swi

This commit is contained in:
Rekai Nyangadzayi Musuka 2022-07-02 10:09:44 -03:00
parent 74f1fbc8fd
commit e17e9fb703
2 changed files with 6 additions and 4 deletions
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5
src/cpu/arm/software_interrupt.zig
View File

@ -6,7 +6,7 @@ pub fn armSoftwareInterrupt() InstrFn {
return struct {
fn inner(cpu: *Arm7tdmi, _: *Bus, _: u32) void {
// Copy Values from Current Mode
const r15 = cpu.r[15];
const ret_addr = cpu.r[15] - 4;
const cpsr = cpu.cpsr.raw;
// Switch Mode
@ -14,9 +14,10 @@ pub fn armSoftwareInterrupt() InstrFn {
cpu.cpsr.t.write(false); // Force ARM Mode
cpu.cpsr.i.write(true); // Disable normal interrupts
cpu.r[14] = r15; // Resume Execution
cpu.r[14] = ret_addr; // Resume Execution
cpu.spsr.raw = cpsr; // Previous mode CPSR
cpu.r[15] = 0x0000_0008;
cpu.pipe.flush();
}
}.inner;
}

5
src/cpu/thumb/software_interrupt.zig
View File

@ -6,7 +6,7 @@ pub fn thumbSoftwareInterrupt() InstrFn {
return struct {
fn inner(cpu: *Arm7tdmi, _: *Bus, _: u16) void {
// Copy Values from Current Mode
const r15 = cpu.r[15];
const ret_addr = cpu.r[15] - 2;
const cpsr = cpu.cpsr.raw;
// Switch Mode
@ -14,9 +14,10 @@ pub fn thumbSoftwareInterrupt() InstrFn {
cpu.cpsr.t.write(false); // Force ARM Mode
cpu.cpsr.i.write(true); // Disable normal interrupts
cpu.r[14] = r15; // Resume Execution
cpu.r[14] = ret_addr; // Resume Execution
cpu.spsr.raw = cpsr; // Previous mode CPSR
cpu.r[15] = 0x0000_0008;
cpu.pipe.flush();
}
}.inner;
}