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feat(dma): Implement DMA Latch 

Regressions in DMA Tests, need to be solved
This commit is contained in:
Rekai Nyangadzayi Musuka 2022-10-22 19:35:51 -03:00
parent 22979d9450
commit db681d402f
1 changed files with 10 additions and 2 deletions
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12
src/core/bus/dma.zig
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@ -11,6 +11,8 @@ const log = std.log.scoped(.DmaTransfer);
const setHi = util.setHi;
const setLo = util.setLo;
const rotr = @import("../../util.zig").rotr;
pub fn create() DmaTuple {
return .{ DmaController(0).init(), DmaController(1).init(), DmaController(2).init(), DmaController(3).init() };
}
@ -112,6 +114,8 @@ fn DmaController(comptime id: u2) type {
/// Note: Use writeControl instead of manipulating cnt directly.
cnt: DmaControl,
/// Internal. The last successfully read value
data_latch: u32,
/// Internal. Currrent Source Address
sad_latch: u32,
/// Internal. Current Destination Address
@ -134,6 +138,8 @@ fn DmaController(comptime id: u2) type {
// Internals
.sad_latch = 0,
.dad_latch = 0,
.data_latch = 0,
._word_count = 0,
.in_progress = false,
};
@ -183,9 +189,11 @@ fn DmaController(comptime id: u2) type {
const mask = if (transfer_type) ~@as(u32, 3) else ~@as(u32, 1);
if (transfer_type) {
cpu.bus.write(u32, self.dad_latch & mask, cpu.bus.read(u32, self.sad_latch & mask));
if (self.sad_latch & mask > 0x0200_0000) self.data_latch = cpu.bus.read(u32, self.sad_latch & mask);
cpu.bus.write(u32, self.dad_latch & mask, self.data_latch);
} else {
cpu.bus.write(u16, self.dad_latch & mask, cpu.bus.read(u16, self.sad_latch & mask));
if (self.sad_latch & mask > 0x0200_0000) self.data_latch = cpu.bus.read(u16, self.sad_latch & mask);
cpu.bus.write(u16, self.dad_latch & mask, @truncate(u16, rotr(u32, self.data_latch, 8 * (self.dad_latch & 3))));
}
switch (sad_adj) {